X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fcache%2Ftags%2Ffa_lru.hh;h=a266fb516c86e69c0c166a371cb95f26225631bb;hb=a66fe6a8c36c9ab49cb3a35065bfc645d51036c8;hp=8cbc798130f22a35508b00626ad4146b041f0ad8;hpb=08474ccf68e14f59b4517c6024a9bc6ecbd4a1d5;p=gem5.git diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 8cbc79813..a266fb516 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2012-2013,2016 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2003-2005 The Regents of The University of Michigan * All rights reserved. * @@ -33,15 +45,17 @@ * Declaration of a fully associative LRU tag store. */ -#ifndef __FA_LRU_HH__ -#define __FA_LRU_HH__ +#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__ +#define __MEM_CACHE_TAGS_FA_LRU_HH__ #include +#include -#include "mem/cache/cache_blk.hh" +#include "mem/cache/base.hh" +#include "mem/cache/blk.hh" +#include "mem/cache/tags/base.hh" #include "mem/packet.hh" -#include "base/hashmap.hh" -#include "mem/cache/tags/base_tags.hh" +#include "params/FALRU.hh" /** * A fully associative cache block. @@ -76,24 +90,14 @@ class FALRU : public BaseTags public: /** Typedef the block type used in this class. */ typedef FALRUBlk BlkType; - /** Typedef a list of pointers to the local block type. */ - typedef std::list BlkList; - protected: - /** The block size of the cache. */ - const int blkSize; - /** The size of the cache. */ - const int size; - /** The number of blocks in the cache. */ - const int numBlks; // calculated internally - /** The hit latency of the cache. */ - const int hitLatency; + protected: /** Array of pointers to blocks at the cache size boundaries. */ FALRUBlk **cacheBoundaries; /** A mask for the FALRUBlk::inCache bits. */ int cacheMask; /** The number of different size caches being tracked. */ - int numCaches; + unsigned numCaches; /** The cache blocks. */ FALRUBlk *blks; @@ -104,7 +108,7 @@ class FALRU : public BaseTags FALRUBlk *tail; /** Hash table type mapping addresses to cache block pointers. */ - typedef m5::hash_map > hash_t; + typedef std::unordered_map > hash_t; /** Iterator into the address hash table. */ typedef hash_t::const_iterator tagIterator; @@ -139,108 +143,82 @@ class FALRU : public BaseTags */ /** Hits in each cache size >= 128K. */ - Stats::Vector<> hits; + Stats::Vector hits; /** Misses in each cache size >= 128K. */ - Stats::Vector<> misses; + Stats::Vector misses; /** Total number of accesses. */ - Stats::Scalar<> accesses; + Stats::Scalar accesses; /** * @} */ public: + + typedef FALRUParams Params; + /** * Construct and initialize this cache tagstore. - * @param blkSize The block size of the cache. - * @param size The size of the cache. - * @param hit_latency The hit latency of the cache. */ - FALRU(int blkSize, int size, int hit_latency); + FALRU(const Params *p); + ~FALRU(); /** * Register the stats for this object. * @param name The name to prepend to the stats name. */ - void regStats(const std::string &name); - - /** - * Return true if the address is found in the cache. - * @param asid The address space ID. - * @param addr The address to look for. - * @return True if the address is in the cache. - */ - bool probe(Addr addr) const; + void regStats() override; /** * Invalidate a cache block. * @param blk The block to invalidate. */ - void invalidateBlk(BlkType *blk); + void invalidate(CacheBlk *blk) override; /** - * Find the block in the cache and update the replacement data. Returns - * the access latency and the in cache flags as a side effect + * Access block and update replacement data. May not succeed, in which + * case nullptr pointer is returned. This has all the implications of a + * cache access and should only be used as such. + * Returns the access latency and inCache flags as a side effect. * @param addr The address to look for. - * @param asid The address space ID. + * @param is_secure True if the target memory space is secure. * @param lat The latency of the access. * @param inCache The FALRUBlk::inCache flags. * @return Pointer to the cache block. */ - FALRUBlk* findBlock(Addr addr, int &lat, int *inCache = 0); + CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat, + int *inCache); + + /** + * Just a wrapper of above function to conform with the base interface. + */ + CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override; /** * Find the block in the cache, do not update the replacement data. * @param addr The address to look for. + * @param is_secure True if the target memory space is secure. * @param asid The address space ID. * @return Pointer to the cache block. */ - FALRUBlk* findBlock(Addr addr) const; + CacheBlk* findBlock(Addr addr, bool is_secure) const override; /** * Find a replacement block for the address provided. * @param pkt The request to a find a replacement candidate for. - * @param writebacks List for any writebacks to be performed. * @return The block to place the replacement in. */ - FALRUBlk* findReplacement(Addr addr, PacketList & writebacks); + CacheBlk* findVictim(Addr addr) override; - /** - * Return the hit latency of this cache. - * @return The hit latency. - */ - int getHitLatency() const - { - return hitLatency; - } + void insertBlock(PacketPtr pkt, CacheBlk *blk) override; /** - * Return the block size of this cache. - * @return The block size. + * Find the cache block given set and way + * @param set The set of the block. + * @param way The way of the block. + * @return The cache block. */ - int getBlockSize() - { - return blkSize; - } - - /** - * Return the subblock size of this cache, always the block size. - * @return The block size. - */ - int getSubBlockSize() - { - return blkSize; - } - - /** - * Align an address to the block size. - * @param addr the address to align. - * @return The aligned address. - */ - Addr blkAlign(Addr addr) const - { - return (addr & ~(Addr)(blkSize-1)); - } + CacheBlk* findBlockBySetAndWay(int set, int way) const override; /** * Generate the tag from the addres. For fully associative this is just the @@ -248,7 +226,7 @@ public: * @param addr The address to get the tag from. * @return The tag. */ - Addr extractTag(Addr addr) const + Addr extractTag(Addr addr) const override { return blkAlign(addr); } @@ -258,56 +236,46 @@ public: * @param addr The address to get the set from. * @return 0. */ - int extractSet(Addr addr) const + int extractSet(Addr addr) const override { return 0; } - /** - * Calculate the block offset of an address. - * @param addr the address to get the offset of. - * @return the block offset. - */ - int extractBlkOffset(Addr addr) const - { - return (addr & (Addr)(blkSize-1)); - } - /** * Regenerate the block address from the tag and the set. * @param tag The tag of the block. * @param set The set the block belongs to. * @return the block address. */ - Addr regenerateBlkAddr(Addr tag, int set) const + Addr regenerateBlkAddr(Addr tag, unsigned set) const override { return (tag); } /** - * Read the data out of the internal storage of a cache block. FALRU - * currently doesn't support data storage. - * @param blk The cache block to read. - * @param data The buffer to read the data into. - * @return The data from the cache block. + * @todo Implement as in lru. Currently not used */ - void readData(FALRUBlk *blk, uint8_t *data) - { - } + virtual std::string print() const override { return ""; } /** - * Write data into the internal storage of a cache block. FALRU - * currently doesn't support data storage. - * @param blk The cache block to be written. - * @param data The data to write. - * @param size The number of bytes to write. - * @param writebacks A list for any writebacks to be performed. May be - * needed when writing to a compressed block. + * Visit each block in the tag store and apply a visitor to the + * block. + * + * The visitor should be a function (or object that behaves like a + * function) that takes a cache block reference as its parameter + * and returns a bool. A visitor can request the traversal to be + * stopped by returning false, returning true causes it to be + * called for the next block in the tag store. + * + * \param visitor Visitor to call on each block. */ - void writeData(FALRUBlk *blk, uint8_t *data, int size, - PacketList &writebacks) - { + void forEachBlk(CacheBlkVisitor &visitor) override { + for (int i = 0; i < numBlocks; i++) { + if (!visitor(blks[i])) + return; + } } + }; -#endif +#endif // __MEM_CACHE_TAGS_FA_LRU_HH__