X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fpacket_access.hh;h=06c1068eb84fd23a2b62b6de8a69223d300e1785;hb=078bdc86617e096d545b253f359ab27d5b3fdced;hp=882aa98d0c94e57296fb3c203e660765828fe8f6;hpb=b9005f35621c564fb70b60223352732eb9cde955;p=gem5.git

diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh
index 882aa98d0..06c1068eb 100644
--- a/src/mem/packet_access.hh
+++ b/src/mem/packet_access.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2015 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -27,50 +39,92 @@
  *
  * Authors: Ali Saidi
  *          Nathan Binkert
+ *          Andreas Sandberg
  */
 
-#include "arch/isa_traits.hh"
-#include "base/bigint.hh"
+#ifndef __MEM_PACKET_ACCESS_HH__
+#define __MEM_PACKET_ACCESS_HH__
+
 #include "mem/packet.hh"
 #include "sim/byteswap.hh"
 
-#ifndef __MEM_PACKET_ACCESS_HH__
-#define __MEM_PACKET_ACCESS_HH__
-// The memory system needs to have an endianness. This is the easiest
-// way to deal with it for now. At some point, we will have to remove
-// these functions and make the users do their own byte swapping since
-// the memory system does not in fact have an endianness.
-
-template<>
-inline Twin64_t
-Packet::get()
+template <typename T>
+inline T
+Packet::getRaw() const
 {
-    Twin64_t d;
-    assert(staticData || dynamicData);
-    assert(sizeof(Twin64_t) <= size);
-    d.a = TheISA::gtoh(*(uint64_t*)data);
-    d.b = TheISA::gtoh(*((uint64_t*)data + 1));
-    return d;
+    assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
+    assert(sizeof(T) <= size);
+    return *(T*)data;
+}
+
+template <typename T>
+inline void
+Packet::setRaw(T v)
+{
+    assert(flags.isSet(STATIC_DATA|DYNAMIC_DATA));
+    assert(sizeof(T) <= size);
+    *(T*)data = v;
 }
 
 
-/** return the value of what is pointed to in the packet. */
 template <typename T>
 inline T
-Packet::get()
+Packet::getBE() const
 {
-    assert(staticData || dynamicData);
-    assert(sizeof(T) <= size);
-    return TheISA::gtoh(*(T*)data);
+    return betoh(getRaw<T>());
+}
+
+template <typename T>
+inline T
+Packet::getLE() const
+{
+    return letoh(getRaw<T>());
+}
+
+template <typename T>
+inline T
+Packet::get(ByteOrder endian) const
+{
+    switch (endian) {
+      case BigEndianByteOrder:
+        return getBE<T>();
+
+      case LittleEndianByteOrder:
+        return getLE<T>();
+
+      default:
+        panic("Illegal byte order in Packet::get()\n");
+    };
 }
 
-/** set the value in the data pointer to v. */
 template <typename T>
 inline void
-Packet::set(T v)
+Packet::setBE(T v)
 {
-    assert(sizeof(T) <= size);
-    *(T*)data = TheISA::htog(v);
+    setRaw(htobe(v));
+}
+
+template <typename T>
+inline void
+Packet::setLE(T v)
+{
+    setRaw(htole(v));
+}
+
+template <typename T>
+inline void
+Packet::set(T v, ByteOrder endian)
+{
+    switch (endian) {
+      case BigEndianByteOrder:
+        return setBE<T>(v);
+
+      case LittleEndianByteOrder:
+        return setLE<T>(v);
+
+      default:
+        panic("Illegal byte order in Packet::set()\n");
+    };
 }
 
 #endif //__MEM_PACKET_ACCESS_HH__