X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fprotocol%2FMESI_CMP_directory-dma.sm;h=374463164aa1fccc6633ce1875a994fd375e1d6f;hb=0c58106b6e27445e259d82bb13e2a5b6ae991bb6;hp=143c465efc16e6e4bdf598b4ebb1405c8976f9d8;hpb=d9a24500543a4c2f0e28f9a1c66118a19f85f495;p=gem5.git

diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index 143c465ef..374463164 100644
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -1,15 +1,44 @@
+/*
+ * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
+ * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 machine(DMA, "DMA Controller") 
-: int request_latency
+: DMASequencer * dma_sequencer,
+  int request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
 
-  enumeration(State, desc="DMA states", default="DMA_State_READY") {
-    READY, desc="Ready to accept a new request";
-    BUSY_RD,  desc="Busy: currently processing a request";
-    BUSY_WR,  desc="Busy: currently processing a request";
+  state_declaration(State, desc="DMA states", default="DMA_State_READY") {
+    READY, AccessPermission:Invalid, desc="Ready to accept a new request";
+    BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
+    BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
   }
 
   enumeration(Event, desc="DMA events") {
@@ -19,13 +48,12 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  external_type(DMASequencer) {
+  structure(DMASequencer, external="yes") {
     void ackCallback();
     void dataCallback(DataBlock);
   }
 
   MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
   State cur_state, no_vector="true";
 
   State getState(Address addr) {
@@ -35,7 +63,18 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
-  out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
+  DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+    error("DMA does not support get data block.");
+  }
+
+  out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
     if (dmaRequestQueue_in.isReady()) {