X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fprotocol%2FMOESI_AMD_Base-Region-CorePair.sm;h=5c08c6bd71a16345ef6a0513a60a4840da7a06a3;hb=e33b3aa6692b172f6db5957774a9e0289e81fa5b;hp=fd84447a2d1982855b0a050a5e5c9a8ddb1678ad;hpb=1a7d3f9fcb76a68540dd948f91413533a383bfde;p=gem5.git

diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
index fd84447a2..5c08c6bd7 100644
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -14,9 +14,9 @@
  * this list of conditions and the following disclaimer in the documentation
  * and/or other materials provided with the distribution.
  *
- * 3. Neither the name of the copyright holder nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -30,7 +30,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- * Author: Lisa Hsu
+ * Authors: Lisa Hsu
  */
 
 machine(MachineType:CorePair, "CP-like Core Coherence")
@@ -237,6 +237,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
   void wakeUpAllBuffers();
   void wakeUpBuffers(Addr a);
   Cycles curCycle();
+  MachineID mapAddressToMachine(Addr addr, MachineType mtype);
 
   // END STRUCTURE DEFINITIONS
 
@@ -1119,7 +1120,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
         out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:StaleNotif;
         out_msg.Sender := machineID;
-        out_msg.Destination.add(map_Address_to_Directory(address));
+        out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
         out_msg.MessageSize := MessageSizeType:Response_Control;
         DPRINTF(RubySlicc, "%s\n", out_msg);
       }
@@ -1201,7 +1202,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
         out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:CPUData;
         out_msg.Sender := machineID;
-        out_msg.Destination.add(map_Address_to_Directory(address));
+        out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
         out_msg.DataBlk := tbe.DataBlk;
         out_msg.Dirty := tbe.Dirty;
         if (tbe.Shared) {
@@ -1221,7 +1222,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.Dirty := false;
       out_msg.Hit := false;
       out_msg.Ntsl := true;
@@ -1236,7 +1238,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.Dirty := false;
       out_msg.Ntsl := true;
       out_msg.Hit := false;
@@ -1252,7 +1255,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       assert(addressInCore(address) || is_valid(tbe));
       out_msg.Dirty := false;  // only true if sending back data i think
       out_msg.Hit := true;
@@ -1268,7 +1272,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;  // L3 and CPUs respond in same way to probes
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       if (addressInCore(address)) {
         out_msg.Hit := true;
       } else {
@@ -1288,7 +1293,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.DataBlk := cache_entry.DataBlk;
       assert(cache_entry.Dirty);
       out_msg.Dirty := true;
@@ -1305,7 +1311,8 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address)); // will this always be ok? probably not for multisocket
+      // will this always be ok? probably not for multisocket
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.DataBlk := cache_entry.DataBlk;
       assert(cache_entry.Dirty);
       out_msg.Dirty := true;
@@ -1323,7 +1330,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUPrbResp;
       out_msg.Sender := machineID;
-      out_msg.Destination.add(map_Address_to_Directory(address));
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.DataBlk := tbe.DataBlk;
       assert(tbe.Dirty);
       out_msg.Dirty := true;
@@ -1358,7 +1365,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
     enqueue(responseNetwork_out, ResponseMsg, issue_latency) {
       out_msg.addr := address;
       out_msg.Type := CoherenceResponseType:CPUCancelWB;
-      out_msg.Destination.add(map_Address_to_Directory(address));
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.Sender := machineID;
       out_msg.MessageSize := MessageSizeType:Response_Control;
     }
@@ -1372,7 +1379,7 @@ machine(MachineType:CorePair, "CP-like Core Coherence")
   action(uu_sendUnblock, "uu", desc="state changed, unblock") {
     enqueue(unblockNetwork_out, UnblockMsg, issue_latency) {
       out_msg.addr := address;
-      out_msg.Destination.add(map_Address_to_Directory(address));
+      out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory));
       out_msg.MessageSize := MessageSizeType:Unblock_Control;
       out_msg.wasValid := isValid(address);
       DPRINTF(RubySlicc, "%s\n", out_msg);