X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fprotocol%2FMOESI_hammer-cache.sm;h=9cbd277d4fb82f22a0d7f2c79c08b1612aaab943;hb=e33b3aa6692b172f6db5957774a9e0289e81fa5b;hp=5d23835410b3067de34544f778e33360fc56a701;hpb=cd9e4458139658c4ce8f038e3a44bdecd17fa75d;p=gem5.git diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 5d2383541..9cbd277d4 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -33,7 +33,7 @@ * Brad Beckmann */ -machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") +machine(MachineType:L1Cache, "AMD Hammer-like protocol") : Sequencer * sequencer; CacheMemory * L1Icache; CacheMemory * L1Dcache; @@ -89,7 +89,6 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack"; MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack"; II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Other_GETS or Other_GETX, waiting for ack"; - IT, AccessPermission:Busy, "IT", desc="Invalid block transferring to L1"; ST, AccessPermission:Busy, "ST", desc="S block transferring to L1"; OT, AccessPermission:Busy, "OT", desc="O block transferring to L1"; MT, AccessPermission:Busy, "MT", desc="M block transferring to L1"; @@ -189,6 +188,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") void wakeUpAllBuffers(); void wakeUpBuffers(Addr a); Cycles curCycle(); + MachineID mapAddressToMachine(Addr addr, MachineType mtype); Entry getCacheEntry(Addr address), return_by_pointer="yes" { Entry L2cache_entry := static_cast(Entry, "pointer", L2cache.lookup(address)); @@ -555,7 +555,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.InitialRequestTime := curCycle(); @@ -570,7 +570,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.InitialRequestTime := curCycle(); @@ -586,7 +586,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.InitialRequestTime := curCycle(); } @@ -602,7 +602,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETF; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Request_Control; out_msg.InitialRequestTime := curCycle(); @@ -662,7 +662,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUT; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } @@ -672,7 +672,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUTF; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } } @@ -827,7 +827,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Unblock_Control; } } @@ -837,7 +837,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCKM; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Unblock_Control; } } @@ -849,7 +849,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") out_msg.Type := CoherenceResponseType:UNBLOCKS; out_msg.Sender := machineID; out_msg.CurOwner := tbe.CurOwner; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Unblock_Control; } } @@ -1127,7 +1127,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") assert(is_valid(tbe)); out_msg.addr := address; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.Dirty := tbe.Dirty; if (tbe.Dirty) { out_msg.Type := CoherenceResponseType:WB_DIRTY; @@ -1158,7 +1158,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") assert(is_valid(tbe)); out_msg.addr := address; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.DataBlk := tbe.DataBlk; out_msg.Dirty := tbe.Dirty; if (tbe.Dirty) { @@ -1243,9 +1243,23 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") unset_cache_entry(); } + action(gr_deallocateCacheBlock, "\gr", desc="Deallocate an L1 or L2 cache block.") { + if (L1Dcache.isTagPresent(address)) { + L1Dcache.deallocate(address); + } + else if (L1Icache.isTagPresent(address)){ + L1Icache.deallocate(address); + } + else { + assert(L2cache.isTagPresent(address)); + L2cache.deallocate(address); + } + unset_cache_entry(); + } + action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") { if (send_evictions) { - DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address); + DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address); sequencer.evictionCallback(address); } } @@ -1296,7 +1310,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") //***************************************************** // Transitions for Load/Store/L2_Replacement from transient states - transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) { + transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, ST, OT, MT, MMT}, {Store, L2_Replacement}) { zz_stallAndWaitMandatoryQueue; } @@ -1308,11 +1322,11 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") zz_stallAndWaitMandatoryQueue; } - transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) { + transition({IM, IS, OI, MI, II, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) { zz_stallAndWaitMandatoryQueue; } - transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) { + transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, ST, OT, MT, MMT, IM_F, SM_F, ISM_F, OM_F, MM_WF, MI_F, MM_F, IR, SR, OR, MR, MMR}, L1_to_L2) { zz_stallAndWaitMandatoryQueue; } @@ -1324,7 +1338,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") zz_stallAndWaitMandatoryQueue; } - transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) { + transition({ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) { z_stall; } @@ -1333,7 +1347,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") } // Transitions moving data between the L1 and L2 caches - transition({I, S, O, M, MM}, L1_to_L2) { + transition({S, O, M, MM}, L1_to_L2) { i_allocateTBE; gg_deallocateL1CacheBlock; vv_allocateL2CacheBlock; @@ -1341,16 +1355,6 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") s_deallocateTBE; } - transition(I, Trigger_L2_to_L1D, IT) { - i_allocateTBE; - rr_deallocateL2CacheBlock; - ii_allocateL1DCacheBlock; - nb_copyFromTBEToL1; // Not really needed for state I - s_deallocateTBE; - zz_stallAndWaitMandatoryQueue; - ll_L2toL1Transfer; - } - transition(S, Trigger_L2_to_L1D, ST) { i_allocateTBE; rr_deallocateL2CacheBlock; @@ -1391,16 +1395,6 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") ll_L2toL1Transfer; } - transition(I, Trigger_L2_to_L1I, IT) { - i_allocateTBE; - rr_deallocateL2CacheBlock; - jj_allocateL1ICacheBlock; - nb_copyFromTBEToL1; - s_deallocateTBE; - zz_stallAndWaitMandatoryQueue; - ll_L2toL1Transfer; - } - transition(S, Trigger_L2_to_L1I, ST) { i_allocateTBE; rr_deallocateL2CacheBlock; @@ -1441,11 +1435,6 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") ll_L2toL1Transfer; } - transition(IT, Complete_L2_to_L1, IR) { - j_popTriggerQueue; - kd_wakeUpDependents; - } - transition(ST, Complete_L2_to_L1, SR) { j_popTriggerQueue; kd_wakeUpDependents; @@ -1500,11 +1489,6 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") k_popMandatoryQueue; } - transition(I, L2_Replacement) { - rr_deallocateL2CacheBlock; - ka_wakeUpAllDependents; - } - transition(I, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) { f_sendAck; l_popForwardQueue; @@ -1564,6 +1548,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") transition(S, {Other_GETX, Invalidate}, I) { f_sendAck; forward_eviction_to_cpu; + gr_deallocateCacheBlock; l_popForwardQueue; } @@ -1630,6 +1615,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") transition(O, {Other_GETX, Invalidate}, I) { e_sendData; forward_eviction_to_cpu; + gr_deallocateCacheBlock; l_popForwardQueue; } @@ -1712,12 +1698,14 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") transition(MM, {Other_GETX, Invalidate}, I) { c_sendExclusiveData; forward_eviction_to_cpu; + gr_deallocateCacheBlock; l_popForwardQueue; } transition(MM, Other_GETS, I) { c_sendExclusiveData; forward_eviction_to_cpu; + gr_deallocateCacheBlock; l_popForwardQueue; } @@ -1778,6 +1766,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") transition(M, {Other_GETX, Invalidate}, I) { c_sendExclusiveData; forward_eviction_to_cpu; + gr_deallocateCacheBlock; l_popForwardQueue; }