X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Fruby%2Fstructures%2FCacheMemory.hh;h=c126a535db01acca6444360dc35dab96aaff1fa3;hb=78270ede7be98d78671940b7f0a8e33c6d810164;hp=9434660cb64ddea6e04ab8adf85eee38bd1335c6;hpb=6da3e5748f36c909829b92121493500efdd76385;p=gem5.git

diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 9434660cb..c126a535d 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -140,7 +140,6 @@ class CacheMemory : public SimObject
     void print(std::ostream& out) const;
     void printData(std::ostream& out) const;
 
-    void regStats();
     bool checkResourceAvailable(CacheResourceType res, Addr addr);
     void recordRequestType(CacheRequestType requestType, Addr addr);
 
@@ -149,29 +148,24 @@ class CacheMemory : public SimObject
     void htmCommitTransaction();
 
   public:
-    Stats::Scalar m_demand_hits;
-    Stats::Scalar m_demand_misses;
-    Stats::Formula m_demand_accesses;
-
-    Stats::Scalar m_sw_prefetches;
-    Stats::Scalar m_hw_prefetches;
-    Stats::Formula m_prefetches;
-
-    Stats::Vector m_accessModeType;
+    struct CacheMemoryStats : public Stats::Group
+    {
+        CacheMemoryStats(Stats::Group *parent);
 
-    Stats::Scalar numDataArrayReads;
-    Stats::Scalar numDataArrayWrites;
-    Stats::Scalar numTagArrayReads;
-    Stats::Scalar numTagArrayWrites;
+        Stats::Scalar numDataArrayReads;
+        Stats::Scalar numDataArrayWrites;
+        Stats::Scalar numTagArrayReads;
+        Stats::Scalar numTagArrayWrites;
 
-    Stats::Scalar numTagArrayStalls;
-    Stats::Scalar numDataArrayStalls;
+        Stats::Scalar numTagArrayStalls;
+        Stats::Scalar numDataArrayStalls;
 
-    // hardware transactional memory
-    Stats::Histogram htmTransCommitReadSet;
-    Stats::Histogram htmTransCommitWriteSet;
-    Stats::Histogram htmTransAbortReadSet;
-    Stats::Histogram htmTransAbortWriteSet;
+        // hardware transactional memory
+        Stats::Histogram htmTransCommitReadSet;
+        Stats::Histogram htmTransCommitWriteSet;
+        Stats::Histogram htmTransAbortReadSet;
+        Stats::Histogram htmTransAbortWriteSet;
+    };
 
     int getCacheSize() const { return m_cache_size; }
     int getCacheAssoc() const { return m_cache_assoc; }
@@ -229,6 +223,18 @@ class CacheMemory : public SimObject
      * false.
      */
     bool m_use_occupancy;
+
+    public:
+      CacheMemoryStats cacheMemoryStats;
+      Stats::Scalar m_demand_hits;
+      Stats::Scalar m_demand_misses;
+      Stats::Formula m_demand_accesses;
+
+      Stats::Scalar m_sw_prefetches;
+      Stats::Scalar m_hw_prefetches;
+      Stats::Formula m_prefetches;
+
+      Stats::Vector m_accessModeType;
 };
 
 std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);