X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmem%2Ftport.hh;h=5e80f4fab081d5dd6ecee7a44f1abb25bf22193e;hb=f49830ce0ba79c54c65c9c4b25bc3c6184aaf2a9;hp=3d28ea3e5d65d0221e468396ca836d3d9ff79d18;hpb=b5e68fb54677f601bb00c23af52db8fd6571301f;p=gem5.git

diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index 3d28ea3e5..5e80f4fab 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
@@ -26,6 +38,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Ali Saidi
+ *          Andreas Hansson
  */
 
 #ifndef __MEM_TPORT_HH__
@@ -37,104 +50,61 @@
  * Declaration of SimpleTimingPort.
  */
 
-#include "mem/port.hh"
-#include "sim/eventq.hh"
-#include <list>
-#include <string>
+#include "mem/qport.hh"
 
 /**
- * A simple port for interfacing objects that basically have only
- * functional memory behavior (e.g. I/O devices) to the memory system.
- * Both timing and functional accesses are implemented in terms of
- * atomic accesses.  A derived port class thus only needs to provide
- * recvAtomic() to support all memory access modes.
- *
- * The tricky part is handling recvTiming(), where the response must
- * be scheduled separately via a later call to sendTiming().  This
- * feature is handled by scheduling an internal event that calls
- * sendTiming() after a delay, and optionally rescheduling the
- * response if it is nacked.
+ * The simple timing port uses a queued port to implement
+ * recvFunctional and recvTimingReq through recvAtomic. It is always a
+ * slave port.
  */
-class SimpleTimingPort : public Port
+class SimpleTimingPort : public QueuedSlavePort
 {
-  protected:
-    /** A list of outgoing timing response packets that haven't been
-     * serviced yet. */
-    std::list<std::pair<Tick,PacketPtr> > transmitList;
+
+  private:
 
     /**
-     * This class is used to implemented sendTiming() with a delay. When
-     * a delay is requested a the event is scheduled if it isn't already.
-     * When the event time expires it attempts to send the packet.
-     * If it cannot, the packet sent when recvRetry() is called.
-     **/
-    class SendEvent : public Event
-    {
-        SimpleTimingPort *port;
-
-      public:
-        SendEvent(SimpleTimingPort *p)
-            : Event(&mainEventQueue), port(p)
-        { }
-
-        virtual void process();
-
-        virtual const char *description()
-        { return "Future scheduled sendTiming event"; }
-    };
-
-    SendEvent sendEvent;
-
-    /** If we need to drain, keep the drain event around until we're done
-     * here.*/
-    Event *drainEvent;
-
-    /** Schedule a sendTiming() event to be called in the future.
-     * @param pkt packet to send
-     * @param time increment from now (in ticks) to send packet
+     * The packet queue used to store outgoing responses. Note that
+     * the queue is made private and that we avoid overloading the
+     * name used in the QueuedSlavePort. Access is provided through
+     * the queue reference in the base class.
      */
-    void sendTiming(PacketPtr pkt, Tick time);
+    SlavePacketQueue queueImpl;
 
-    /** This function is notification that the device should attempt to send a
-     * packet again. */
-    virtual void recvRetry();
+  protected:
 
     /** Implemented using recvAtomic(). */
     void recvFunctional(PacketPtr pkt);
 
     /** Implemented using recvAtomic(). */
-    bool recvTiming(PacketPtr pkt);
+    bool recvTimingReq(PacketPtr pkt);
+
+    virtual Tick recvAtomic(PacketPtr pkt) = 0;
 
     /**
-     * Simple ports generally don't care about any status
-     * changes... can always override this in cases where that's not
-     * true. */
-    virtual void recvStatusChange(Status status) { }
+     * @todo this is a temporary workaround until the 4-phase code is committed.
+     * upstream caches need this packet until true is returned, so hold it for
+     * deletion until a subsequent call
+     */
+    std::vector<PacketPtr> pendingDelete;
 
 
   public:
 
-    SimpleTimingPort(std::string pname, MemObject *_owner = NULL)
-        : Port(pname, _owner), sendEvent(this), drainEvent(NULL)
-    {}
-
-    /** Hook for draining timing accesses from the system.  The
-     * associated SimObject's drain() functions should be implemented
-     * something like this when this class is used:
-     \code
-          PioDevice::drain(Event *de)
-          {
-              unsigned int count;
-              count = SimpleTimingPort->drain(de);
-              if (count)
-                  changeState(Draining);
-              else
-                  changeState(Drained);
-              return count;
-          }
-     \endcode
-    */
-    unsigned int drain(Event *de);
+    /**
+     * Create a new SimpleTimingPort that relies on a packet queue to
+     * hold responses, and implements recvTimingReq and recvFunctional
+     * through calls to recvAtomic. Once a request arrives, it is
+     * passed to recvAtomic, and in the case of a timing access any
+     * response is scheduled to be sent after the delay of the atomic
+     * operation.
+     *
+     * @param name port name
+     * @param owner structural owner
+     */
+    SimpleTimingPort(const std::string& name, MemObject* owner);
+
+    virtual ~SimpleTimingPort() { }
+
 };
 
 #endif // __MEM_TPORT_HH__