X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi915%2Fi830_vtbl.c;h=0775d7fe943034a4bf16cc62c6c91e0d3a3f0f1d;hb=fba5f6bda76f5236f6f05aa81157a08949cde7c3;hp=6dd64ef45e89c23bbf8bdbe274d11aa24dd1a77e;hpb=f9439e4a4696b8bc5fcdf3ac664f5e8d446f6621;p=mesa.git

diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 6dd64ef45e8..0775d7fe943 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -235,8 +235,8 @@ static GLboolean
 i830_check_vertex_size(struct intel_context *intel, GLuint expected)
 {
    struct i830_context *i830 = i830_context(&intel->ctx);
-   int vft0 = i830->current->Ctx[I830_CTXREG_VF];
-   int vft1 = i830->current->Ctx[I830_CTXREG_VF2];
+   int vft0 = i830->state.Ctx[I830_CTXREG_VF];
+   int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
    int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
    int i, sz = 0;
 
@@ -412,10 +412,10 @@ static void
 i830_emit_state(struct intel_context *intel)
 {
    struct i830_context *i830 = i830_context(&intel->ctx);
-   struct i830_hw_state *state = i830->current;
+   struct i830_hw_state *state = &i830->state;
    int i, count;
    GLuint dirty;
-   dri_bo *aper_array[3 + I830_TEX_UNITS];
+   drm_intel_bo *aper_array[3 + I830_TEX_UNITS];
    int aper_count;
    GET_CURRENT_CONTEXT(ctx);
    BATCH_LOCALS;
@@ -496,15 +496,13 @@ i830_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
-		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                state->draw_region->draw_offset);
+		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 
       if (state->depth_region) {
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
          OUT_RELOC(state->depth_region->buffer,
-		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                   state->depth_region->draw_offset);
+		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
       }
 
       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
@@ -575,12 +573,10 @@ i830_destroy_context(struct intel_context *intel)
 
    intel_region_release(&i830->state.draw_region);
    intel_region_release(&i830->state.depth_region);
-   intel_region_release(&i830->initial.draw_region);
-   intel_region_release(&i830->initial.depth_region);
 
    for (i = 0; i < I830_TEX_UNITS; i++) {
       if (i830->state.tex_buffer[i] != NULL) {
-	 dri_bo_unreference(i830->state.tex_buffer[i]);
+	 drm_intel_bo_unreference(i830->state.tex_buffer[i]);
 	 i830->state.tex_buffer[i] = NULL;
       }
    }
@@ -600,6 +596,7 @@ i830_set_draw_region(struct intel_context *intel,
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    GLuint value;
    struct i830_hw_state *state = &i830->state;
+   uint32_t draw_x, draw_y;
 
    if (state->draw_region != color_regions[0]) {
       intel_region_release(&state->draw_region);
@@ -654,14 +651,40 @@ i830_set_draw_region(struct intel_context *intel,
    }
    state->Buffer[I830_DESTREG_DV1] = value;
 
+   /* We set up the drawing rectangle to be offset into the color
+    * region's location in the miptree.  If it doesn't match with
+    * depth's offsets, we can't render to it.
+    *
+    * (Well, not actually true -- the hw grew a bit to let depth's
+    * offset get forced to 0,0.  We may want to use that if people are
+    * hitting that case.  Also, some configurations may be supportable
+    * by tweaking the start offset of the buffers around, which we
+    * can't do in general due to tiling)
+    */
+   FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
+	    (depth_region && color_regions[0]) &&
+	    (depth_region->draw_x != color_regions[0]->draw_x ||
+	     depth_region->draw_y != color_regions[0]->draw_y));
+
+   if (color_regions[0]) {
+      draw_x = color_regions[0]->draw_x;
+      draw_y = color_regions[0]->draw_y;
+   } else if (depth_region) {
+      draw_x = depth_region->draw_x;
+      draw_y = depth_region->draw_y;
+   } else {
+      draw_x = 0;
+      draw_y = 0;
+   }
+
    state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
    state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
-   state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
+   state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
    state->Buffer[I830_DESTREG_DRAWRECT3] =
-      (ctx->DrawBuffer->Width & 0xffff) |
-      (ctx->DrawBuffer->Height << 16);
-   state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
-   state->Buffer[I830_DESTREG_DRAWRECT5] = 0;
+      ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
+      ((ctx->DrawBuffer->Height + draw_y) << 16);
+   state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
+   state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
 
    I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
 }
@@ -679,8 +702,7 @@ static void
 i830_assert_not_dirty( struct intel_context *intel )
 {
    struct i830_context *i830 = i830_context(&intel->ctx);
-   struct i830_hw_state *state = i830->current;
-   assert(!get_dirty(state));
+   assert(!get_dirty(&i830->state));
 }
 
 static void