X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi915%2Fi830_vtbl.c;h=8ed8ff555ba66ea17b574a7d6572026587dc2516;hb=2b9c35945a74c6e2b559bb52eb612231465e86a1;hp=f7fdb78d059eec50660ced840c23004075409c84;hpb=4926c5748028d33da4808f8a5473aa7b2f2bdc62;p=mesa.git diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index f7fdb78d059..8ed8ff555ba 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -1,6 +1,6 @@ /************************************************************************** * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright 2003 VMware, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a @@ -18,7 +18,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -28,16 +28,23 @@ #include "i830_context.h" #include "i830_reg.h" #include "intel_batchbuffer.h" +#include "intel_mipmap_tree.h" #include "intel_regions.h" #include "intel_tris.h" #include "intel_fbo.h" +#include "intel_buffers.h" +#include "tnl/tnl.h" #include "tnl/t_context.h" #include "tnl/t_vertex.h" +#include "swrast_setup/swrast_setup.h" +#include "main/renderbuffer.h" +#include "main/framebuffer.h" +#include "main/fbobject.h" #define FILE_DEBUG_FLAG DEBUG_STATE -static GLboolean i830_check_vertex_size(struct intel_context *intel, - GLuint expected); +static bool i830_check_vertex_size(struct intel_context *intel, + GLuint expected); #define SZ_TO_HW(sz) ((sz-2)&0x3) #define EMIT_SZ(sz) (EMIT_1F + (sz) - 1) @@ -73,13 +80,11 @@ i830_render_start(struct intel_context *intel) struct i830_context *i830 = i830_context(ctx); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - DECLARE_RENDERINPUTS(index_bitset); + GLbitfield64 index_bitset = tnl->render_inputs_bitset; GLuint v0 = _3DSTATE_VFT0_CMD; GLuint v2 = _3DSTATE_VFT1_CMD; GLuint mcsb1 = 0; - RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset); - /* Important: */ VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; @@ -88,7 +93,7 @@ i830_render_start(struct intel_context *intel) /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. */ - if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) { + if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW); intel->coloroffset = 4; } @@ -97,59 +102,60 @@ i830_render_start(struct intel_context *intel) intel->coloroffset = 3; } - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) { + if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) { EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH); } EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE); intel->specoffset = 0; - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) || - RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) { - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) { + if (index_bitset & (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | + BITFIELD64_BIT(_TNL_ATTRIB_FOG))) { + if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { intel->specoffset = intel->coloroffset + 1; EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC); } else EMIT_PAD(3); - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) + if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC); else EMIT_PAD(1); } - if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) { + if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { int i, count = 0; for (i = 0; i < I830_TEX_UNITS; i++) { - if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) { + if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) { GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size; GLuint emit; GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] & ~TEXCOORDTYPE_MASK); - switch (sz) { - case 1: - case 2: - emit = EMIT_2F; - sz = 2; - mcs |= TEXCOORDTYPE_CARTESIAN; - break; - case 3: + if (intel->ctx.Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) { emit = EMIT_3F; sz = 3; mcs |= TEXCOORDTYPE_VECTOR; - break; - case 4: - emit = EMIT_3F_XYW; - sz = 3; - mcs |= TEXCOORDTYPE_HOMOGENEOUS; - break; - default: - continue; - }; - + } else { + switch (sz) { + case 1: + case 2: + case 3: + emit = EMIT_2F; + sz = 2; + mcs |= TEXCOORDTYPE_CARTESIAN; + break; + case 4: + emit = EMIT_3F_XYW; + sz = 3; + mcs |= TEXCOORDTYPE_HOMOGENEOUS; + break; + default: + continue; + } + } EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0); v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz)); @@ -173,9 +179,7 @@ i830_render_start(struct intel_context *intel) if (v0 != i830->state.Ctx[I830_CTXREG_VF] || v2 != i830->state.Ctx[I830_CTXREG_VF2] || mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] || - !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) { - int k; - + index_bitset != i830->last_index_bitset) { I830_STATECHANGE(i830, I830_UPLOAD_CTX); /* Must do this *after* statechange, so as not to affect @@ -192,10 +196,9 @@ i830_render_start(struct intel_context *intel) i830->state.Ctx[I830_CTXREG_VF] = v0; i830->state.Ctx[I830_CTXREG_VF2] = v2; i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1; - RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset); + i830->last_index_bitset = index_bitset; - k = i830_check_vertex_size(intel, intel->vertex_size); - assert(k); + assert(i830_check_vertex_size(intel, intel->vertex_size)); } } @@ -231,7 +234,7 @@ i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim) /* Pull apart the vertex format registers and figure out how large a * vertex is supposed to be. */ -static GLboolean +static bool i830_check_vertex_size(struct intel_context *intel, GLuint expected) { struct i830_context *i830 = i830_context(&intel->ctx); @@ -364,7 +367,7 @@ i830_emit_invarient_state(struct intel_context *intel) #define emit( intel, state, size ) \ - intel_batchbuffer_data(intel->batch, state, size ) + intel_batchbuffer_data(intel, state, size) static GLuint get_dirty(struct i830_hw_state *state) @@ -428,18 +431,19 @@ i830_emit_state(struct intel_context *intel) * scheduling is allowed, rather than assume that it is whenever a * batchbuffer fills up. */ - intel_batchbuffer_require_space(intel->batch, - get_state_size(state) + INTEL_PRIM_EMIT_SIZE); + intel_batchbuffer_require_space(intel, + get_state_size(state) + + INTEL_PRIM_EMIT_SIZE); count = 0; again: aper_count = 0; dirty = get_dirty(state); - aper_array[aper_count++] = intel->batch->buf; + aper_array[aper_count++] = intel->batch.bo; if (dirty & I830_UPLOAD_BUFFERS) { - aper_array[aper_count++] = state->draw_region->buffer; + aper_array[aper_count++] = state->draw_region->bo; if (state->depth_region) - aper_array[aper_count++] = state->depth_region->buffer; + aper_array[aper_count++] = state->depth_region->bo; } for (i = 0; i < I830_TEX_UNITS; i++) @@ -452,7 +456,7 @@ i830_emit_state(struct intel_context *intel) if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) { if (count == 0) { count++; - intel_batchbuffer_flush(intel->batch); + intel_batchbuffer_flush(intel); goto again; } else { _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state"); @@ -495,22 +499,22 @@ i830_emit_state(struct intel_context *intel) BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); - OUT_RELOC(state->draw_region->buffer, + OUT_RELOC(state->draw_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); if (state->depth_region) { OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]); - OUT_RELOC(state->depth_region->buffer, + OUT_RELOC(state->depth_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); } OUT_BATCH(state->Buffer[I830_DESTREG_DV0]); OUT_BATCH(state->Buffer[I830_DESTREG_DV1]); - OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]); OUT_BATCH(state->Buffer[I830_DESTREG_SR0]); OUT_BATCH(state->Buffer[I830_DESTREG_SR1]); OUT_BATCH(state->Buffer[I830_DESTREG_SR2]); + OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]); assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); @@ -534,14 +538,9 @@ i830_emit_state(struct intel_context *intel) BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]); - if (state->tex_buffer[i]) { - OUT_RELOC(state->tex_buffer[i], - I915_GEM_DOMAIN_SAMPLER, 0, - state->tex_offset[i]); - } - else { - OUT_BATCH(state->tex_offset[i]); - } + OUT_RELOC(state->tex_buffer[i], + I915_GEM_DOMAIN_SAMPLER, 0, + state->tex_offset[i]); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]); @@ -560,9 +559,7 @@ i830_emit_state(struct intel_context *intel) } } - intel->batch->dirty_state &= ~dirty; assert(get_dirty(state) == 0); - assert((intel->batch->dirty_state & (1<<1)) == 0); } static void @@ -584,6 +581,30 @@ i830_destroy_context(struct intel_context *intel) _tnl_free_vertices(&intel->ctx); } +static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] = +{ + [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888, + [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888, + [MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565, + [MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555, + [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444, +}; + +static bool +i830_render_target_supported(struct intel_context *intel, + struct gl_renderbuffer *rb) +{ + mesa_format format = rb->Format; + + if (format == MESA_FORMAT_Z24_UNORM_S8_UINT || + format == MESA_FORMAT_Z24_UNORM_X8_UINT || + format == MESA_FORMAT_Z_UNORM16) { + return true; + } + + return i830_render_target_format_for_mesa_format[format] != 0; +} + static void i830_set_draw_region(struct intel_context *intel, struct intel_region *color_regions[], @@ -594,16 +615,16 @@ i830_set_draw_region(struct intel_context *intel, struct gl_context *ctx = &intel->ctx; struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; struct intel_renderbuffer *irb = intel_renderbuffer(rb); + struct gl_renderbuffer *drb; + struct intel_renderbuffer *idrb = NULL; GLuint value; struct i830_hw_state *state = &i830->state; uint32_t draw_x, draw_y; if (state->draw_region != color_regions[0]) { - intel_region_release(&state->draw_region); intel_region_reference(&state->draw_region, color_regions[0]); } if (state->depth_region != depth_region) { - intel_region_release(&state->depth_region); intel_region_reference(&state->depth_region, depth_region); } @@ -623,24 +644,7 @@ i830_set_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ if (irb != NULL) { - switch (irb->Base.Format) { - case MESA_FORMAT_ARGB8888: - case MESA_FORMAT_XRGB8888: - value |= DV_PF_8888; - break; - case MESA_FORMAT_RGB565: - value |= DV_PF_565; - break; - case MESA_FORMAT_ARGB1555: - value |= DV_PF_1555; - break; - case MESA_FORMAT_ARGB4444: - value |= DV_PF_4444; - break; - default: - _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->Base.Format); - } + value |= i830_render_target_format_for_mesa_format[intel_rb_format(irb)]; } if (depth_region && depth_region->cpp == 4) { @@ -651,6 +655,13 @@ i830_set_draw_region(struct intel_context *intel, } state->Buffer[I830_DESTREG_DV1] = value; + drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer; + if (!drb) + drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer; + + if (drb) + idrb = intel_renderbuffer(drb); + /* We set up the drawing rectangle to be offset into the color * region's location in the miptree. If it doesn't match with * depth's offsets, we can't render to it. @@ -662,16 +673,15 @@ i830_set_draw_region(struct intel_context *intel, * can't do in general due to tiling) */ FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET, - (depth_region && color_regions[0]) && - (depth_region->draw_x != color_regions[0]->draw_x || - depth_region->draw_y != color_regions[0]->draw_y)); - - if (color_regions[0]) { - draw_x = color_regions[0]->draw_x; - draw_y = color_regions[0]->draw_y; - } else if (depth_region) { - draw_x = depth_region->draw_x; - draw_y = depth_region->draw_y; + idrb && irb && (idrb->draw_x != irb->draw_x || + idrb->draw_y != irb->draw_y)); + + if (irb) { + draw_x = irb->draw_x; + draw_y = irb->draw_y; + } else if (idrb) { + draw_x = idrb->draw_x; + draw_y = idrb->draw_y; } else { draw_x = 0; draw_y = 0; @@ -681,14 +691,159 @@ i830_set_draw_region(struct intel_context *intel, state->Buffer[I830_DESTREG_DRAWRECT1] = 0; state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x; state->Buffer[I830_DESTREG_DRAWRECT3] = - ((ctx->DrawBuffer->Width + draw_x) & 0xffff) | - ((ctx->DrawBuffer->Height + draw_y) << 16); + ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) | + ((ctx->DrawBuffer->Height + draw_y - 1) << 16); state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x; state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP; I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS); } +/** + * Update the hardware state for drawing into a window or framebuffer object. + * + * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other + * places within the driver. + * + * Basically, this needs to be called any time the current framebuffer + * changes, the renderbuffers change, or we need to draw into different + * color buffers. + */ +static void +i830_update_draw_buffer(struct intel_context *intel) +{ + struct gl_context *ctx = &intel->ctx; + struct gl_framebuffer *fb = ctx->DrawBuffer; + struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL; + struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL; + + if (!fb) { + /* this can happen during the initial context initialization */ + return; + } + + irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH); + irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL); + + /* Do this here, not core Mesa, since this function is called from + * many places within the driver. + */ + if (ctx->NewState & _NEW_BUFFERS) { + /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */ + _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer); + /* this updates the DrawBuffer's Width/Height if it's a FBO */ + _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer); + } + + if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) { + /* this may occur when we're called by glBindFrameBuffer() during + * the process of someone setting up renderbuffers, etc. + */ + /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/ + return; + } + + /* How many color buffers are we drawing into? + * + * If there are zero buffers or the buffer is too big, don't configure any + * regions for hardware drawing. We'll fallback to software below. Not + * having regions set makes some of the software fallback paths faster. + */ + if ((fb->Width > ctx->Const.MaxRenderbufferSize) + || (fb->Height > ctx->Const.MaxRenderbufferSize) + || (fb->_NumColorDrawBuffers == 0)) { + /* writing to 0 */ + colorRegions[0] = NULL; + } + else if (fb->_NumColorDrawBuffers > 1) { + int i; + struct intel_renderbuffer *irb; + + for (i = 0; i < fb->_NumColorDrawBuffers; i++) { + irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); + colorRegions[i] = (irb && irb->mt) ? irb->mt->region : NULL; + } + } + else { + /* Get the intel_renderbuffer for the single colorbuffer we're drawing + * into. + */ + if (_mesa_is_winsys_fbo(fb)) { + /* drawing to window system buffer */ + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) + colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT); + else + colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT); + } + else { + /* drawing to user-created FBO */ + struct intel_renderbuffer *irb; + irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]); + colorRegions[0] = (irb && irb->mt->region) ? irb->mt->region : NULL; + } + } + + if (!colorRegions[0]) { + FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true); + } + else { + FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false); + } + + /* Check for depth fallback. */ + if (irbDepth && irbDepth->mt) { + FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false); + depthRegion = irbDepth->mt->region; + } else if (irbDepth && !irbDepth->mt) { + FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true); + depthRegion = NULL; + } else { /* !irbDepth */ + /* No fallback is needed because there is no depth buffer. */ + FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false); + depthRegion = NULL; + } + + /* Check for stencil fallback. */ + if (irbStencil && irbStencil->mt) { + assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT); + FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false); + } else if (irbStencil && !irbStencil->mt) { + FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true); + } else { /* !irbStencil */ + /* No fallback is needed because there is no stencil buffer. */ + FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false); + } + + /* If we have a (packed) stencil buffer attached but no depth buffer, + * we still need to set up the shared depth/stencil state so we can use it. + */ + if (depthRegion == NULL && irbStencil && irbStencil->mt + && intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) { + depthRegion = irbStencil->mt->region; + } + + /* + * Update depth and stencil test state + */ + ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); + ctx->Driver.Enable(ctx, GL_STENCIL_TEST, + (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0)); + + intel->vtbl.set_draw_region(intel, colorRegions, depthRegion, + fb->_NumColorDrawBuffers); + intel->NewGLState |= _NEW_BUFFERS; + + /* Set state we know depends on drawable parameters: + */ + intelCalcViewport(ctx); + ctx->Driver.Scissor(ctx); + + /* Update culling direction which changes depending on the + * orientation of the buffer: + */ + ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); +} + /* This isn't really handled at the moment. */ static void @@ -709,6 +864,12 @@ i830_assert_not_dirty( struct intel_context *intel ) static void i830_invalidate_state(struct intel_context *intel, GLuint new_state) { + struct gl_context *ctx = &intel->ctx; + + _swsetup_InvalidateState(ctx, new_state); + _tnl_InvalidateState(ctx, new_state); + _tnl_invalidate_vertex_state(ctx, new_state); + if (new_state & _NEW_LIGHT) i830_update_provoking_vertex(&intel->ctx); } @@ -722,10 +883,12 @@ i830InitVtbl(struct i830_context *i830) i830->intel.vtbl.new_batch = i830_new_batch; i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; i830->intel.vtbl.set_draw_region = i830_set_draw_region; + i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer; i830->intel.vtbl.update_texture_state = i830UpdateTextureState; i830->intel.vtbl.render_start = i830_render_start; i830->intel.vtbl.render_prevalidate = i830_render_prevalidate; i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty; i830->intel.vtbl.finish_batch = intel_finish_vb; i830->intel.vtbl.invalidate_state = i830_invalidate_state; + i830->intel.vtbl.render_target_supported = i830_render_target_supported; }