X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi915%2Fi915_vtbl.c;h=6a0a121856d7943a9f3309b774ebd753a5b03102;hb=f8894fab0294817481b30e3cc40f6b3ccfe9314d;hp=3368fe43f2e1ccffaec7cfb571143c5c6457993a;hpb=f6426509dcbe6ff1332f30f74d9cf2ec3c00908f;p=mesa.git diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 3368fe43f2e..6a0a121856d 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -1,6 +1,6 @@ /************************************************************************** * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright 2003 VMware, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a @@ -18,7 +18,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -31,7 +31,6 @@ #include "main/mtypes.h" #include "main/imports.h" #include "main/macros.h" -#include "main/colormac.h" #include "main/renderbuffer.h" #include "main/framebuffer.h" @@ -177,7 +176,7 @@ i915_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(17); + BEGIN_BATCH(15); OUT_BATCH(_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | @@ -201,18 +200,13 @@ i915_emit_invarient_state(struct intel_context *intel) CSB_TCB(3, 3) | CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7)); - /* Need to initialize this to zero. - */ - OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0)); + OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); + OUT_BATCH(0); OUT_BATCH(0); /* XXX: Use this */ OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); - OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE); OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */ @@ -356,7 +350,7 @@ i915_emit_state(struct intel_context *intel) assert(get_dirty(state) == 0); if (INTEL_DEBUG & DEBUG_STATE) - fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty); + fprintf(stderr, "%s dirty: %x\n", __func__, dirty); if (dirty & I915_UPLOAD_INVARIENT) { if (INTEL_DEBUG & DEBUG_STATE) @@ -415,10 +409,10 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_DV0]); OUT_BATCH(state->Buffer[I915_DESTREG_DV1]); - OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]); OUT_BATCH(state->Buffer[I915_DESTREG_SR0]); OUT_BATCH(state->Buffer[I915_DESTREG_SR1]); OUT_BATCH(state->Buffer[I915_DESTREG_SR2]); + OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]); if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP) OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); @@ -549,22 +543,22 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region, static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] = { - [MESA_FORMAT_ARGB8888] = DV_PF_8888, - [MESA_FORMAT_XRGB8888] = DV_PF_8888, - [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS, - [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS, - [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS, + [MESA_FORMAT_B8G8R8A8_UNORM] = DV_PF_8888, + [MESA_FORMAT_B8G8R8X8_UNORM] = DV_PF_8888, + [MESA_FORMAT_B5G6R5_UNORM] = DV_PF_565 | DITHER_FULL_ALWAYS, + [MESA_FORMAT_B5G5R5A1_UNORM] = DV_PF_1555 | DITHER_FULL_ALWAYS, + [MESA_FORMAT_B4G4R4A4_UNORM] = DV_PF_4444 | DITHER_FULL_ALWAYS, }; static bool i915_render_target_supported(struct intel_context *intel, struct gl_renderbuffer *rb) { - gl_format format = rb->Format; + mesa_format format = rb->Format; - if (format == MESA_FORMAT_S8_Z24 || - format == MESA_FORMAT_X8_Z24 || - format == MESA_FORMAT_Z16) { + if (format == MESA_FORMAT_Z24_UNORM_S8_UINT || + format == MESA_FORMAT_Z24_UNORM_X8_UINT || + format == MESA_FORMAT_Z_UNORM16) { return true; } @@ -732,9 +726,9 @@ i915_update_draw_buffer(struct intel_context *intel) */ if (ctx->NewState & _NEW_BUFFERS) { /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */ - _mesa_update_framebuffer(ctx); + _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer); /* this updates the DrawBuffer's Width/Height if it's a FBO */ - _mesa_update_draw_buffer_bounds(ctx); + _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer); } if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) { @@ -777,7 +771,7 @@ i915_update_draw_buffer(struct intel_context *intel) /* Check for stencil fallback. */ if (irbStencil && irbStencil->mt) { - assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24); + assert(intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT); FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false); } else if (irbStencil && !irbStencil->mt) { FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true); @@ -790,7 +784,7 @@ i915_update_draw_buffer(struct intel_context *intel) * we still need to set up the shared depth/stencil state so we can use it. */ if (depthRegion == NULL && irbStencil && irbStencil->mt - && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) { + && intel_rb_format(irbStencil) == MESA_FORMAT_Z24_UNORM_S8_UINT) { depthRegion = irbStencil->mt->region; } @@ -806,14 +800,10 @@ i915_update_draw_buffer(struct intel_context *intel) fb->_NumColorDrawBuffers); intel->NewGLState |= _NEW_BUFFERS; - /* update viewport since it depends on window size */ - intelCalcViewport(ctx); - /* Set state we know depends on drawable parameters: */ - ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, - ctx->Scissor.Width, ctx->Scissor.Height); - ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far); + intelCalcViewport(ctx); + ctx->Driver.Scissor(ctx); /* Update culling direction which changes depending on the * orientation of the buffer: