X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi915%2Fintel_reg.h;h=f855b45979c7db7aceaf0628f9494ddaa198658c;hb=f8894fab0294817481b30e3cc40f6b3ccfe9314d;hp=dd91a1586c777f5d45e6135f4a1da53b95a60e60;hpb=733d32f3765be84a7e908df7e99a278cadcee853;p=mesa.git

diff --git a/src/mesa/drivers/dri/i915/intel_reg.h b/src/mesa/drivers/dri/i915/intel_reg.h
index dd91a1586c7..f855b45979c 100644
--- a/src/mesa/drivers/dri/i915/intel_reg.h
+++ b/src/mesa/drivers/dri/i915/intel_reg.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2003 VMware, Inc.
  * All Rights Reserved.
  * 
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -55,36 +55,6 @@
 
 #define _3DSTATE_DRAWRECT_INFO		(CMD_3D | (0x1d<<24) | (0x80<<16) | 0x3)
 
-/** @{
- *
- * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
- * additional flushing control.
- */
-#define _3DSTATE_PIPE_CONTROL		(CMD_3D | (3 << 27) | (2 << 24))
-#define PIPE_CONTROL_CS_STALL		(1 << 20)
-#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET	(1 << 19)
-#define PIPE_CONTROL_TLB_INVALIDATE	(1 << 18)
-#define PIPE_CONTROL_SYNC_GFDT		(1 << 17)
-#define PIPE_CONTROL_MEDIA_STATE_CLEAR	(1 << 16)
-#define PIPE_CONTROL_NO_WRITE		(0 << 14)
-#define PIPE_CONTROL_WRITE_IMMEDIATE	(1 << 14)
-#define PIPE_CONTROL_WRITE_DEPTH_COUNT	(2 << 14)
-#define PIPE_CONTROL_WRITE_TIMESTAMP	(3 << 14)
-#define PIPE_CONTROL_DEPTH_STALL	(1 << 13)
-#define PIPE_CONTROL_WRITE_FLUSH	(1 << 12)
-#define PIPE_CONTROL_INSTRUCTION_FLUSH	(1 << 11)
-#define PIPE_CONTROL_TC_FLUSH		(1 << 10) /* GM45+ only */
-#define PIPE_CONTROL_ISP_DIS		(1 << 9)
-#define PIPE_CONTROL_INTERRUPT_ENABLE	(1 << 8)
-/* GT */
-#define PIPE_CONTROL_VF_CACHE_INVALIDATE	(1 << 4)
-#define PIPE_CONTROL_CONST_CACHE_INVALIDATE	(1 << 3)
-#define PIPE_CONTROL_STATE_CACHE_INVALIDATE	(1 << 2)
-#define PIPE_CONTROL_STALL_AT_SCOREBOARD	(1 << 1)
-#define PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1 << 0)
-#define PIPE_CONTROL_PPGTT_WRITE	(0 << 2)
-#define PIPE_CONTROL_GLOBAL_GTT_WRITE	(1 << 2)
-
 /** @} */
 
 /** @{
@@ -123,7 +93,11 @@
 #define S2_TEX_COUNT_SHIFT_830		12
 #define S2_VERTEX_1_WIDTH_SHIFT_830	0
 #define S2_VERTEX_0_WIDTH_SHIFT_830	6
-/* S3 not interesting */
+
+#define S3_TEXCOORD_WRAP_SHORTEST_TCX(unit)	(1<<((unit)*4+3))
+#define S3_TEXCOORD_WRAP_SHORTEST_TCY(unit)	(1<<((unit)*4+2))
+#define S3_TEXCOORD_WRAP_SHORTEST_TCZ(unit)	(1<<((unit)*4+1))
+#define S3_TEXCOORD_PERSPECTIVE_DISABLE(unit)	(1<<((unit)*4+0))
 
 #define S4_POINT_WIDTH_SHIFT           23
 #define S4_POINT_WIDTH_MASK            (0x1ff<<23)
@@ -261,40 +235,3 @@
 #define BR13_8			(0x0 << 24)
 #define BR13_565		(0x1 << 24)
 #define BR13_8888		(0x3 << 24)
-
-#define FENCE_LINEAR 0
-#define FENCE_XMAJOR 1
-#define FENCE_YMAJOR 2
-
-/* Pipeline Statistics Counter Registers */
-#define IA_VERTICES_COUNT               0x2310
-#define IA_PRIMITIVES_COUNT             0x2318
-#define VS_INVOCATION_COUNT             0x2320
-#define HS_INVOCATION_COUNT             0x2300
-#define DS_INVOCATION_COUNT             0x2308
-#define GS_INVOCATION_COUNT             0x2328
-#define GS_PRIMITIVES_COUNT             0x2330
-#define CL_INVOCATION_COUNT             0x2338
-#define CL_PRIMITIVES_COUNT             0x2340
-#define PS_INVOCATION_COUNT             0x2348
-#define PS_DEPTH_COUNT                  0x2350
-
-#define SO_NUM_PRIM_STORAGE_NEEDED	0x2280
-#define SO_PRIM_STORAGE_NEEDED0_IVB	0x5240
-#define SO_PRIM_STORAGE_NEEDED1_IVB	0x5248
-#define SO_PRIM_STORAGE_NEEDED2_IVB	0x5250
-#define SO_PRIM_STORAGE_NEEDED3_IVB	0x5258
-
-#define SO_NUM_PRIMS_WRITTEN		0x2288
-#define SO_NUM_PRIMS_WRITTEN0_IVB	0x5200
-#define SO_NUM_PRIMS_WRITTEN1_IVB	0x5208
-#define SO_NUM_PRIMS_WRITTEN2_IVB	0x5210
-#define SO_NUM_PRIMS_WRITTEN3_IVB	0x5218
-
-#define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
-
-#define TIMESTAMP                       0x2358
-
-#define BCS_SWCTRL                      0x22200
-# define BCS_SWCTRL_SRC_Y               (1 << 0)
-# define BCS_SWCTRL_DST_Y               (1 << 1)