X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2FMakefile.sources;h=b1776a8513ae0f5b5c76fea9a80d33e974dae741;hb=951f56cd43bc870da2b0332cc388915ab604598e;hp=d8711edcf3939708dc7631771b6a16492fcca1b0;hpb=5136b67915ffbafa1715e08be4bd714c6ff540b3;p=mesa.git

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index d8711edcf39..b1776a8513a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -6,8 +6,6 @@ i965_compiler_FILES = \
 	brw_dead_control_flow.cpp \
 	brw_dead_control_flow.h \
 	brw_defines.h \
-	brw_device_info.c \
-	brw_device_info.h \
 	brw_disasm.c \
 	brw_eu.c \
 	brw_eu_compact.c \
@@ -46,7 +44,9 @@ i965_compiler_FILES = \
 	brw_nir.c \
 	brw_nir_analyze_boolean_resolves.c \
 	brw_nir_attribute_workarounds.c \
+	brw_nir_intrinsics.c \
 	brw_nir_opt_peephole_ffma.c \
+	brw_nir_tcs_workarounds.c \
 	brw_packed_float.c \
 	brw_predicated_break.cpp \
 	brw_reg.h \
@@ -78,25 +78,19 @@ i965_compiler_FILES = \
 	brw_vec4_tes.h \
 	brw_vec4_visitor.cpp \
 	brw_vec4_vs_visitor.cpp \
+	brw_vec4_vs.h \
 	brw_vue_map.c \
 	brw_wm_iz.cpp \
 	gen6_gs_visitor.cpp \
 	gen6_gs_visitor.h \
 	intel_asm_annotation.c \
-	intel_asm_annotation.h \
-	intel_debug.c \
-	intel_debug.h \
-	intel_reg.h \
-	intel_resolve_map.c \
-	intel_resolve_map.h
+	intel_asm_annotation.h
 
 i965_compiler_GENERATED_FILES = \
 	brw_nir_trig_workarounds.c
 
 i965_FILES = \
 	brw_binding_tables.c \
-	brw_blorp_blit.cpp \
-	brw_blorp_clear.cpp \
 	brw_blorp.c \
 	brw_blorp.h \
 	brw_cc.c \
@@ -115,7 +109,6 @@ i965_FILES = \
 	brw_context.h \
 	brw_cs.c \
 	brw_cs.h \
-	brw_cubemap_normalize.cpp \
 	brw_curbe.c \
 	brw_draw.c \
 	brw_draw.h \
@@ -131,18 +124,18 @@ i965_FILES = \
 	brw_gs_state.c \
 	brw_gs_surface_state.c \
 	brw_link.cpp \
-	brw_lower_texture_gradients.cpp \
-	brw_lower_unnormalized_offset.cpp \
 	brw_meta_util.c \
 	brw_meta_util.h \
 	brw_misc_state.c \
 	brw_multisample_state.h \
 	brw_nir_uniforms.cpp \
 	brw_object_purgeable.c \
-	brw_performance_monitor.c \
 	brw_pipe_control.c \
+	brw_performance_query.h \
+	brw_performance_query.c \
 	brw_program.c \
 	brw_program.h \
+	brw_program_cache.c \
 	brw_primitive_restart.c \
 	brw_queryobj.c \
 	brw_reset.c \
@@ -152,17 +145,16 @@ i965_FILES = \
 	brw_sf.h \
 	brw_sf_state.c \
 	brw_state_batch.c \
-	brw_state_cache.c \
 	brw_state_dump.c \
 	brw_state.h \
 	brw_state_upload.c \
 	brw_structs.h \
 	brw_surface_formats.c \
+	brw_sync.c \
 	brw_tcs.c \
 	brw_tcs_surface_state.c \
 	brw_tes.c \
 	brw_tes_surface_state.c \
-	brw_tex.c \
 	brw_tex_layout.c \
 	brw_urb.c \
 	brw_vs.c \
@@ -173,7 +165,6 @@ i965_FILES = \
 	brw_wm.h \
 	brw_wm_state.c \
 	brw_wm_surface_state.c \
-	gen6_blorp.c \
 	gen6_cc.c \
 	gen6_clip_state.c \
 	gen6_constant_state.c \
@@ -186,12 +177,10 @@ i965_FILES = \
 	gen6_scissor_state.c \
 	gen6_sf_state.c \
 	gen6_sol.c \
-	gen6_surface_state.c \
 	gen6_urb.c \
 	gen6_viewport_state.c \
 	gen6_vs_state.c \
 	gen6_wm_state.c \
-	gen7_blorp.c \
 	gen7_cs_state.c \
 	gen7_ds_state.c \
 	gen7_gs_state.c \
@@ -207,9 +196,7 @@ i965_FILES = \
 	gen7_wm_state.c \
 	gen7_wm_surface_state.c \
 	gen8_blend_state.c \
-	gen8_blorp.c \
 	gen8_depth_state.c \
-	gen8_disable.c \
 	gen8_draw_upload.c \
 	gen8_ds_state.c \
 	gen8_gs_state.c \
@@ -245,10 +232,11 @@ i965_FILES = \
 	intel_pixel_draw.c \
 	intel_pixel.h \
 	intel_pixel_read.c \
+	intel_resolve_map.c \
+	intel_resolve_map.h \
 	intel_screen.c \
 	intel_screen.h \
 	intel_state.c \
-	intel_syncobj.c \
 	intel_tex.c \
 	intel_tex_copy.c \
 	intel_tex.h \
@@ -259,3 +247,18 @@ i965_FILES = \
 	intel_tiled_memcpy.c \
 	intel_tiled_memcpy.h \
 	intel_upload.c
+
+i965_gen6_FILES = \
+	genX_blorp_exec.c
+
+i965_gen7_FILES = \
+	genX_blorp_exec.c
+
+i965_gen75_FILES = \
+	genX_blorp_exec.c
+
+i965_gen8_FILES = \
+	genX_blorp_exec.c
+
+i965_gen9_FILES = \
+	genX_blorp_exec.c