X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_blorp.cpp;h=eac1f005496a3d83b3a67dd7b6b0ae8ddc334ddf;hb=5c0436dbf87fef76ba67456f215d9285c38f1816;hp=91df346b887cf6e050dcac20dd3a84c3ce5fa2de;hpb=72aade48fe7d4c4099ef713887c06b3aaacf1acd;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 91df346b887..eac1f005496 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -21,6 +21,7 @@ * IN THE SOFTWARE. */ +#include #include "intel_batchbuffer.h" #include "intel_fbo.h" @@ -53,13 +54,22 @@ void brw_blorp_mip_info::set(struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer) { + /* Layer is a physical layer, so if this is a 2D multisample array texture + * using INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, then it had better + * be a multiple of num_samples. + */ + if (mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || + mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { + assert(layer % mt->num_samples == 0); + } + intel_miptree_check_level_layer(mt, level, layer); this->mt = mt; this->level = level; this->layer = layer; - this->width = mt->level[level].width; - this->height = mt->level[level].height; + this->width = minify(mt->physical_width0, level - mt->first_level); + this->height = minify(mt->physical_height0, level - mt->first_level); intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset); } @@ -68,16 +78,19 @@ void brw_blorp_surface_info::set(struct brw_context *brw, struct intel_mipmap_tree *mt, unsigned int level, unsigned int layer, - bool is_render_target) + mesa_format format, bool is_render_target) { brw_blorp_mip_info::set(mt, level, layer); this->num_samples = mt->num_samples; - this->array_spacing_lod0 = mt->array_spacing_lod0; + this->array_layout = mt->array_layout; this->map_stencil_as_y_tiled = false; this->msaa_layout = mt->msaa_layout; - switch (mt->format) { - case MESA_FORMAT_S8: + if (format == MESA_FORMAT_NONE) + format = mt->format; + + switch (format) { + case MESA_FORMAT_S_UINT8: /* The miptree is a W-tiled stencil buffer. Surface states can't be set * up for W tiling, so we'll need to use Y tiling and have the WM * program swizzle the coordinates. @@ -85,7 +98,7 @@ brw_blorp_surface_info::set(struct brw_context *brw, this->map_stencil_as_y_tiled = true; this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM; break; - case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_Z24_UNORM_X8_UINT: /* It would make sense to use BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS * here, but unfortunately it isn't supported as a render target, which * would prevent us from blitting to 24-bit depth. @@ -98,14 +111,14 @@ brw_blorp_surface_info::set(struct brw_context *brw, */ this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; - case MESA_FORMAT_Z32_FLOAT: + case MESA_FORMAT_Z_FLOAT32: this->brw_surfaceformat = BRW_SURFACEFORMAT_R32_FLOAT; break; - case MESA_FORMAT_Z16: + case MESA_FORMAT_Z_UNORM16: this->brw_surfaceformat = BRW_SURFACEFORMAT_R16_UNORM; break; default: { - gl_format linear_format = _mesa_get_srgb_format_linear(mt->format); + mesa_format linear_format = _mesa_get_srgb_format_linear(format); if (is_render_target) { assert(brw->format_supported_as_render_target[linear_format]); this->brw_surfaceformat = brw->render_target_format[linear_format]; @@ -129,36 +142,33 @@ uint32_t brw_blorp_surface_info::compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const { - struct intel_region *region = mt->region; uint32_t mask_x, mask_y; - intel_region_get_tile_masks(region, &mask_x, &mask_y, - map_stencil_as_y_tiled); + intel_miptree_get_tile_masks(mt, &mask_x, &mask_y, map_stencil_as_y_tiled); *tile_x = x_offset & mask_x; *tile_y = y_offset & mask_y; - return intel_region_get_aligned_offset(region, x_offset & ~mask_x, - y_offset & ~mask_y, - map_stencil_as_y_tiled); + return intel_miptree_get_aligned_offset(mt, x_offset & ~mask_x, + y_offset & ~mask_y, + map_stencil_as_y_tiled); } -brw_blorp_params::brw_blorp_params() +brw_blorp_params::brw_blorp_params(unsigned num_varyings, + unsigned num_draw_buffers, + unsigned num_layers) : x0(0), y0(0), x1(0), y1(0), depth_format(0), hiz_op(GEN6_HIZ_OP_NONE), - fast_clear_op(GEN7_FAST_CLEAR_OP_NONE), - num_samples(0), - use_wm_prog(false) + use_wm_prog(false), + num_varyings(num_varyings), + num_draw_buffers(num_draw_buffers), + num_layers(num_layers) { - color_write_disable[0] = false; - color_write_disable[1] = false; - color_write_disable[2] = false; - color_write_disable[3] = false; } extern "C" { @@ -184,10 +194,14 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, } DBG("%s %s to mt %p level %d layer %d\n", - __FUNCTION__, opname, mt, level, layer); + __func__, opname, mt, level, layer); - brw_hiz_op_params params(mt, level, layer, op); - brw_blorp_exec(brw, ¶ms); + if (brw->gen >= 8) { + gen8_hiz_exec(brw, mt, level, layer, op); + } else { + brw_hiz_op_params params(mt, level, layer, op); + brw_blorp_exec(brw, ¶ms); + } } } /* extern "C" */ @@ -195,6 +209,26 @@ intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt, void brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) { + struct gl_context *ctx = &brw->ctx; + uint32_t estimated_max_batch_usage = 1500; + bool check_aperture_failed_once = false; + + /* Flush the sampler and render caches. We definitely need to flush the + * sampler cache so that we get updated contents from the render cache for + * the glBlitFramebuffer() source. Also, we are sometimes warned in the + * docs to flush the cache between reinterpretations of the same surface + * data with different formats, which blorp does for stencil and depth + * data. + */ + brw_emit_mi_flush(brw); + +retry: + intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING); + intel_batchbuffer_save_state(brw); + drm_intel_bo *saved_bo = brw->batch.bo; + uint32_t saved_used = USED_BATCH(brw->batch); + uint32_t saved_state_batch_offset = brw->batch.state_batch_offset; + switch (brw->gen) { case 6: gen6_blorp_exec(brw, params); @@ -204,8 +238,36 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) break; default: /* BLORP is not supported before Gen6. */ - assert(false); - break; + unreachable("not reached"); + } + + /* Make sure we didn't wrap the batch unintentionally, and make sure we + * reserved enough space that a wrap will never happen. + */ + assert(brw->batch.bo == saved_bo); + assert((USED_BATCH(brw->batch) - saved_used) * 4 + + (saved_state_batch_offset - brw->batch.state_batch_offset) < + estimated_max_batch_usage); + /* Shut up compiler warnings on release build */ + (void)saved_bo; + (void)saved_used; + (void)saved_state_batch_offset; + + /* Check if the blorp op we just did would make our batch likely to fail to + * map all the BOs into the GPU at batch exec time later. If so, flush the + * batch and try again with nothing else in the batch. + */ + if (dri_bufmgr_check_aperture_space(&brw->batch.bo, 1)) { + if (!check_aperture_failed_once) { + check_aperture_failed_once = true; + intel_batchbuffer_reset_to_saved(brw); + intel_batchbuffer_flush(brw); + goto retry; + } else { + int ret = intel_batchbuffer_flush(brw); + WARN_ONCE(ret == -ENOSPC, + "i965: blorp emit exceeded available aperture space\n"); + } } if (unlikely(brw->always_flush_batch)) @@ -214,17 +276,14 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) /* We've smashed all state compared to what the normal 3D pipeline * rendering tracks for GL. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; - brw->state_batch_count = 0; - brw->batch.need_workaround_flush = true; + brw->ctx.NewDriverState = ~0ull; + brw->no_depth_or_stencil = false; brw->ib.type = -1; - intel_batchbuffer_clear_cache(brw); /* Flush the sampler cache so any texturing from the destination is * coherent. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); } brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt, @@ -267,13 +326,13 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt, x1 = depth.width; y1 = depth.height; - assert(intel_miptree_slice_has_hiz(mt, level, layer)); + assert(intel_miptree_level_has_hiz(mt, level)); switch (mt->format) { - case MESA_FORMAT_Z16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break; - case MESA_FORMAT_Z32_FLOAT: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break; - case MESA_FORMAT_X8_Z24: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break; - default: assert(0); break; + case MESA_FORMAT_Z_UNORM16: depth_format = BRW_DEPTHFORMAT_D16_UNORM; break; + case MESA_FORMAT_Z_FLOAT32: depth_format = BRW_DEPTHFORMAT_D32_FLOAT; break; + case MESA_FORMAT_Z24_UNORM_X8_UINT: depth_format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break; + default: unreachable("not reached"); } }