X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_blorp.h;h=ff68000a2941aec96712dc1ebf34dba9d1f719b1;hb=8776b1b14b229d110f283f5da8c3c36261068ede;hp=c00766c5bf694301233b804dbde3560f0600d0ad;hpb=8b1f467cce34340637e9baca4847fc5273cf7541;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index c00766c5bf6..ff68000a294 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.h +++ b/src/mesa/drivers/dri/i965/brw_blorp.h @@ -26,10 +26,31 @@ #include #include "brw_context.h" +#include "brw_reg.h" #include "intel_mipmap_tree.h" struct brw_context; +#ifdef __cplusplus +extern "C" { +#endif + +void +brw_blorp_blit_miptrees(struct brw_context *brw, + struct intel_mipmap_tree *src_mt, + unsigned src_level, unsigned src_layer, + mesa_format src_format, + struct intel_mipmap_tree *dst_mt, + unsigned dst_level, unsigned dst_layer, + mesa_format dst_format, + float src_x0, float src_y0, + float src_x1, float src_y1, + float dst_x0, float dst_y0, + float dst_x1, float dst_y1, + GLenum filter, bool mirror_x, bool mirror_y); + +#ifdef __cplusplus +} /* end extern "C" */ /** * Binding table indices used by BLORP. @@ -46,19 +67,52 @@ class brw_blorp_mip_info public: brw_blorp_mip_info(); - virtual void set(struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer); - void get_draw_offsets(uint32_t *draw_x, uint32_t *draw_y) const; - - void get_miplevel_dims(uint32_t *width, uint32_t *height) const - { - *width = mt->level[level].width; - *height = mt->level[level].height; - } + void set(struct intel_mipmap_tree *mt, + unsigned int level, unsigned int layer); struct intel_mipmap_tree *mt; - unsigned int level; - unsigned int layer; + + /** + * The miplevel to use. + */ + uint32_t level; + + /** + * The 2D layer within the miplevel. Combined, level and layer define the + * 2D miptree slice to use. + * + * Note: if mt is a 2D multisample array texture on Gen7+ using + * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical + * layer holding sample 0. So, for example, if mt->num_samples == 4, then + * logical layer n corresponds to layer == 4*n. + */ + uint32_t layer; + + /** + * Width of the miplevel to be used. For surfaces using + * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels. + */ + uint32_t width; + + /** + * Height of the miplevel to be used. For surfaces using + * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels. + */ + uint32_t height; + + /** + * X offset within the surface to texture from (or render to). For + * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not + * pixels. + */ + uint32_t x_offset; + + /** + * Y offset within the surface to texture from (or render to). For + * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not + * pixels. + */ + uint32_t y_offset; }; class brw_blorp_surface_info : public brw_blorp_mip_info @@ -66,16 +120,20 @@ class brw_blorp_surface_info : public brw_blorp_mip_info public: brw_blorp_surface_info(); - virtual void set(struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer); + void set(struct brw_context *brw, + struct intel_mipmap_tree *mt, + unsigned int level, unsigned int layer, + mesa_format format, bool is_render_target); + + uint32_t compute_tile_offsets(uint32_t *tile_x, uint32_t *tile_y) const; /* Setting this flag indicates that the buffer's contents are W-tiled * stencil data, but the surface state should be set up for Y tiled - * MESA_FORMAT_R8 data (this is necessary because surface states don't + * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't * support W tiling). * * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of - * MESA_FORMAT_R8 data are 128 pixels wide by 32 pixels high, the width and + * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and * pitch stored in the surface state will be multiplied by 2, and the * height will be halved. Also, since W and Y tiles store their data in a * different order, the width and height will be rounded up to a multiple @@ -86,34 +144,52 @@ public: unsigned num_samples; - /* Setting this flag indicates that the surface should be set up in - * ARYSPC_LOD0 mode. Ignored prior to Gen7. + /** + * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE), + * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD). + * + * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored + * prior to Gen7. + */ + enum miptree_array_layout array_layout; + + /** + * Format that should be used when setting up the surface state for this + * surface. Should correspond to one of the BRW_SURFACEFORMAT_* enums. + */ + uint32_t brw_surfaceformat; + + /** + * For MSAA surfaces, MSAA layout that should be used when setting up the + * surface state for this surface. */ - bool array_spacing_lod0; + intel_msaa_layout msaa_layout; }; struct brw_blorp_coord_transform_params { - void setup(GLuint src0, GLuint dst0, GLuint dst1, + void setup(GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1, bool mirror); - int16_t multiplier; - int16_t offset; + float multiplier; + float offset; }; struct brw_blorp_wm_push_constants { - uint16_t dst_x0; - uint16_t dst_x1; - uint16_t dst_y0; - uint16_t dst_y1; + uint32_t dst_x0; + uint32_t dst_x1; + uint32_t dst_y0; + uint32_t dst_y1; + /* Top right coordinates of the rectangular grid used for scaled blitting */ + float rect_grid_x1; + float rect_grid_y1; brw_blorp_coord_transform_params x_transform; brw_blorp_coord_transform_params y_transform; - /* Pad out to an integral number of registers */ - uint16_t pad[8]; + uint32_t pad[6]; }; /* Every 32 bytes of push constant data constitutes one GEN register. */ @@ -131,6 +207,14 @@ struct brw_blorp_prog_data bool persample_msaa_dispatch; }; + +enum gen7_fast_clear_op { + GEN7_FAST_CLEAR_OP_NONE, + GEN7_FAST_CLEAR_OP_FAST_CLEAR, + GEN7_FAST_CLEAR_OP_RESOLVE, +}; + + class brw_blorp_params { public: @@ -148,14 +232,15 @@ public: brw_blorp_surface_info src; brw_blorp_surface_info dst; enum gen6_hiz_op hiz_op; - unsigned num_samples; + enum gen7_fast_clear_op fast_clear_op; bool use_wm_prog; brw_blorp_wm_push_constants wm_push_consts; + bool color_write_disable[4]; }; void -brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params); +brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params); /** @@ -185,26 +270,35 @@ struct brw_blorp_blit_prog_key */ unsigned tex_samples; + /* MSAA layout that has been configured in the surface state for texturing + * from. + */ + intel_msaa_layout tex_layout; + /* Actual number of samples per pixel in the source image. */ unsigned src_samples; - /* If src_samples > 0, whether or not the source image uses an interleaved - * MSAA layout. False if src_samples == 0. - */ - bool src_interleaved; + /* Actual MSAA layout used by the source image. */ + intel_msaa_layout src_layout; /* Number of samples per pixel that have been configured in the render * target. */ unsigned rt_samples; + /* MSAA layout that has been configured in the render target. */ + intel_msaa_layout rt_layout; + /* Actual number of samples per pixel in the destination image. */ unsigned dst_samples; - /* If dst_samples > 0, whether or not the destination image uses an - * interleaved MSAA layout. False if dst_samples == 0. + /* Actual MSAA layout used by the destination image. */ + intel_msaa_layout dst_layout; + + /* Type of the data to be read from the texture (one of + * BRW_REGISTER_TYPE_{UD,D,F}). */ - bool dst_interleaved; + enum brw_reg_type texture_data_type; /* True if the source image is W tiled. If true, the surface state for the * source image must be configured as Y tiled, and tex_samples must be 0. @@ -234,6 +328,18 @@ struct brw_blorp_blit_prog_key * than one sample per pixel. */ bool persample_msaa_dispatch; + + /* True for scaled blitting. */ + bool blit_scaled; + + /* Scale factors between the pixel grid and the grid of samples. We're + * using grid of samples for bilinear filetring in multisample scaled blits. + */ + float x_scale; + float y_scale; + + /* True for blits with filter = GL_LINEAR. */ + bool bilinear_filter; }; class brw_blorp_blit_params : public brw_blorp_params @@ -241,11 +347,16 @@ class brw_blorp_blit_params : public brw_blorp_params public: brw_blorp_blit_params(struct brw_context *brw, struct intel_mipmap_tree *src_mt, + unsigned src_level, unsigned src_layer, + mesa_format src_format, struct intel_mipmap_tree *dst_mt, - GLuint src_x0, GLuint src_y0, - GLuint dst_x0, GLuint dst_y0, - GLuint width, GLuint height, - bool mirror_x, bool mirror_y); + unsigned dst_level, unsigned dst_layer, + mesa_format dst_format, + GLfloat src_x0, GLfloat src_y0, + GLfloat src_x1, GLfloat src_y1, + GLfloat dst_x0, GLfloat dst_y0, + GLfloat dst_x1, GLfloat dst_y1, + GLenum filter, bool mirror_x, bool mirror_y); virtual uint32_t get_wm_prog(struct brw_context *brw, brw_blorp_prog_data **prog_data) const; @@ -264,14 +375,6 @@ private: void gen6_blorp_init(struct brw_context *brw); -void -gen6_blorp_compute_tile_masks(const brw_blorp_params *params, - uint32_t *tile_mask_x, uint32_t *tile_mask_y); - -void -gen6_blorp_emit_batch_head(struct brw_context *brw, - const brw_blorp_params *params); - void gen6_blorp_emit_state_base_address(struct brw_context *brw, const brw_blorp_params *params); @@ -317,4 +420,10 @@ gen6_blorp_emit_clip_disable(struct brw_context *brw, void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, const brw_blorp_params *params); + +uint32_t +gen6_blorp_emit_sampler_state(struct brw_context *brw, + const brw_blorp_params *params); /** \} */ + +#endif /* __cplusplus */