X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_bufmgr.h;h=32fc7a553c95277e236cdddebd8d17548644344b;hb=bb84fa146f2252f22999205a2904d8a948bffd3b;hp=7423dde2d368000dab54aea108d6eabac13f8b9e;hpb=c366943ebffefc4a8acb3fdd08dd45934098595b;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h index 7423dde2d36..32fc7a553c9 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h @@ -37,6 +37,8 @@ #include #include #include +#include + #include "util/u_atomic.h" #include "util/list.h" @@ -47,6 +49,42 @@ extern "C" { struct gen_device_info; struct brw_context; +/** + * Memory zones. When allocating a buffer, you can request that it is + * placed into a specific region of the virtual address space (PPGTT). + * + * Most buffers can go anywhere (BRW_MEMZONE_OTHER). Some buffers are + * accessed via an offset from a base address. STATE_BASE_ADDRESS has + * a maximum 4GB size for each region, so we need to restrict those + * buffers to be within 4GB of the base. Each memory zone corresponds + * to a particular base address. + * + * Currently, i965 partitions the address space into two regions: + * + * - Low 4GB + * - Full 48-bit address space + * + * Eventually, we hope to carve out 4GB of VMA for each base address. + */ +enum brw_memory_zone { + BRW_MEMZONE_LOW_4G, + BRW_MEMZONE_OTHER, + + /* Shaders - Instruction State Base Address */ + BRW_MEMZONE_SHADER = BRW_MEMZONE_LOW_4G, + + /* Scratch - General State Base Address */ + BRW_MEMZONE_SCRATCH = BRW_MEMZONE_LOW_4G, + + /* Surface State Base Address */ + BRW_MEMZONE_SURFACE = BRW_MEMZONE_LOW_4G, + + /* Dynamic State Base Address */ + BRW_MEMZONE_DYNAMIC = BRW_MEMZONE_LOW_4G, +}; + +#define BRW_MEMZONE_COUNT (BRW_MEMZONE_OTHER + 1) + struct brw_bo { /** * Size in bytes of the buffer object. @@ -56,13 +94,6 @@ struct brw_bo { */ uint64_t size; - /** - * Alignment requirement for object - * - * Used for GTT mapping & pinning the object. - */ - uint64_t align; - /** Buffer manager context associated with this buffer object */ struct brw_bufmgr *bufmgr; @@ -70,11 +101,33 @@ struct brw_bo { uint32_t gem_handle; /** - * Last seen card virtual address (offset from the beginning of the - * aperture) for the object. This should be used to fill relocation - * entries when calling brw_bo_emit_reloc() + * Offset of the buffer inside the Graphics Translation Table. + * + * This is effectively our GPU address for the buffer and we use it + * as our base for all state pointers into the buffer. However, since the + * kernel may be forced to move it around during the course of the + * buffer's lifetime, we can only know where the buffer was on the last + * execbuf. We presume, and are usually right, that the buffer will not + * move and so we use that last offset for the next batch and by doing + * so we can avoid having the kernel perform a relocation fixup pass as + * our pointers inside the batch will be using the correct base offset. + * + * Since we do use it as a base address for the next batch of pointers, + * the kernel treats our offset as a request, and if possible will + * arrange the buffer to placed at that address (trying to balance + * the cost of buffer migration versus the cost of performing + * relocations). Furthermore, we can force the kernel to place the buffer, + * or report a failure if we specified a conflicting offset, at our chosen + * offset by specifying EXEC_OBJECT_PINNED. + * + * Note the GTT may be either per context, or shared globally across the + * system. On a shared system, our buffers have to contend for address + * space with both aperture mappings and framebuffers and so are more + * likely to be moved. On a full ppGTT system, each batch exists in its + * own GTT, and so each buffer may have their own offset within each + * context. */ - uint64_t offset64; + uint64_t gtt_offset; /** * The validation list index for this buffer, or -1 when not in a batch. @@ -98,9 +151,6 @@ struct brw_bo { int refcount; const char *name; -#ifndef EXEC_OBJECT_CAPTURE -#define EXEC_OBJECT_CAPTURE (1<<7) -#endif uint64_t kflags; /** @@ -156,7 +206,7 @@ struct brw_bo { * using brw_bo_map() to be used by the CPU. */ struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name, - uint64_t size, uint64_t alignment); + uint64_t size, enum brw_memory_zone memzone); /** * Allocate a tiled buffer object. @@ -172,6 +222,7 @@ struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name, struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char *name, uint64_t size, + enum brw_memory_zone memzone, uint32_t tiling_mode, uint32_t pitch, unsigned flags); @@ -194,6 +245,7 @@ struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, struct brw_bo *brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr, const char *name, int x, int y, int cpp, + enum brw_memory_zone memzone, uint32_t tiling_mode, uint32_t *pitch, unsigned flags); @@ -233,7 +285,7 @@ MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct brw_bo *bo, unsigned * Reduces the refcount on the userspace mapping of the buffer * object. */ -static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; } +static inline int brw_bo_unmap(UNUSED struct brw_bo *bo) { return 0; } /** Write data into an object. */ int brw_bo_subdata(struct brw_bo *bo, uint64_t offset, @@ -291,8 +343,7 @@ int brw_bo_busy(struct brw_bo *bo); int brw_bo_madvise(struct brw_bo *bo, int madv); /* drm_bacon_bufmgr_gem.c */ -struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, - int fd, int batch_size); +struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd); struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr, const char *name, unsigned int handle); @@ -301,15 +352,28 @@ void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr); int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns); uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr); + +int brw_hw_context_set_priority(struct brw_bufmgr *bufmgr, + uint32_t ctx_id, + int priority); + void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id); int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd); struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd); +struct brw_bo *brw_bo_gem_create_from_prime_tiled(struct brw_bufmgr *bufmgr, + int prime_fd, + uint32_t tiling_mode, + uint32_t stride); + +uint32_t brw_bo_export_gem_handle(struct brw_bo *bo); int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset, uint64_t *result); +bool brw_using_softpin(struct brw_bufmgr *bufmgr); + /** @{ */ #if defined(__cplusplus)