X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_cc.c;h=02f5a3a76fb3e31a6f1ed4ccdea0eb9868cfa3a9;hb=530445330b403d835a4027b41388b5eea8c2e1ab;hp=408783a3e6a87b38766220f26103605de9a25dba;hpb=3f55683927278e57f3ef8a151d15f4cffdc060dc;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index 408783a3e6a..02f5a3a76fb 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -1,8 +1,8 @@ /* Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + Intel funded Tungsten Graphics to develop this 3D driver. - + Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including @@ -10,11 +10,11 @@ distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: - + The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. - + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. @@ -22,11 +22,11 @@ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - + **********************************************************************/ /* * Authors: - * Keith Whitwell + * Keith Whitwell */ @@ -35,30 +35,52 @@ #include "brw_defines.h" #include "brw_util.h" #include "main/macros.h" +#include "main/stencil.h" #include "intel_batchbuffer.h" -void -brw_update_cc_vp(struct brw_context *brw) +static void +brw_upload_cc_vp(struct brw_context *brw) { - struct gl_context *ctx = &brw->intel.ctx; - struct brw_cc_viewport ccv; - - memset(&ccv, 0, sizeof(ccv)); + struct gl_context *ctx = &brw->ctx; + struct brw_cc_viewport *ccv; + + ccv = brw_state_batch(brw, AUB_TRACE_CC_VP_STATE, + sizeof(*ccv) * ctx->Const.MaxViewports, 32, + &brw->cc.vp_offset); + + /* _NEW_TRANSFORM */ + for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) { + if (ctx->Transform.DepthClamp) { + /* _NEW_VIEWPORT */ + ccv[i].min_depth = MIN2(ctx->ViewportArray[i].Near, + ctx->ViewportArray[i].Far); + ccv[i].max_depth = MAX2(ctx->ViewportArray[i].Near, + ctx->ViewportArray[i].Far); + } else { + ccv[i].min_depth = 0.0; + ccv[i].max_depth = 1.0; + } + } - /* _NEW_TRANSOFORM */ - if (ctx->Transform.DepthClamp) { - /* _NEW_VIEWPORT */ - ccv.min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far); - ccv.max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far); + if (brw->gen >= 7) { + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2)); + OUT_BATCH(brw->cc.vp_offset); + ADVANCE_BATCH(); } else { - ccv.min_depth = 0.0; - ccv.max_depth = 1.0; + brw->state.dirty.brw |= BRW_NEW_CC_VP; } - - drm_intel_bo_unreference(brw->cc.vp_bo); - brw->cc.vp_bo = brw_cache_data(&brw->cache, BRW_CC_VP, &ccv, sizeof(ccv)); } +const struct brw_tracked_state brw_cc_vp = { + .dirty = { + .mesa = _NEW_TRANSFORM | + _NEW_VIEWPORT, + .brw = BRW_NEW_BATCH, + }, + .emit = brw_upload_cc_vp +}; + /** * Modify blend function to force destination alpha to 1.0 * @@ -66,8 +88,8 @@ brw_update_cc_vp(struct brw_context *brw) * replace it with a function that hard-wires destination alpha to 1.0. This * is used when rendering to xRGB targets. */ -static GLenum -fix_xRGB_alpha(GLenum function) +GLenum +brw_fix_xRGB_alpha(GLenum function) { switch (function) { case GL_DST_ALPHA: @@ -81,24 +103,19 @@ fix_xRGB_alpha(GLenum function) return function; } -static void prepare_cc_unit(struct brw_context *brw) -{ - brw_add_validated_bo(brw, brw->cc.vp_bo); -} - /** - * Creates the state cache entry for the given CC unit key. + * Creates a CC unit packet from the current blend state. */ static void upload_cc_unit(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; - struct gl_context *ctx = &brw->intel.ctx; + struct gl_context *ctx = &brw->ctx; struct brw_cc_unit_state *cc; - cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset); + cc = brw_state_batch(brw, AUB_TRACE_CC_STATE, + sizeof(*cc), 64, &brw->cc.state_offset); memset(cc, 0, sizeof(*cc)); - /* _NEW_STENCIL */ + /* _NEW_STENCIL | _NEW_BUFFERS */ if (ctx->Stencil._Enabled) { const unsigned back = ctx->Stencil._BackFace; @@ -111,7 +128,7 @@ static void upload_cc_unit(struct brw_context *brw) intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); cc->cc0.stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); - cc->cc1.stencil_ref = ctx->Stencil.Ref[0]; + cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0); cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0]; cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0]; @@ -125,7 +142,7 @@ static void upload_cc_unit(struct brw_context *brw) intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); cc->cc0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); - cc->cc1.bf_stencil_ref = ctx->Stencil.Ref[back]; + cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back); cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; } @@ -138,7 +155,7 @@ static void upload_cc_unit(struct brw_context *brw) } /* _NEW_COLOR */ - if (ctx->Color._LogicOpEnabled && ctx->Color.LogicOp != GL_COPY) { + if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) { cc->cc2.logicop_enable = 1; cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp); } else if (ctx->Color.BlendEnabled) { @@ -154,10 +171,10 @@ static void upload_cc_unit(struct brw_context *brw) * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO. */ if (ctx->DrawBuffer->Visual.alphaBits == 0) { - srcRGB = fix_xRGB_alpha(srcRGB); - srcA = fix_xRGB_alpha(srcA); - dstRGB = fix_xRGB_alpha(dstRGB); - dstA = fix_xRGB_alpha(dstA); + srcRGB = brw_fix_xRGB_alpha(srcRGB); + srcA = brw_fix_xRGB_alpha(srcA); + dstRGB = brw_fix_xRGB_alpha(dstRGB); + dstA = brw_fix_xRGB_alpha(dstA); } if (eqRGB == GL_MIN || eqRGB == GL_MAX) { @@ -182,7 +199,8 @@ static void upload_cc_unit(struct brw_context *brw) eqA != eqRGB); } - if (ctx->Color.AlphaEnabled) { + /* _NEW_BUFFERS */ + if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) { cc->cc3.alpha_test = 1; cc->cc3.alpha_test_func = intel_translate_compare_func(ctx->Color.AlphaFunc); @@ -205,53 +223,53 @@ static void upload_cc_unit(struct brw_context *brw) cc->cc2.depth_write_enable = ctx->Depth.Mask; } - if (intel->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS)) + if (brw->stats_wm || unlikely(INTEL_DEBUG & DEBUG_STATS)) cc->cc5.statistics_enable = 1; - /* CACHE_NEW_CC_VP */ - cc->cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */ + /* BRW_NEW_CC_VP */ + cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 + + brw->cc.vp_offset) >> 5; /* reloc */ - brw->state.dirty.cache |= CACHE_NEW_CC_UNIT; + brw->state.dirty.brw |= BRW_NEW_GEN4_UNIT_STATE; /* Emit CC viewport relocation */ - drm_intel_bo_emit_reloc(brw->intel.batch->buf, + drm_intel_bo_emit_reloc(brw->batch.bo, (brw->cc.state_offset + offsetof(struct brw_cc_unit_state, cc4)), - brw->cc.vp_bo, 0, + brw->batch.bo, brw->cc.vp_offset, I915_GEM_DOMAIN_INSTRUCTION, 0); } const struct brw_tracked_state brw_cc_unit = { .dirty = { - .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH, - .brw = BRW_NEW_BATCH, - .cache = CACHE_NEW_CC_VP + .mesa = _NEW_BUFFERS | + _NEW_COLOR | + _NEW_DEPTH | + _NEW_STENCIL, + .brw = BRW_NEW_BATCH | + BRW_NEW_CC_VP | + BRW_NEW_STATS_WM, }, - .prepare = prepare_cc_unit, .emit = upload_cc_unit, }; static void upload_blend_constant_color(struct brw_context *brw) { - struct gl_context *ctx = &brw->intel.ctx; - struct brw_blend_constant_color bcc; - - memset(&bcc, 0, sizeof(bcc)); - bcc.header.opcode = _3DSTATE_BLEND_CONSTANT_COLOR; - bcc.header.length = sizeof(bcc)/4-2; - bcc.blend_constant_color[0] = ctx->Color.BlendColor[0]; - bcc.blend_constant_color[1] = ctx->Color.BlendColor[1]; - bcc.blend_constant_color[2] = ctx->Color.BlendColor[2]; - bcc.blend_constant_color[3] = ctx->Color.BlendColor[3]; - - BRW_CACHED_BATCH_STRUCT(brw, &bcc); + struct gl_context *ctx = &brw->ctx; + + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2)); + OUT_BATCH_F(ctx->Color.BlendColorUnclamped[0]); + OUT_BATCH_F(ctx->Color.BlendColorUnclamped[1]); + OUT_BATCH_F(ctx->Color.BlendColorUnclamped[2]); + OUT_BATCH_F(ctx->Color.BlendColorUnclamped[3]); + ADVANCE_BATCH(); } const struct brw_tracked_state brw_blend_constant_color = { .dirty = { .mesa = _NEW_COLOR, .brw = BRW_NEW_CONTEXT, - .cache = 0 }, .emit = upload_blend_constant_color };