X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_clear.c;h=488732cb4f5ba2f3f10c14639e031c7cb9e39842;hb=8bed1adfc144d9ae8d55ccb9b277942da8a78064;hp=604a68037bbf9cb376668202dcc61778d0fa21cf;hpb=a3967ff441e95289a0a33a4a02ab7cd15b010a51;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 604a68037bb..488732cb4f5 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -1,14 +1,13 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * Copyright 2009 Intel Corporation. +/* + * Copyright 2003 VMware, Inc. + * Copyright 2009, 2012 Intel Corporation. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to + * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * @@ -18,25 +17,25 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ + */ -#include "main/glheader.h" #include "main/mtypes.h" #include "main/condrender.h" #include "swrast/swrast.h" #include "drivers/common/meta.h" -#include "intel_context.h" +#include "intel_batchbuffer.h" #include "intel_blit.h" -#include "intel_clear.h" #include "intel_fbo.h" -#include "intel_regions.h" +#include "intel_mipmap_tree.h" + +#include "brw_context.h" +#include "brw_blorp.h" #define FILE_DEBUG_FLAG DEBUG_BLIT @@ -75,120 +74,207 @@ debug_mask(const char *name, GLbitfield mask) } /** - * Called by ctx->Driver.Clear. + * Returns true if the scissor is a noop (cuts out nothing). */ -static void -intelClear(struct gl_context *ctx, GLbitfield mask) +static bool +noop_scissor(struct gl_framebuffer *fb) +{ + return fb->_Xmin <= 0 && + fb->_Ymin <= 0 && + fb->_Xmax >= fb->Width && + fb->_Ymax >= fb->Height; +} + +/** + * Implements fast depth clears on gen6+. + * + * Fast clears basically work by setting a flag in each of the subspans + * represented in the HiZ buffer that says "When you need the depth values for + * this subspan, it's the hardware's current clear value." Then later rendering + * can just use the static clear value instead of referencing memory. + * + * The tricky part of the implementation is that you have to have the clear + * value that was used on the depth buffer in place for all further rendering, + * at least until a resolve to the real depth buffer happens. + */ +static bool +brw_fast_clear_depth(struct gl_context *ctx) { - struct intel_context *intel = intel_context(ctx); - const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]); - GLbitfield tri_mask = 0; - GLbitfield blit_mask = 0; - GLbitfield swrast_mask = 0; + struct brw_context *brw = brw_context(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - struct intel_renderbuffer *irb; - int i; + struct intel_renderbuffer *depth_irb = + intel_get_renderbuffer(fb, BUFFER_DEPTH); + struct intel_mipmap_tree *mt = depth_irb->mt; + struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH]; - if (!_mesa_check_conditional_render(ctx)) - return; + if (brw->gen < 6) + return false; - if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) { - intel->front_buffer_dirty = true; + if (!intel_renderbuffer_has_hiz(depth_irb)) + return false; + + /* We only handle full buffer clears -- otherwise you'd have to track whether + * a previous clear had happened at a different clear value and resolve it + * first. + */ + if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) { + perf_debug("Failed to fast clear %dx%d depth because of scissors. " + "Possible 5%% performance win if avoided.\n", + mt->logical_width0, mt->logical_height0); + return false; } - if (0) - fprintf(stderr, "%s\n", __FUNCTION__); + uint32_t depth_clear_value; + switch (mt->format) { + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + case MESA_FORMAT_Z24_UNORM_S8_UINT: + /* From the Sandy Bridge PRM, volume 2 part 1, page 314: + * + * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be + * enabled (the legacy method of clearing must be performed): + * + * - If the depth buffer format is D32_FLOAT_S8X24_UINT or + * D24_UNORM_S8_UINT. + */ + return false; - /* Get SW clears out of the way: Anything without an intel_renderbuffer */ - for (i = 0; i < BUFFER_COUNT; i++) { - if (!(mask & (1 << i))) - continue; + case MESA_FORMAT_Z_FLOAT32: + depth_clear_value = float_as_int(ctx->Depth.Clear); + break; - irb = intel_get_renderbuffer(fb, i); - if (unlikely(!irb)) { - swrast_mask |= (1 << i); - mask &= ~(1 << i); - } - } - if (unlikely(swrast_mask)) { - debug_mask("swrast", swrast_mask); - _swrast_Clear(ctx, swrast_mask); - } + case MESA_FORMAT_Z_UNORM16: + /* From the Sandy Bridge PRM, volume 2 part 1, page 314: + * + * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be + * enabled (the legacy method of clearing must be performed): + * + * - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the + * width of the map (LOD0) is not multiple of 16, fast clear + * optimization must be disabled. + */ + if (brw->gen == 6 && + (minify(mt->physical_width0, + depth_irb->mt_level - mt->first_level) % 16) != 0) + return false; + /* FALLTHROUGH */ - /* HW color buffers (front, back, aux, generic FBO, etc) */ - if (intel->gen < 6 && colorMask == ~0) { - /* clear all R,G,B,A */ - blit_mask |= (mask & BUFFER_BITS_COLOR); + default: + if (brw->gen >= 8) + depth_clear_value = float_as_int(ctx->Depth.Clear); + else + depth_clear_value = fb->_DepthMax * ctx->Depth.Clear; + break; } - else { - /* glColorMask in effect */ - tri_mask |= (mask & BUFFER_BITS_COLOR); + + /* If we're clearing to a new clear value, then we need to resolve any clear + * flags out of the HiZ buffer into the real depth buffer. + */ + if (mt->depth_clear_value != depth_clear_value) { + intel_miptree_all_slices_resolve_depth(brw, mt); + mt->depth_clear_value = depth_clear_value; } - /* Make sure we have up to date buffers before we start looking at - * the tiling bits to determine how to clear. */ - intel_prepare_render(intel); + /* From the Sandy Bridge PRM, volume 2 part 1, page 313: + * + * "If other rendering operations have preceded this clear, a + * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled + * must be issued before the rectangle primitive used for the depth + * buffer clear operation. + */ + brw_emit_mi_flush(brw); - /* HW stencil */ - if (mask & BUFFER_BIT_STENCIL) { - const struct intel_region *stencilRegion - = intel_get_rb_region(fb, BUFFER_STENCIL); - if (stencilRegion) { - /* have hw stencil */ - if (stencilRegion->tiling == I915_TILING_Y || - (ctx->Stencil.WriteMask[0] & 0xff) != 0xff) { - /* We have to use the 3D engine if we're clearing a partial mask - * of the stencil buffer, or if we're on a 965 which has a tiled - * depth/stencil buffer in a layout we can't blit to. - */ - tri_mask |= BUFFER_BIT_STENCIL; - } - else if (intel->has_separate_stencil && - stencilRegion->tiling == I915_TILING_NONE) { - /* The stencil buffer is actually W tiled, which the hardware - * cannot blit to. */ - tri_mask |= BUFFER_BIT_STENCIL; - } - else { - /* clearing all stencil bits, use blitting */ - blit_mask |= BUFFER_BIT_STENCIL; - } + if (fb->MaxNumLayers > 0) { + for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { + intel_hiz_exec(brw, mt, depth_irb->mt_level, + depth_irb->mt_layer + layer, + BLORP_HIZ_OP_DEPTH_CLEAR); } + } else { + intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, + BLORP_HIZ_OP_DEPTH_CLEAR); } - /* HW depth */ - if (mask & BUFFER_BIT_DEPTH) { - const struct intel_region *irb = intel_get_rb_region(fb, BUFFER_DEPTH); - - /* clear depth with whatever method is used for stencil (see above) */ - if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL) - tri_mask |= BUFFER_BIT_DEPTH; - else - blit_mask |= BUFFER_BIT_DEPTH; + if (brw->gen == 6) { + /* From the Sandy Bridge PRM, volume 2 part 1, page 314: + * + * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed + * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then + * followed by Depth FLUSH' + */ + brw_emit_mi_flush(brw); } - /* If we're doing a tri pass for depth/stencil, include a likely color - * buffer with it. + /* Now, the HiZ buffer contains data that needs to be resolved to the depth + * buffer. */ - if (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) { - int color_bit = ffs(mask & BUFFER_BITS_COLOR); - if (color_bit != 0) { - tri_mask |= blit_mask & (1 << (color_bit - 1)); - blit_mask &= ~(1 << (color_bit - 1)); + intel_renderbuffer_att_set_needs_depth_resolve(depth_att); + + return true; +} + +/** + * Called by ctx->Driver.Clear. + */ +static void +brw_clear(struct gl_context *ctx, GLbitfield mask) +{ + struct brw_context *brw = brw_context(ctx); + struct gl_framebuffer *fb = ctx->DrawBuffer; + bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb); + + if (!_mesa_check_conditional_render(ctx)) + return; + + if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) { + brw->front_buffer_dirty = true; + } + + intel_prepare_render(brw); + brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask); + + if (mask & BUFFER_BIT_DEPTH) { + if (brw_fast_clear_depth(ctx)) { + DBG("fast clear: depth\n"); + mask &= ~BUFFER_BIT_DEPTH; } } - /* Anything left, just use tris */ - tri_mask |= mask & ~blit_mask; + if (mask & BUFFER_BIT_STENCIL) { + struct intel_renderbuffer *stencil_irb = + intel_get_renderbuffer(fb, BUFFER_STENCIL); + struct intel_mipmap_tree *mt = stencil_irb->mt; + if (mt && mt->stencil_mt) + mt->stencil_mt->r8stencil_needs_update = true; + } - if (blit_mask) { - debug_mask("blit", blit_mask); - tri_mask |= intelClearWithBlit(ctx, blit_mask); + /* BLORP is currently only supported on Gen6+. */ + if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) { + const bool encode_srgb = ctx->Color.sRGBEnabled; + if (brw_blorp_clear_color(brw, fb, mask, partial_clear, encode_srgb)) { + debug_mask("blorp color", mask & BUFFER_BITS_COLOR); + mask &= ~BUFFER_BITS_COLOR; + } } + GLbitfield tri_mask = mask & (BUFFER_BITS_COLOR | + BUFFER_BIT_STENCIL | + BUFFER_BIT_DEPTH); + if (tri_mask) { debug_mask("tri", tri_mask); - _mesa_meta_glsl_Clear(&intel->ctx, tri_mask); + mask &= ~tri_mask; + + if (ctx->API == API_OPENGLES) { + _mesa_meta_Clear(&brw->ctx, tri_mask); + } else { + _mesa_meta_glsl_Clear(&brw->ctx, tri_mask); + } + } + + /* Any strange buffers get passed off to swrast */ + if (mask) { + debug_mask("swrast", mask); + _swrast_Clear(ctx, mask); } } @@ -196,5 +282,5 @@ intelClear(struct gl_context *ctx, GLbitfield mask) void intelInitClearFuncs(struct dd_function_table *functions) { - functions->Clear = intelClear; + functions->Clear = brw_clear; }