X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_clear.c;h=488732cb4f5ba2f3f10c14639e031c7cb9e39842;hb=8bed1adfc144d9ae8d55ccb9b277942da8a78064;hp=b2cea98dbd6d29cefa5c57728162a4b68fb9f3ca;hpb=98e048cf323c22688bfa465153e648005e555d12;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index b2cea98dbd6..488732cb4f5 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -1,5 +1,4 @@ -/************************************************************************** - * +/* * Copyright 2003 VMware, Inc. * Copyright 2009, 2012 Intel Corporation. * All Rights Reserved. @@ -8,7 +7,7 @@ * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to + * distribute, sublicense, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * @@ -18,15 +17,13 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ + */ -#include "main/glheader.h" #include "main/mtypes.h" #include "main/condrender.h" #include "swrast/swrast.h" @@ -36,7 +33,6 @@ #include "intel_blit.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" -#include "intel_regions.h" #include "brw_context.h" #include "brw_blorp.h" @@ -81,12 +77,12 @@ debug_mask(const char *name, GLbitfield mask) * Returns true if the scissor is a noop (cuts out nothing). */ static bool -noop_scissor(struct gl_context *ctx, struct gl_framebuffer *fb) +noop_scissor(struct gl_framebuffer *fb) { - return ctx->Scissor.ScissorArray[0].X <= 0 && - ctx->Scissor.ScissorArray[0].Y <= 0 && - ctx->Scissor.ScissorArray[0].Width >= fb->Width && - ctx->Scissor.ScissorArray[0].Height >= fb->Height; + return fb->_Xmin <= 0 && + fb->_Ymin <= 0 && + fb->_Xmax >= fb->Width && + fb->_Ymax >= fb->Height; } /** @@ -121,9 +117,10 @@ brw_fast_clear_depth(struct gl_context *ctx) * a previous clear had happened at a different clear value and resolve it * first. */ - if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(ctx, fb)) { - perf_debug("Failed to fast clear depth due to scissor being enabled. " - "Possible 5%% performance win if avoided.\n"); + if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) { + perf_debug("Failed to fast clear %dx%d depth because of scissors. " + "Possible 5%% performance win if avoided.\n", + mt->logical_width0, mt->logical_height0); return false; } @@ -155,8 +152,9 @@ brw_fast_clear_depth(struct gl_context *ctx) * width of the map (LOD0) is not multiple of 16, fast clear * optimization must be disabled. */ - if (brw->gen == 6 && (minify(mt->physical_width0, - depth_irb->mt_level) % 16) != 0) + if (brw->gen == 6 && + (minify(mt->physical_width0, + depth_irb->mt_level - mt->first_level) % 16) != 0) return false; /* FALLTHROUGH */ @@ -183,17 +181,17 @@ brw_fast_clear_depth(struct gl_context *ctx) * must be issued before the rectangle primitive used for the depth * buffer clear operation. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); if (fb->MaxNumLayers > 0) { - unsigned num_layers = depth_irb->mt->level[depth_irb->mt_level].depth; - for (unsigned layer = 0; layer < num_layers; layer++) { - intel_hiz_exec(brw, mt, depth_irb->mt_level, layer, - GEN6_HIZ_OP_DEPTH_CLEAR); + for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { + intel_hiz_exec(brw, mt, depth_irb->mt_level, + depth_irb->mt_layer + layer, + BLORP_HIZ_OP_DEPTH_CLEAR); } } else { intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, - GEN6_HIZ_OP_DEPTH_CLEAR); + BLORP_HIZ_OP_DEPTH_CLEAR); } if (brw->gen == 6) { @@ -203,7 +201,7 @@ brw_fast_clear_depth(struct gl_context *ctx) * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then * followed by Depth FLUSH' */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); } /* Now, the HiZ buffer contains data that needs to be resolved to the depth @@ -222,7 +220,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) { struct brw_context *brw = brw_context(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(ctx, fb); + bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb); if (!_mesa_check_conditional_render(ctx)) return; @@ -241,13 +239,20 @@ brw_clear(struct gl_context *ctx, GLbitfield mask) } } + if (mask & BUFFER_BIT_STENCIL) { + struct intel_renderbuffer *stencil_irb = + intel_get_renderbuffer(fb, BUFFER_STENCIL); + struct intel_mipmap_tree *mt = stencil_irb->mt; + if (mt && mt->stencil_mt) + mt->stencil_mt->r8stencil_needs_update = true; + } + /* BLORP is currently only supported on Gen6+. */ - if (brw->gen >= 6 && brw->gen < 8) { - if (mask & BUFFER_BITS_COLOR) { - if (brw_blorp_clear_color(brw, fb, partial_clear)) { - debug_mask("blorp color", mask & BUFFER_BITS_COLOR); - mask &= ~BUFFER_BITS_COLOR; - } + if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) { + const bool encode_srgb = ctx->Color.sRGBEnabled; + if (brw_blorp_clear_color(brw, fb, mask, partial_clear, encode_srgb)) { + debug_mask("blorp color", mask & BUFFER_BITS_COLOR); + mask &= ~BUFFER_BITS_COLOR; } }