X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_context.h;h=1a4efa3cb0cbd9385ba664e0c8e6274ef074b0f7;hb=9c9f45b82410646d2f7a8576d03de9916118bf07;hp=aa1284db3ce5bab9772c5f683c26ba97032faf85;hpb=365e5d78924ffe7d4ce47e3fbadc35c7105e5d34;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index aa1284db3ce..1a4efa3cb0c 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -34,14 +34,13 @@ #define BRWCONTEXT_INC #include -#include -#include "main/imports.h" #include "main/macros.h" -#include "main/mm.h" #include "main/mtypes.h" #include "brw_structs.h" +#include "brw_compiler.h" #include "intel_aub.h" -#include "program/prog_parameter.h" + +#include "isl/isl.h" #ifdef __cplusplus extern "C" { @@ -49,9 +48,7 @@ extern "C" { #define virtual virt #endif -#include #include -#include #ifdef __cplusplus #undef virtual } @@ -115,6 +112,12 @@ extern "C" { * enabled, it first passes them to a VS thread which is a good place * for the driver to implement any active vertex shader. * + * HS - Hull Shader (Tessellation Control Shader) + * + * TE - Tessellation Engine (Tessellation Primitive Generation) + * + * DS - Domain Shader (Tessellation Evaluation Shader) + * * GS - Geometry Shader. This corresponds to a new DX10 concept. If * enabled, incoming strips etc are passed to GS threads in individual * line/triangle/point units. The GS thread may perform arbitary @@ -160,11 +163,13 @@ enum brw_pipeline { enum brw_cache_id { BRW_CACHE_FS_PROG, - BRW_CACHE_BLORP_BLIT_PROG, + BRW_CACHE_BLORP_PROG, BRW_CACHE_SF_PROG, BRW_CACHE_VS_PROG, BRW_CACHE_FF_GS_PROG, BRW_CACHE_GS_PROG, + BRW_CACHE_TCS_PROG, + BRW_CACHE_TES_PROG, BRW_CACHE_CLIP_PROG, BRW_CACHE_CS_PROG, @@ -176,21 +181,24 @@ enum brw_state_id { BRW_STATE_URB_FENCE = BRW_MAX_CACHE, BRW_STATE_FRAGMENT_PROGRAM, BRW_STATE_GEOMETRY_PROGRAM, + BRW_STATE_TESS_PROGRAMS, BRW_STATE_VERTEX_PROGRAM, BRW_STATE_CURBE_OFFSETS, BRW_STATE_REDUCED_PRIMITIVE, + BRW_STATE_PATCH_PRIMITIVE, BRW_STATE_PRIMITIVE, BRW_STATE_CONTEXT, BRW_STATE_PSP, BRW_STATE_SURFACES, - BRW_STATE_VS_BINDING_TABLE, - BRW_STATE_GS_BINDING_TABLE, - BRW_STATE_PS_BINDING_TABLE, + BRW_STATE_BINDING_TABLE_POINTERS, BRW_STATE_INDICES, BRW_STATE_VERTICES, + BRW_STATE_DEFAULT_TESS_LEVELS, BRW_STATE_BATCH, BRW_STATE_INDEX_BUFFER, BRW_STATE_VS_CONSTBUF, + BRW_STATE_TCS_CONSTBUF, + BRW_STATE_TES_CONSTBUF, BRW_STATE_GS_CONSTBUF, BRW_STATE_PROGRAM_CACHE, BRW_STATE_STATE_BASE_ADDRESS, @@ -214,6 +222,9 @@ enum brw_state_id { BRW_STATE_VS_ATTRIB_WORKAROUNDS, BRW_STATE_COMPUTE_PROGRAM, BRW_STATE_CS_WORK_GROUPS, + BRW_STATE_URB_SIZE, + BRW_STATE_CC_STATE, + BRW_STATE_BLORP, BRW_NUM_STATE_BITS }; @@ -243,28 +254,31 @@ enum brw_state_id { * polluting the brw_state_cache code with special cases, we retain the dirty * bit for now. It should eventually be removed. */ -#define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG) +#define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG) #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG) #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG) #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG) #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG) +#define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG) +#define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG) #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG) #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG) #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE) #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM) #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM) +#define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS) #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM) #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS) #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE) +#define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE) #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE) #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT) #define BRW_NEW_PSP (1ull << BRW_STATE_PSP) #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES) -#define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE) -#define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE) -#define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE) +#define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS) #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES) #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES) +#define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS) /** * Used for any batch entry with a relocated pointer that will be used * by any 3D rendering. @@ -273,6 +287,8 @@ enum brw_state_id { /** \see brw.state.depth_region */ #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER) #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF) +#define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF) +#define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF) #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF) #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE) #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS) @@ -296,6 +312,9 @@ enum brw_state_id { #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS) #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM) #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS) +#define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE) +#define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE) +#define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP) struct brw_state_flags { /** State update flags signalled by mesa internals */ @@ -313,6 +332,20 @@ struct brw_vertex_program { }; +/** Subclass of Mesa tessellation control program */ +struct brw_tess_ctrl_program { + struct gl_tess_ctrl_program program; + unsigned id; /**< serial no. to identify tess ctrl progs, never re-used */ +}; + + +/** Subclass of Mesa tessellation evaluation program */ +struct brw_tess_eval_program { + struct gl_tess_eval_program program; + unsigned id; /**< serial no. to identify tess eval progs, never re-used */ +}; + + /** Subclass of Mesa geometry program */ struct brw_geometry_program { struct gl_geometry_program program; @@ -335,265 +368,11 @@ struct brw_compute_program { struct brw_shader { - struct gl_shader base; + struct gl_linked_shader base; bool compiled_once; }; -struct brw_stage_prog_data { - struct { - /** size of our binding table. */ - uint32_t size_bytes; - - /** @{ - * surface indices for the various groups of surfaces - */ - uint32_t pull_constants_start; - uint32_t texture_start; - uint32_t gather_texture_start; - uint32_t ubo_start; - uint32_t abo_start; - uint32_t image_start; - uint32_t shader_time_start; - /** @} */ - } binding_table; - - GLuint nr_params; /**< number of float params/constants */ - GLuint nr_pull_params; - unsigned nr_image_params; - - unsigned curb_read_length; - unsigned total_scratch; - - /** - * Register where the thread expects to find input data from the URB - * (typically uniforms, followed by vertex or fragment attributes). - */ - unsigned dispatch_grf_start_reg; - - bool use_alt_mode; /**< Use ALT floating point mode? Otherwise, IEEE. */ - - /* Pointers to tracked values (only valid once - * _mesa_load_state_parameters has been called at runtime). - */ - const gl_constant_value **param; - const gl_constant_value **pull_param; - - /** Image metadata passed to the shader as uniforms. */ - struct brw_image_param *image_param; -}; - -/* - * Image metadata structure as laid out in the shader parameter - * buffer. Entries have to be 16B-aligned for the vec4 back-end to be - * able to use them. That's okay because the padding and any unused - * entries [most of them except when we're doing untyped surface - * access] will be removed by the uniform packing pass. - */ -#define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0 -#define BRW_IMAGE_PARAM_OFFSET_OFFSET 4 -#define BRW_IMAGE_PARAM_SIZE_OFFSET 8 -#define BRW_IMAGE_PARAM_STRIDE_OFFSET 12 -#define BRW_IMAGE_PARAM_TILING_OFFSET 16 -#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20 -#define BRW_IMAGE_PARAM_SIZE 24 - -struct brw_image_param { - /** Surface binding table index. */ - uint32_t surface_idx; - - /** Offset applied to the X and Y surface coordinates. */ - uint32_t offset[2]; - - /** Surface X, Y and Z dimensions. */ - uint32_t size[3]; - - /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in - * pixels, vertical slice stride in pixels. - */ - uint32_t stride[4]; - - /** Log2 of the tiling modulus in the X, Y and Z dimension. */ - uint32_t tiling[3]; - - /** - * Right shift to apply for bit 6 address swizzling. Two different - * swizzles can be specified and will be applied one after the other. The - * resulting address will be: - * - * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^ - * (addr >> swizzling[1]))) - * - * Use \c 0xff if any of the swizzles is not required. - */ - uint32_t swizzling[2]; -}; - -/* Data about a particular attempt to compile a program. Note that - * there can be many of these, each in a different GL state - * corresponding to a different brw_wm_prog_key struct, with different - * compiled programs. - */ -struct brw_wm_prog_data { - struct brw_stage_prog_data base; - - GLuint num_varying_inputs; - - GLuint dispatch_grf_start_reg_16; - GLuint reg_blocks; - GLuint reg_blocks_16; - - struct { - /** @{ - * surface indices the WM-specific surfaces - */ - uint32_t render_target_start; - /** @} */ - } binding_table; - - uint8_t computed_depth_mode; - - bool early_fragment_tests; - bool no_8; - bool dual_src_blend; - bool uses_pos_offset; - bool uses_omask; - bool uses_kill; - bool pulls_bary; - uint32_t prog_offset_16; - - /** - * Mask of which interpolation modes are required by the fragment shader. - * Used in hardware setup on gen6+. - */ - uint32_t barycentric_interp_modes; - - /** - * Map from gl_varying_slot to the position within the FS setup data - * payload where the varying's attribute vertex deltas should be delivered. - * For varying slots that are not used by the FS, the value is -1. - */ - int urb_setup[VARYING_SLOT_MAX]; -}; - -struct brw_cs_prog_data { - struct brw_stage_prog_data base; - - GLuint dispatch_grf_start_reg_16; - unsigned local_size[3]; - unsigned simd_size; - bool uses_barrier; - bool uses_num_work_groups; - unsigned local_invocation_id_regs; - - struct { - /** @{ - * surface indices the CS-specific surfaces - */ - uint32_t work_groups_start; - /** @} */ - } binding_table; -}; - -/** - * Enum representing the i965-specific vertex results that don't correspond - * exactly to any element of gl_varying_slot. The values of this enum are - * assigned such that they don't conflict with gl_varying_slot. - */ -typedef enum -{ - BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX, - BRW_VARYING_SLOT_PAD, - /** - * Technically this is not a varying but just a placeholder that - * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord - * builtin variable to be compiled correctly. see compile_sf_prog() for - * more info. - */ - BRW_VARYING_SLOT_PNTC, - BRW_VARYING_SLOT_COUNT -} brw_varying_slot; - - -/** - * Data structure recording the relationship between the gl_varying_slot enum - * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a - * single octaword within the VUE (128 bits). - * - * Note that each BRW register contains 256 bits (2 octawords), so when - * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two - * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as - * in a vertex shader), each register corresponds to a single VUE slot, since - * it contains data for two separate vertices. - */ -struct brw_vue_map { - /** - * Bitfield representing all varying slots that are (a) stored in this VUE - * map, and (b) actually written by the shader. Does not include any of - * the additional varying slots defined in brw_varying_slot. - */ - GLbitfield64 slots_valid; - - /** - * Is this VUE map for a separate shader pipeline? - * - * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched - * without the linker having a chance to dead code eliminate unused varyings. - * - * This means that we have to use a fixed slot layout, based on the output's - * location field, rather than assigning slots in a compact contiguous block. - */ - bool separate; - - /** - * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are - * not stored in a slot (because they are not written, or because - * additional processing is applied before storing them in the VUE), the - * value is -1. - */ - signed char varying_to_slot[BRW_VARYING_SLOT_COUNT]; - - /** - * Map from VUE slot to gl_varying_slot value. For slots that do not - * directly correspond to a gl_varying_slot, the value comes from - * brw_varying_slot. - * - * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this - * simplifies code that uses the value stored in slot_to_varying to - * create a bit mask). - */ - signed char slot_to_varying[BRW_VARYING_SLOT_COUNT]; - - /** - * Total number of VUE slots in use - */ - int num_slots; -}; - -/** - * Convert a VUE slot number into a byte offset within the VUE. - */ -static inline GLuint brw_vue_slot_to_offset(GLuint slot) -{ - return 16*slot; -} - -/** - * Convert a vertex output (brw_varying_slot) into a byte offset within the - * VUE. - */ -static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map, - GLuint varying) -{ - return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]); -} - -void brw_compute_vue_map(const struct brw_device_info *devinfo, - struct brw_vue_map *vue_map, - GLbitfield64 slots_valid, - bool separate_shader); - - /** * Bitmask indicating which fragment shader inputs represent varyings (and * hence have to be delivered to the fragment shader by the SF/SBE stage). @@ -613,7 +392,7 @@ struct interpolation_mode_map { static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map) { for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++) - if (map->mode[i] == INTERP_QUALIFIER_FLAT) + if (map->mode[i] == INTERP_MODE_FLAT) return true; return false; @@ -622,7 +401,7 @@ static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map) static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map) { for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++) - if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE) + if (map->mode[i] == INTERP_MODE_NOPERSPECTIVE) return true; return false; @@ -670,39 +449,6 @@ struct brw_ff_gs_prog_data { unsigned svbi_postincrement_value; }; -enum shader_dispatch_mode { - DISPATCH_MODE_4X1_SINGLE = 0, - DISPATCH_MODE_4X2_DUAL_INSTANCE = 1, - DISPATCH_MODE_4X2_DUAL_OBJECT = 2, - DISPATCH_MODE_SIMD8 = 3, -}; - -struct brw_vue_prog_data { - struct brw_stage_prog_data base; - struct brw_vue_map vue_map; - - GLuint urb_read_length; - GLuint total_grf; - - /* Used for calculating urb partitions. In the VS, this is the size of the - * URB entry used for both input and output to the thread. In the GS, this - * is the size of the URB entry used for output. - */ - GLuint urb_entry_size; - - enum shader_dispatch_mode dispatch_mode; -}; - - -struct brw_vs_prog_data { - struct brw_vue_prog_data base; - - GLbitfield64 inputs_read; - - bool uses_vertexid; - bool uses_instanceid; -}; - /** Number of texture sampler units */ #define BRW_MAX_TEX_UNIT 32 @@ -710,14 +456,11 @@ struct brw_vs_prog_data { #define BRW_MAX_DRAW_BUFFERS 8 /** Max number of UBOs in a shader */ -#define BRW_MAX_UBO 12 +#define BRW_MAX_UBO 14 /** Max number of SSBOs in a shader */ #define BRW_MAX_SSBO 12 -/** Max number of combined UBOs and SSBOs in a shader */ -#define BRW_MAX_COMBINED_UBO_SSBO (BRW_MAX_UBO + BRW_MAX_SSBO) - /** Max number of atomic counter buffer objects in a shader */ #define BRW_MAX_ABO 16 @@ -763,71 +506,6 @@ struct brw_vs_prog_data { #define SURF_INDEX_GEN6_SOL_BINDING(t) (t) -struct brw_gs_prog_data -{ - struct brw_vue_prog_data base; - - /** - * Size of an output vertex, measured in HWORDS (32 bytes). - */ - unsigned output_vertex_size_hwords; - - unsigned output_topology; - - /** - * Size of the control data (cut bits or StreamID bits), in hwords (32 - * bytes). 0 if there is no control data. - */ - unsigned control_data_header_size_hwords; - - /** - * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID - * if the control data is StreamID bits, or - * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits). - * Ignored if control_data_header_size is 0. - */ - unsigned control_data_format; - - bool include_primitive_id; - - /** - * The number of vertices emitted, if constant - otherwise -1. - */ - int static_vertex_count; - - int invocations; - - /** - * Gen6 transform feedback enabled flag. - */ - bool gen6_xfb_enabled; - - /** - * Gen6: Provoking vertex convention for odd-numbered triangles - * in tristrips. - */ - GLuint pv_first:1; - - /** - * Gen6: Number of varyings that are output to transform feedback. - */ - GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */ - - /** - * Gen6: Map from the index of a transform feedback binding table entry to the - * gl_varying_slot that should be streamed out through that binding table - * entry. - */ - unsigned char transform_feedback_bindings[BRW_MAX_SOL_BINDINGS]; - - /** - * Gen6: Map from the index of a transform feedback binding table entry to the - * swizzles that should be used when streaming out data through that - * binding table entry. - */ - unsigned char transform_feedback_swizzles[BRW_MAX_SOL_BINDINGS]; -}; - /** * Stride in bytes between shader_time entries. * @@ -855,8 +533,6 @@ struct brw_cache_item { }; -typedef void (*cache_aux_free_func)(const void *aux); - struct brw_cache { struct brw_context *brw; @@ -866,9 +542,6 @@ struct brw_cache { uint32_t next_offset; bool bo_used_by_gpu; - - /** Optional functions for freeing other pointers attached to a prog_data. */ - cache_aux_free_func aux_free[BRW_MAX_CACHE]; }; @@ -886,6 +559,8 @@ struct brw_tracked_state { enum shader_time_shader_type { ST_NONE, ST_VS, + ST_TCS, + ST_TES, ST_GS, ST_FS8, ST_FS16, @@ -896,6 +571,7 @@ struct brw_vertex_buffer { /** Buffer object containing the uploaded vertex data */ drm_intel_bo *bo; uint32_t offset; + uint32_t size; /** Byte stride between elements in the uploaded array */ GLuint stride; GLuint step_rate; @@ -946,6 +622,7 @@ struct intel_batchbuffer { uint32_t state_batch_offset; enum brw_gpu_ring ring; bool needs_sol_reset; + bool state_base_address_emitted; struct { uint32_t *map_next; @@ -953,6 +630,8 @@ struct intel_batchbuffer { } saved; }; +#define MAX_GS_INPUT_VERTICES 6 + #define BRW_MAX_XFB_STREAMS 4 struct brw_transform_feedback_object { @@ -997,9 +676,28 @@ struct brw_stage_state /** * Optional scratch buffer used to store spilled register values and * variably-indexed GRF arrays. + * + * The contents of this buffer are short-lived so the same memory can be + * re-used at will for multiple shader programs (executed by the same fixed + * function). However reusing a scratch BO for which shader invocations + * are still in flight with a per-thread scratch slot size other than the + * original can cause threads with different scratch slot size and FFTID + * (which may be executed in parallel depending on the shader stage and + * hardware generation) to map to an overlapping region of the scratch + * space, which can potentially lead to mutual scratch space corruption. + * For that reason if you borrow this scratch buffer you should only be + * using the slot size given by the \c per_thread_scratch member below, + * unless you're taking additional measures to synchronize thread execution + * across slot size changes. */ drm_intel_bo *scratch_bo; + /** + * Scratch slot size allocated for each thread in the buffer object given + * by \c scratch_bo. + */ + uint32_t per_thread_scratch; + /** Offset in the program cache to the program */ uint32_t prog_offset; @@ -1035,6 +733,8 @@ enum brw_predicate_state { struct shader_times; +struct brw_l3_config; + /** * brw_context is derived from gl_context. */ @@ -1044,34 +744,10 @@ struct brw_context struct { - void (*update_texture_surface)(struct gl_context *ctx, - unsigned unit, - uint32_t *surf_offset, - bool for_gather); uint32_t (*update_renderbuffer_surface)(struct brw_context *brw, struct gl_renderbuffer *rb, bool layered, unsigned unit, uint32_t surf_index); - - void (*emit_texture_surface_state)(struct brw_context *brw, - struct intel_mipmap_tree *mt, - GLenum target, - unsigned min_layer, - unsigned max_layer, - unsigned min_level, - unsigned max_level, - unsigned format, - unsigned swizzle, - uint32_t *surf_offset, - bool rw, bool for_gather); - void (*emit_buffer_surface_state)(struct brw_context *brw, - uint32_t *out_offset, - drm_intel_bo *bo, - unsigned buffer_offset, - unsigned surface_format, - unsigned buffer_size, - unsigned pitch, - bool rw); void (*emit_null_surface_state)(struct brw_context *brw, unsigned width, unsigned height, @@ -1161,6 +837,7 @@ struct brw_context bool always_flush_cache; bool disable_throttling; bool precompile; + bool dual_color_blend_by_location; driOptionCache optionCache; /** @} */ @@ -1176,7 +853,7 @@ struct brw_context */ bool perf_debug; - uint32_t max_gtt_map_object_size; + uint64_t max_gtt_map_object_size; int gen; int gt; @@ -1200,6 +877,11 @@ struct brw_context bool use_rep_send; bool use_resource_streamer; + /** + * Whether LRI can be used to write register values from the batch buffer. + */ + bool can_do_pipelined_register_writes; + /** * Some versions of Gen hardware don't do centroid interpolation correctly * on unlit pixels, causing incorrect values for derivatives near triangle @@ -1209,6 +891,8 @@ struct brw_context */ bool needs_unlit_centroid_workaround; + struct isl_device isl_dev; + GLuint NewGLState; struct { struct brw_state_flags pipelines[BRW_NUM_PIPELINES]; @@ -1219,7 +903,7 @@ struct brw_context struct brw_cache cache; /** IDs for meta stencil blit shader programs. */ - unsigned meta_stencil_blit_programs[2]; + struct gl_shader_program *meta_stencil_blit_programs[2]; /* Whether a meta-operation is in progress. */ bool meta_in_progress; @@ -1231,8 +915,13 @@ struct brw_context uint32_t pma_stall_bits; struct { - /** The value of gl_BaseVertex for the current _mesa_prim. */ - int gl_basevertex; + struct { + /** The value of gl_BaseVertex for the current _mesa_prim. */ + int gl_basevertex; + + /** The value of gl_BaseInstance for the current _mesa_prim. */ + int gl_baseinstance; + } params; /** * Buffer and offset used for GL_ARB_shader_draw_parameters @@ -1240,6 +929,15 @@ struct brw_context */ drm_intel_bo *draw_params_bo; uint32_t draw_params_offset; + + /** + * The value of gl_DrawID for the current _mesa_prim. This always comes + * in from it's own vertex buffer since it's not part of the indirect + * draw parameters. + */ + int gl_drawid; + drm_intel_bo *draw_id_bo; + uint32_t draw_id_offset; } draw; struct { @@ -1264,6 +962,7 @@ struct brw_context /* Summary of size and varying of active arrays, so we can check * for changes to this state: */ + bool index_bounds_valid; unsigned int min_index, max_index; /* Offset from start of vertex buffer so we can avoid redefining @@ -1290,6 +989,7 @@ struct brw_context /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */ drm_intel_bo *bo; + uint32_t size; GLuint type; /* Offset to index buffer index to use in CMD_3D_PRIM so that we can @@ -1303,6 +1003,8 @@ struct brw_context */ const struct gl_vertex_program *vertex_program; const struct gl_geometry_program *geometry_program; + const struct gl_tess_ctrl_program *tess_ctrl_program; + const struct gl_tess_eval_program *tess_eval_program; const struct gl_fragment_program *fragment_program; const struct gl_compute_program *compute_program; @@ -1328,6 +1030,8 @@ struct brw_context struct { GLuint vsize; /* vertex size plus header in urb registers */ GLuint gsize; /* GS output size in urb registers */ + GLuint hsize; /* Tessellation control output size in urb registers */ + GLuint dsize; /* Tessellation evaluation output size in urb registers */ GLuint csize; /* constant buffer size in urb registers */ GLuint sfsize; /* setup data size in urb registers */ @@ -1340,22 +1044,37 @@ struct brw_context GLuint max_gs_entries; /* Maximum number of GS entries */ GLuint nr_vs_entries; + GLuint nr_hs_entries; + GLuint nr_ds_entries; GLuint nr_gs_entries; GLuint nr_clip_entries; GLuint nr_sf_entries; GLuint nr_cs_entries; GLuint vs_start; + GLuint hs_start; + GLuint ds_start; GLuint gs_start; GLuint clip_start; GLuint sf_start; GLuint cs_start; - GLuint size; /* Hardware URB size, in KB. */ + /** + * URB size in the current configuration. The units this is expressed + * in are somewhat inconsistent, see brw_device_info::urb::size. + * + * FINISHME: Represent the URB size consistently in KB on all platforms. + */ + GLuint size; /* True if the most recently sent _3DSTATE_URB message allocated * URB space for the GS. */ bool gs_present; + + /* True if the most recently sent _3DSTATE_URB message allocated + * URB space for the HS and DS. + */ + bool tess_present; } urb; @@ -1392,6 +1111,28 @@ struct brw_context struct brw_vs_prog_data *prog_data; } vs; + struct { + struct brw_stage_state base; + struct brw_tcs_prog_data *prog_data; + + /** + * True if the 3DSTATE_HS command most recently emitted to the 3D + * pipeline enabled the HS; false otherwise. + */ + bool enabled; + } tcs; + + struct { + struct brw_stage_state base; + struct brw_tes_prog_data *prog_data; + + /** + * True if the 3DSTATE_DS command most recently emitted to the 3D + * pipeline enabled the DS; false otherwise. + */ + bool enabled; + } tes; + struct { struct brw_stage_state base; struct brw_gs_prog_data *prog_data; @@ -1528,8 +1269,8 @@ struct brw_context } perfmon; int num_atoms[BRW_NUM_PIPELINES]; - const struct brw_tracked_state render_atoms[60]; - const struct brw_tracked_state compute_atoms[8]; + const struct brw_tracked_state render_atoms[76]; + const struct brw_tracked_state compute_atoms[11]; /* If (INTEL_DEBUG & DEBUG_BATCH) */ struct { @@ -1570,6 +1311,11 @@ struct brw_context uint32_t num_instances; int basevertex; + int baseinstance; + + struct { + const struct brw_l3_config *config; + } l3; struct { drm_intel_bo *bo; @@ -1601,7 +1347,8 @@ extern void intelInitClearFuncs(struct dd_function_table *functions); */ extern const char *const brw_vendor_string; -extern const char *brw_get_renderer_string(unsigned deviceID); +extern const char * +brw_get_renderer_string(const struct intel_screen *intelScreen); enum { DRI_CONF_BO_REUSE_DISABLED, @@ -1628,37 +1375,9 @@ GLboolean brwCreateContext(gl_api api, /*====================================================================== * brw_misc_state.c */ -GLuint brw_get_rb_for_slice(struct brw_context *brw, - struct intel_mipmap_tree *mt, - unsigned level, unsigned layer, bool flat); - -void brw_meta_updownsample(struct brw_context *brw, - struct intel_mipmap_tree *src, - struct intel_mipmap_tree *dst); - -void brw_meta_fbo_stencil_blit(struct brw_context *brw, - struct gl_framebuffer *read_fb, - struct gl_framebuffer *draw_fb, - GLfloat srcX0, GLfloat srcY0, - GLfloat srcX1, GLfloat srcY1, - GLfloat dstX0, GLfloat dstY0, - GLfloat dstX1, GLfloat dstY1); - -void brw_meta_stencil_updownsample(struct brw_context *brw, - struct intel_mipmap_tree *src, - struct intel_mipmap_tree *dst); - -bool brw_meta_fast_clear(struct brw_context *brw, - struct gl_framebuffer *fb, - GLbitfield mask, - bool partial_clear); - void brw_meta_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt); -void -brw_meta_fast_clear_free(struct brw_context *brw); - /*====================================================================== * brw_misc_state.c @@ -1682,13 +1401,16 @@ void brw_init_common_queryobj_functions(struct dd_function_table *functions); void gen4_init_queryobj_functions(struct dd_function_table *functions); void brw_emit_query_begin(struct brw_context *brw); void brw_emit_query_end(struct brw_context *brw); +void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q); +bool brw_is_query_pipelined(struct brw_query_object *query); /** gen6_queryobj.c */ void gen6_init_queryobj_functions(struct dd_function_table *functions); void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx); void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx); -void brw_store_register_mem64(struct brw_context *brw, - drm_intel_bo *bo, uint32_t reg, int idx); + +/** hsw_queryobj.c */ +void hsw_init_queryobj_functions(struct dd_function_table *functions); /** brw_conditional_render.c */ void brw_init_conditional_render_functions(struct dd_function_table *functions); @@ -1705,6 +1427,22 @@ void brw_load_register_mem64(struct brw_context *brw, drm_intel_bo *bo, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +void brw_store_register_mem32(struct brw_context *brw, + drm_intel_bo *bo, uint32_t reg, uint32_t offset); +void brw_store_register_mem64(struct brw_context *brw, + drm_intel_bo *bo, uint32_t reg, uint32_t offset); +void brw_load_register_imm32(struct brw_context *brw, + uint32_t reg, uint32_t imm); +void brw_load_register_imm64(struct brw_context *brw, + uint32_t reg, uint64_t imm); +void brw_load_register_reg(struct brw_context *brw, uint32_t src, + uint32_t dest); +void brw_load_register_reg64(struct brw_context *brw, uint32_t src, + uint32_t dest); +void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo, + uint32_t offset, uint32_t imm); +void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo, + uint32_t offset, uint64_t imm); /*====================================================================== * brw_state_dump.c @@ -1713,7 +1451,7 @@ void brw_debug_batch(struct brw_context *brw); void brw_annotate_aub(struct brw_context *brw); /*====================================================================== - * brw_tex.c + * intel_tex_validate.c */ void brw_validate_textures( struct brw_context *brw ); @@ -1721,16 +1459,30 @@ void brw_validate_textures( struct brw_context *brw ); /*====================================================================== * brw_program.c */ +static inline bool +key_debug(struct brw_context *brw, const char *name, int a, int b) +{ + if (a != b) { + perf_debug(" %s %d->%d\n", name, a, b); + return true; + } + return false; +} + void brwInitFragProgFuncs( struct dd_function_table *functions ); /* Per-thread scratch space is a power-of-two multiple of 1KB. */ static inline int brw_get_scratch_size(int size) { - return util_next_power_of_two(size | 1023); + return MAX2(1024, util_next_power_of_two(size)); } void brw_get_scratch_bo(struct brw_context *brw, drm_intel_bo **scratch_bo, int size); +void brw_alloc_stage_scratch(struct brw_context *brw, + struct brw_stage_state *stage_state, + unsigned per_thread_size, + unsigned thread_count); void brw_init_shader_time(struct brw_context *brw); int brw_get_shader_time_index(struct brw_context *brw, struct gl_shader_program *shader_prog, @@ -1793,14 +1545,12 @@ void brw_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, uint32_t size, - uint32_t *out_offset, - bool dword_pitch); + uint32_t *out_offset); void brw_create_buffer_surface(struct brw_context *brw, drm_intel_bo *bo, uint32_t offset, uint32_t size, - uint32_t *out_offset, - bool dword_pitch); + uint32_t *out_offset); void brw_update_buffer_texture_surface(struct gl_context *ctx, unsigned unit, uint32_t *surf_offset); @@ -1810,16 +1560,15 @@ brw_update_sol_surface(struct brw_context *brw, uint32_t *out_offset, unsigned num_vector_components, unsigned stride_dwords, unsigned offset_dwords); void brw_upload_ubo_surfaces(struct brw_context *brw, - struct gl_shader *shader, + struct gl_linked_shader *shader, struct brw_stage_state *stage_state, - struct brw_stage_prog_data *prog_data, - bool dword_pitch); + struct brw_stage_prog_data *prog_data); void brw_upload_abo_surfaces(struct brw_context *brw, - struct gl_shader_program *prog, + struct gl_linked_shader *shader, struct brw_stage_state *stage_state, struct brw_stage_prog_data *prog_data); void brw_upload_image_surfaces(struct brw_context *brw, - struct gl_shader *shader, + struct gl_linked_shader *shader, struct brw_stage_state *stage_state, struct brw_stage_prog_data *prog_data); @@ -1827,8 +1576,6 @@ void brw_upload_image_surfaces(struct brw_context *brw, bool brw_render_target_supported(struct brw_context *brw, struct gl_renderbuffer *rb); uint32_t brw_depth_format(struct brw_context *brw, mesa_format format); -mesa_format brw_lower_mesa_image_format(const struct brw_device_info *devinfo, - mesa_format format); /* brw_performance_monitor.c */ void brw_init_performance_monitors(struct brw_context *brw); @@ -1885,6 +1632,20 @@ void gen7_resume_transform_feedback(struct gl_context *ctx, struct gl_transform_feedback_object *obj); +/* hsw_sol.c */ +void +hsw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, + struct gl_transform_feedback_object *obj); +void +hsw_end_transform_feedback(struct gl_context *ctx, + struct gl_transform_feedback_object *obj); +void +hsw_pause_transform_feedback(struct gl_context *ctx, + struct gl_transform_feedback_object *obj); +void +hsw_resume_transform_feedback(struct gl_context *ctx, + struct gl_transform_feedback_object *obj); + /* brw_blorp_blit.cpp */ GLbitfield brw_blorp_framebuffer(struct brw_context *brw, @@ -1927,18 +1688,18 @@ void gen8_emit_3dstate_sample_pattern(struct brw_context *brw); /* gen7_urb.c */ void gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, + unsigned hs_size, unsigned ds_size, unsigned gs_size, unsigned fs_size); void -gen7_emit_urb_state(struct brw_context *brw, - unsigned nr_vs_entries, unsigned vs_size, - unsigned vs_start, unsigned nr_gs_entries, - unsigned gs_size, unsigned gs_start); - +gen7_upload_urb(struct brw_context *brw, unsigned vs_size, + bool gs_present, bool tess_present); /* brw_reset.c */ extern GLenum brw_get_graphics_reset_status(struct gl_context *ctx); +void +brw_check_for_reset(struct brw_context *brw); /* brw_compute.c */ extern void @@ -1966,6 +1727,18 @@ brw_vertex_program_const(const struct gl_vertex_program *p) return (const struct brw_vertex_program *) p; } +static inline struct brw_tess_ctrl_program * +brw_tess_ctrl_program(struct gl_tess_ctrl_program *p) +{ + return (struct brw_tess_ctrl_program *) p; +} + +static inline struct brw_tess_eval_program * +brw_tess_eval_program(struct gl_tess_eval_program *p) +{ + return (struct brw_tess_eval_program *) p; +} + static inline struct brw_geometry_program * brw_geometry_program(struct gl_geometry_program *p) { @@ -2022,16 +1795,9 @@ brw_program_reloc(struct brw_context *brw, uint32_t state_offset, bool brw_do_cubemap_normalize(struct exec_list *instructions); bool brw_lower_texture_gradients(struct brw_context *brw, struct exec_list *instructions); -bool brw_do_lower_unnormalized_offset(struct exec_list *instructions); -struct opcode_desc { - char *name; - int nsrc; - int ndst; -}; - -extern const struct opcode_desc opcode_descs[128]; extern const char * const conditional_modifier[16]; +extern const char *const pred_ctrl_align16[16]; void brw_emit_depthbuffer(struct brw_context *brw); @@ -2106,6 +1872,11 @@ void brw_emit_depth_stall_flushes(struct brw_context *brw); void gen7_emit_vs_workaround_flush(struct brw_context *brw); void gen7_emit_cs_stall_flush(struct brw_context *brw); +/* brw_queryformat.c */ +void brw_query_internal_format(struct gl_context *ctx, GLenum target, + GLenum internalFormat, GLenum pname, + GLint *params); + #ifdef __cplusplus } #endif