X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_context.h;h=36dc53cc9d5b3b6baf9fe97aad613e9c08180e88;hb=33b9c7a7f68bb5a4362751ba7daf1ba2b10ece95;hp=89dacf3874c0762b0de6db8efc5e54c99d750aee;hpb=1674a0bcbcbc5a7cb9b50f85a3d32d337995adf4;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 89dacf3874c..36dc53cc9d5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -36,7 +36,9 @@ #include #include "main/macros.h" #include "main/mtypes.h" +#include "main/errors.h" #include "brw_structs.h" +#include "brw_pipe_control.h" #include "compiler/brw_compiler.h" #include "isl/isl.h" @@ -44,9 +46,12 @@ #include -#include "common/gen_debug.h" +#include "dev/gen_debug.h" +#include "common/gen_decoder.h" #include "intel_screen.h" #include "intel_tex_obj.h" +#include "perf/gen_perf.h" +#include "perf/gen_perf_query.h" #ifdef __cplusplus extern "C" { @@ -165,6 +170,11 @@ enum brw_cache_id { BRW_MAX_CACHE }; +enum gen9_astc5x5_wa_tex_type { + GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0, + GEN9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1, +}; + enum brw_state_id { /* brw_cache_ids must come first - see brw_program_cache.c */ BRW_STATE_URB_FENCE = BRW_MAX_CACHE, @@ -195,7 +205,6 @@ enum brw_state_id { BRW_STATE_RASTERIZER_DISCARD, BRW_STATE_STATS_WM, BRW_STATE_UNIFORM_BUFFER, - BRW_STATE_ATOMIC_BUFFER, BRW_STATE_IMAGE_UNITS, BRW_STATE_META_IN_PROGRESS, BRW_STATE_PUSH_CONSTANT_ALLOCATION, @@ -215,7 +224,7 @@ enum brw_state_id { BRW_STATE_VIEWPORT_COUNT, BRW_STATE_CONSERVATIVE_RASTERIZATION, BRW_STATE_DRAW_CALL, - BRW_STATE_FAST_CLEAR_COLOR, + BRW_STATE_AUX, BRW_NUM_STATE_BITS }; @@ -288,7 +297,6 @@ enum brw_state_id { #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD) #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM) #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER) -#define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER) #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS) #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS) #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION) @@ -307,7 +315,7 @@ enum brw_state_id { #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP) #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION) #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL) -#define BRW_NEW_FAST_CLEAR_COLOR (1ull << BRW_STATE_FAST_CLEAR_COLOR) +#define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX) struct brw_state_flags { /** State update flags signalled by mesa internals */ @@ -377,6 +385,35 @@ struct brw_cache { uint32_t next_offset; }; +#define perf_debug(...) do { \ + static GLuint msg_id = 0; \ + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \ + dbg_printf(__VA_ARGS__); \ + if (brw->perf_debug) \ + _mesa_gl_debugf(&brw->ctx, &msg_id, \ + MESA_DEBUG_SOURCE_API, \ + MESA_DEBUG_TYPE_PERFORMANCE, \ + MESA_DEBUG_SEVERITY_MEDIUM, \ + __VA_ARGS__); \ +} while(0) + +#define WARN_ONCE(cond, fmt...) do { \ + if (unlikely(cond)) { \ + static bool _warned = false; \ + static GLuint msg_id = 0; \ + if (!_warned) { \ + fprintf(stderr, "WARNING: "); \ + fprintf(stderr, fmt); \ + _warned = true; \ + \ + _mesa_gl_debugf(ctx, &msg_id, \ + MESA_DEBUG_SOURCE_API, \ + MESA_DEBUG_TYPE_OTHER, \ + MESA_DEBUG_SEVERITY_HIGH, fmt); \ + } \ + } \ +} while (0) + /* Considered adding a member to this struct to document which flags * an update might raise so that ordering of the state atoms can be * checked or derived at runtime. Dropped the idea in favor of having @@ -396,6 +433,7 @@ enum shader_time_shader_type { ST_GS, ST_FS8, ST_FS16, + ST_FS32, ST_CS, }; @@ -409,7 +447,7 @@ struct brw_vertex_buffer { GLuint step_rate; }; struct brw_vertex_element { - const struct gl_vertex_array *glarray; + const struct gl_vertex_format *glformat; int buffer; bool is_dual_slot; @@ -430,39 +468,44 @@ struct brw_query_object { bool flushed; }; -enum brw_gpu_ring { - UNKNOWN_RING, - RENDER_RING, - BLT_RING, -}; - struct brw_reloc_list { struct drm_i915_gem_relocation_entry *relocs; int reloc_count; int reloc_array_size; }; +struct brw_growing_bo { + struct brw_bo *bo; + uint32_t *map; + struct brw_bo *partial_bo; + uint32_t *partial_bo_map; + unsigned partial_bytes; + enum brw_memory_zone memzone; +}; + struct intel_batchbuffer { /** Current batchbuffer being queued up. */ - struct brw_bo *bo; - /** Last BO submitted to the hardware. Used for glFinish(). */ + struct brw_growing_bo batch; + /** Current statebuffer being queued up. */ + struct brw_growing_bo state; + + /** Last batchbuffer submitted to the hardware. Used for glFinish(). */ struct brw_bo *last_bo; #ifdef DEBUG uint16_t emit, total; #endif - uint16_t reserved_space; uint32_t *map_next; - uint32_t *map; - uint32_t *cpu_map; + uint32_t state_used; - uint32_t state_batch_offset; - enum brw_gpu_ring ring; + bool use_shadow_copy; bool use_batch_first; bool needs_sol_reset; bool state_base_address_emitted; + bool no_wrap; struct brw_reloc_list batch_relocs; + struct brw_reloc_list state_relocs; unsigned int valid_reloc_flags; /** The validation list */ @@ -472,20 +515,53 @@ struct intel_batchbuffer { int exec_array_size; /** The amount of aperture space (in bytes) used by all exec_bos */ - int aperture_space; + uint64_t aperture_space; struct { uint32_t *map_next; int batch_reloc_count; + int state_reloc_count; int exec_count; } saved; /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */ - struct hash_table *state_batch_sizes; + struct hash_table_u64 *state_batch_sizes; + + struct gen_batch_decode_ctx decoder; }; #define BRW_MAX_XFB_STREAMS 4 +struct brw_transform_feedback_counter { + /** + * Index of the first entry of this counter within the primitive count BO. + * An entry is considered to be an N-tuple of 64bit values, where N is the + * number of vertex streams supported by the platform. + */ + unsigned bo_start; + + /** + * Index one past the last entry of this counter within the primitive + * count BO. + */ + unsigned bo_end; + + /** + * Primitive count values accumulated while this counter was active, + * excluding any entries buffered between \c bo_start and \c bo_end, which + * haven't been accounted for yet. + */ + uint64_t accum[BRW_MAX_XFB_STREAMS]; +}; + +static inline void +brw_reset_transform_feedback_counter( + struct brw_transform_feedback_counter *counter) +{ + counter->bo_start = counter->bo_end; + memset(&counter->accum, 0, sizeof(counter->accum)); +} + struct brw_transform_feedback_object { struct gl_transform_feedback_object base; @@ -504,14 +580,18 @@ struct brw_transform_feedback_object { */ unsigned max_index; + struct brw_bo *prim_count_bo; + /** * Count of primitives generated during this transform feedback operation. - * @{ */ - uint64_t prims_generated[BRW_MAX_XFB_STREAMS]; - struct brw_bo *prim_count_bo; - unsigned prim_count_buffer_index; /**< in number of uint64_t units */ - /** @} */ + struct brw_transform_feedback_counter counter; + + /** + * Count of primitives generated during the previous transform feedback + * operation. Used to implement DrawTransformFeedback(). + */ + struct brw_transform_feedback_counter previous_counter; /** * Number of vertices written between last Begin/EndTransformFeedback(). @@ -574,6 +654,8 @@ struct brw_stage_state uint32_t sampler_count; uint32_t sampler_offset; + struct brw_image_param image_param[BRW_MAX_IMAGES]; + /** Need to re-emit 3DSTATE_CONSTANT_XS? */ bool push_constants_dirty; }; @@ -600,31 +682,14 @@ enum brw_predicate_state { struct shader_times; struct gen_l3_config; +struct gen_perf; -enum brw_query_kind { - OA_COUNTERS, - PIPELINE_STATS -}; - -struct brw_perf_query_info -{ - enum brw_query_kind kind; - const char *name; - const char *guid; - struct brw_perf_query_counter *counters; - int n_counters; - size_t data_size; - - /* OA specific */ - uint64_t oa_metrics_set_id; - int oa_format; - - /* For indexing into the accumulator[] ... */ - int gpu_time_offset; - int gpu_clock_offset; - int a_offset; - int b_offset; - int c_offset; +struct brw_uploader { + struct brw_bufmgr *bufmgr; + struct brw_bo *bo; + void *map; + uint32_t next_offset; + unsigned default_size; }; /** @@ -636,20 +701,6 @@ struct brw_context struct { - /** - * Send the appropriate state packets to configure depth, stencil, and - * HiZ buffers (i965+ only) - */ - void (*emit_depth_stencil_hiz)(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, - uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); - /** * Emit an MI_REPORT_PERF_COUNT command packet. * @@ -661,6 +712,11 @@ struct brw_context struct brw_bo *bo, uint32_t offset_in_bytes, uint32_t report_id); + + void (*emit_compute_walker)(struct brw_context *brw); + void (*emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, + struct brw_bo *bo, uint32_t offset, + uint64_t imm); } vtbl; struct brw_bufmgr *bufmgr; @@ -676,7 +732,14 @@ struct brw_context * and would need flushing before being used from another cache domain that * isn't coherent with it (i.e. the sampler). */ - struct set *render_cache; + struct hash_table *render_cache; + + /** + * Set of struct brw_bo * that have been used as a depth buffer within this + * batchbuffer and would need flushing before being used from another cache + * domain that isn't coherent with it (i.e. the sampler). + */ + struct set *depth_cache; /** * Number of resets observed in the system at context creation. @@ -687,13 +750,8 @@ struct brw_context uint32_t reset_count; struct intel_batchbuffer batch; - bool no_batch_wrap; - struct { - struct brw_bo *bo; - void *map; - uint32_t next_offset; - } upload; + struct brw_uploader upload; /** * Set if rendering has occurred to the drawable's front buffer. @@ -703,6 +761,18 @@ struct brw_context */ bool front_buffer_dirty; + /** + * True if the __DRIdrawable's current __DRIimageBufferMask is + * __DRI_IMAGE_BUFFER_SHARED. + */ + bool is_shared_buffer_bound; + + /** + * True if a shared buffer is bound and it has received any rendering since + * the previous __DRImutableRenderBufferLoaderExtension::displaySharedBuffer(). + */ + bool is_shared_buffer_dirty; + /** Framerate throttling: @{ */ struct brw_bo *throttle_batch[2]; @@ -726,7 +796,6 @@ struct brw_context * drirc options: * @{ */ - bool no_rast; bool always_flush_batch; bool always_flush_cache; bool disable_throttling; @@ -738,6 +807,8 @@ struct brw_context GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */ + bool object_preemption; /**< Object level preemption enabled. */ + GLenum reduced_primitive; /** @@ -773,9 +844,6 @@ struct brw_context struct brw_cache cache; - /** IDs for meta stencil blit shader programs. */ - struct gl_shader_program *meta_stencil_blit_programs[2]; - /* Whether a meta-operation is in progress. */ bool meta_in_progress; @@ -785,30 +853,67 @@ struct brw_context /* The last PMA stall bits programmed. */ uint32_t pma_stall_bits; + /* Whether INTEL_black_render is active. */ + bool frontend_noop; + struct { struct { - /** The value of gl_BaseVertex for the current _mesa_prim. */ - int gl_basevertex; + /** + * Either the value of gl_BaseVertex for indexed draw calls or the + * value of the argument for non-indexed draw calls for the + * current _mesa_prim. + */ + int firstvertex; /** The value of gl_BaseInstance for the current _mesa_prim. */ int gl_baseinstance; } params; /** - * Buffer and offset used for GL_ARB_shader_draw_parameters - * (for now, only gl_BaseVertex). + * Buffer and offset used for GL_ARB_shader_draw_parameters which will + * point to the indirect buffer for indirect draw calls. */ struct brw_bo *draw_params_bo; uint32_t draw_params_offset; + struct { + /** + * The value of gl_DrawID for the current _mesa_prim. This always comes + * in from it's own vertex buffer since it's not part of the indirect + * draw parameters. + */ + int gl_drawid; + + /** + * Stores if the current _mesa_prim is an indexed or non-indexed draw + * (~0/0). Useful to calculate gl_BaseVertex as an AND of firstvertex + * and is_indexed_draw. + */ + int is_indexed_draw; + } derived_params; + /** - * The value of gl_DrawID for the current _mesa_prim. This always comes - * in from it's own vertex buffer since it's not part of the indirect - * draw parameters. + * Buffer and offset used for GL_ARB_shader_draw_parameters which contains + * parameters that are not present in the indirect buffer. They will go in + * their own vertex element. */ - int gl_drawid; - struct brw_bo *draw_id_bo; - uint32_t draw_id_offset; + struct brw_bo *derived_draw_params_bo; + uint32_t derived_draw_params_offset; + + /** + * Pointer to the the buffer storing the indirect draw parameters. It + * currently only stores the number of requested draw calls but more + * parameters could potentially be added. + */ + struct brw_bo *draw_params_count_bo; + uint32_t draw_params_count_offset; + + /** + * Draw indirect buffer. + */ + unsigned draw_indirect_stride; + GLsizeiptr draw_indirect_offset; + struct gl_buffer_object *draw_indirect_data; } draw; struct { @@ -848,6 +953,9 @@ struct brw_context * These bitfields indicate which workarounds are needed. */ uint8_t attrib_wa_flags[VERT_ATTRIB_MAX]; + + /* High bits of the last seen vertex buffer address (for workarounds). */ + uint16_t last_bo_high_bits[33]; } vb; struct { @@ -868,22 +976,23 @@ struct brw_context * referencing the same index buffer. */ unsigned int start_vertex_offset; + + /* High bits of the last seen index buffer address (for workarounds). */ + uint16_t last_bo_high_bits; + + /* Used to understand is GPU state of primitive restart is up to date */ + bool enable_cut_index; } ib; /* Active vertex program: */ - const struct gl_program *vertex_program; - const struct gl_program *geometry_program; - const struct gl_program *tess_ctrl_program; - const struct gl_program *tess_eval_program; - const struct gl_program *fragment_program; - const struct gl_program *compute_program; + struct gl_program *programs[MESA_SHADER_STAGES]; /** * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so * that we don't have to reemit that state every time we change FBOs. */ - int num_samples; + unsigned int num_samples; /* BRW_NEW_URB_ALLOCATIONS: */ @@ -1033,14 +1142,11 @@ struct brw_context struct { struct brw_stage_state base; - GLuint render_surf; - /** * Buffer object used in place of multisampled null render targets on * Gen6. See brw_emit_null_surface_state(). */ struct brw_bo *multisampled_null_render_target_bo; - uint32_t fast_clear_op; float offset_clamp; } wm; @@ -1066,87 +1172,7 @@ struct brw_context bool supported; } predicate; - struct { - /* Variables referenced in the XML meta data for OA performance - * counters, e.g in the normalization equations. - * - * All uint64_t for consistent operand types in generated code - */ - struct { - uint64_t timestamp_frequency; /** $GpuTimestampFrequency */ - uint64_t n_eus; /** $EuCoresTotalCount */ - uint64_t n_eu_slices; /** $EuSlicesTotalCount */ - uint64_t n_eu_sub_slices; /** $EuSubslicesTotalCount */ - uint64_t eu_threads_count; /** $EuThreadsCount */ - uint64_t slice_mask; /** $SliceMask */ - uint64_t subslice_mask; /** $SubsliceMask */ - uint64_t gt_min_freq; /** $GpuMinFrequency */ - uint64_t gt_max_freq; /** $GpuMaxFrequency */ - } sys_vars; - - /* OA metric sets, indexed by GUID, as know by Mesa at build time, - * to cross-reference with the GUIDs of configs advertised by the - * kernel at runtime - */ - struct hash_table *oa_metrics_table; - - struct brw_perf_query_info *queries; - int n_queries; - - /* The i915 perf stream we open to setup + enable the OA counters */ - int oa_stream_fd; - - /* An i915 perf stream fd gives exclusive access to the OA unit that will - * report counter snapshots for a specific counter set/profile in a - * specific layout/format so we can only start OA queries that are - * compatible with the currently open fd... - */ - int current_oa_metrics_set_id; - int current_oa_format; - - /* List of buffers containing OA reports */ - struct exec_list sample_buffers; - - /* Cached list of empty sample buffers */ - struct exec_list free_sample_buffers; - - int n_active_oa_queries; - int n_active_pipeline_stats_queries; - - /* The number of queries depending on running OA counters which - * extends beyond brw_end_perf_query() since we need to wait until - * the last MI_RPC command has parsed by the GPU. - * - * Accurate accounting is important here as emitting an - * MI_REPORT_PERF_COUNT command while the OA unit is disabled will - * effectively hang the gpu. - */ - int n_oa_users; - - /* To help catch an spurious problem with the hardware or perf - * forwarding samples, we emit each MI_REPORT_PERF_COUNT command - * with a unique ID that we can explicitly check for... - */ - int next_query_start_report_id; - - /** - * An array of queries whose results haven't yet been assembled - * based on the data in buffer objects. - * - * These may be active, or have already ended. However, the - * results have not been requested. - */ - struct brw_perf_query_object **unaccumulated; - int unaccumulated_elements; - int unaccumulated_array_size; - - /* The total number of query objects so we can relinquish - * our exclusive access to perf if the application deletes - * all of its objects. (NB: We only disable perf while - * there are no active queries) - */ - int n_query_instances; - } perfquery; + struct gen_perf_context *perf_ctx; int num_atoms[BRW_NUM_PIPELINES]; const struct brw_tracked_state render_atoms[76]; @@ -1195,15 +1221,16 @@ struct brw_context struct brw_fast_clear_state *fast_clear_state; - /* Array of flags telling if auxiliary buffer is disabled for corresponding - * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of - * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is - * disabled. - * This is needed in case the same underlying buffer is also configured - * to be sampled but with a format that the sampling engine can't treat - * compressed or fast cleared. + /* Array of aux usages to use for drawing. Aux usage for render targets is + * a bit more complex than simply calling a single function so we need some + * way of passing it form brw_draw.c to surface state setup. */ - bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS]; + enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS]; + + enum gen9_astc5x5_wa_tex_type gen9_astc5x5_wa_tex_mask; + + /** Last rendering scale argument provided to brw_emit_hashing_mode(). */ + unsigned current_hash_scale; __DRIcontext *driContext; struct intel_screen *screen; @@ -1229,33 +1256,30 @@ void intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); void intel_prepare_render(struct brw_context *brw); -void brw_predraw_resolve_inputs(struct brw_context *brw); +void gen9_apply_single_tex_astc5x5_wa(struct brw_context *brw, + mesa_format format, + enum isl_aux_usage aux_usage); + +void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering, + bool *draw_aux_buffer_disabled); void intel_resolve_for_dri2_flush(struct brw_context *brw, __DRIdrawable *drawable); GLboolean brwCreateContext(gl_api api, - const struct gl_config *mesaVis, - __DRIcontext *driContextPriv, - unsigned major_version, - unsigned minor_version, - uint32_t flags, - bool notify_reset, - unsigned *error, - void *sharedContextPrivate); - -/*====================================================================== - * brw_misc_state.c - */ -void -brw_meta_resolve_color(struct brw_context *brw, - struct intel_mipmap_tree *mt); + const struct gl_config *mesaVis, + __DRIcontext *driContextPriv, + const struct __DriverContextConfig *ctx_config, + unsigned *error, + void *sharedContextPrivate); /*====================================================================== * brw_misc_state.c */ void brw_workaround_depthstencil_alignment(struct brw_context *brw, GLbitfield clear_mask); +void brw_emit_hashing_mode(struct brw_context *brw, unsigned width, + unsigned height, unsigned scale); /* brw_object_purgeable.c */ void brw_init_object_purgeable_functions(struct dd_function_table *functions); @@ -1269,7 +1293,6 @@ void brw_emit_query_begin(struct brw_context *brw); void brw_emit_query_end(struct brw_context *brw); void brw_query_counter(struct gl_context *ctx, struct gl_query_object *q); bool brw_is_query_pipelined(struct brw_query_object *query); -uint64_t brw_timebase_scale(struct brw_context *brw, uint64_t gpu_timestamp); uint64_t brw_raw_timestamp_delta(struct brw_context *brw, uint64_t time0, uint64_t time1); @@ -1305,10 +1328,10 @@ void brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm); void brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm); -void brw_load_register_reg(struct brw_context *brw, uint32_t src, - uint32_t dest); -void brw_load_register_reg64(struct brw_context *brw, uint32_t src, - uint32_t dest); +void brw_load_register_reg(struct brw_context *brw, uint32_t dst, + uint32_t src); +void brw_load_register_reg64(struct brw_context *brw, uint32_t dst, + uint32_t src); void brw_store_data_imm32(struct brw_context *brw, struct brw_bo *bo, uint32_t offset, uint32_t imm); void brw_store_data_imm64(struct brw_context *brw, struct brw_bo *bo, @@ -1323,24 +1346,13 @@ void brw_validate_textures( struct brw_context *brw ); /*====================================================================== * brw_program.c */ -static inline bool -key_debug(struct brw_context *brw, const char *name, int a, int b) -{ - if (a != b) { - perf_debug(" %s %d->%d\n", name, a, b); - return true; - } - return false; -} - void brwInitFragProgFuncs( struct dd_function_table *functions ); void brw_get_scratch_bo(struct brw_context *brw, struct brw_bo **scratch_bo, int size); void brw_alloc_stage_scratch(struct brw_context *brw, struct brw_stage_state *stage_state, - unsigned per_thread_size, - unsigned thread_count); + unsigned per_thread_size); void brw_init_shader_time(struct brw_context *brw); int brw_get_shader_time_index(struct brw_context *brw, struct gl_program *prog, @@ -1364,7 +1376,7 @@ gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx); /* brw_draw_upload.c */ unsigned brw_get_vertex_surface_type(struct brw_context *brw, - const struct gl_vertex_array *glarray); + const struct gl_vertex_format *glformat); static inline unsigned brw_get_index_type(unsigned index_size) @@ -1378,16 +1390,6 @@ brw_get_index_type(unsigned index_size) void brw_prepare_vertices(struct brw_context *brw); /* brw_wm_surface_state.c */ -void brw_create_constant_surface(struct brw_context *brw, - struct brw_bo *bo, - uint32_t offset, - uint32_t size, - uint32_t *out_offset); -void brw_create_buffer_surface(struct brw_context *brw, - struct brw_bo *bo, - uint32_t offset, - uint32_t size, - uint32_t *out_offset); void brw_update_buffer_texture_surface(struct gl_context *ctx, unsigned unit, uint32_t *surf_offset); @@ -1399,10 +1401,6 @@ brw_update_sol_surface(struct brw_context *brw, void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, struct brw_stage_state *stage_state, struct brw_stage_prog_data *prog_data); -void brw_upload_abo_surfaces(struct brw_context *brw, - const struct gl_program *prog, - struct brw_stage_state *stage_state, - struct brw_stage_prog_data *prog_data); void brw_upload_image_surfaces(struct brw_context *brw, const struct gl_program *prog, struct brw_stage_state *stage_state, @@ -1425,7 +1423,6 @@ extern void intelInitExtensions(struct gl_context *ctx); extern int intel_translate_shadow_compare_func(GLenum func); extern int intel_translate_compare_func(GLenum func); extern int intel_translate_stencil_op(GLenum op); -extern int intel_translate_logic_op(GLenum opcode); /* brw_sync.c */ void brw_init_syncobj_functions(struct dd_function_table *functions); @@ -1451,9 +1448,6 @@ brw_resume_transform_feedback(struct gl_context *ctx, void brw_save_primitives_written_counters(struct brw_context *brw, struct brw_transform_feedback_object *obj); -void -brw_compute_xfb_vertices_written(struct brw_context *brw, - struct brw_transform_feedback_object *obj); GLsizei brw_get_transform_feedback_vertex_count(struct gl_context *ctx, struct gl_transform_feedback_object *obj, @@ -1505,6 +1499,10 @@ brw_blorp_copytexsubimage(struct brw_context *brw, int dstX0, int dstY0, int width, int height); +/* brw_generate_mipmap.c */ +void brw_generate_mipmap(struct gl_context *ctx, GLenum target, + struct gl_texture_object *tex_obj); + void gen6_get_sample_position(struct gl_context *ctx, struct gl_framebuffer *fb, @@ -1514,9 +1512,11 @@ void gen6_set_sample_maps(struct gl_context *ctx); /* gen8_multisample_state.c */ -void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp); void gen8_emit_3dstate_sample_pattern(struct brw_context *brw); +/* gen7_l3_state.c */ +void brw_emit_l3_state(struct brw_context *brw); + /* gen7_urb.c */ void gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, @@ -1540,6 +1540,25 @@ brw_check_for_reset(struct brw_context *brw); extern void brw_init_compute_functions(struct dd_function_table *functions); +/* brw_program_binary.c */ +extern void +brw_program_binary_init(unsigned device_id); +extern void +brw_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1); +void brw_serialize_program_binary(struct gl_context *ctx, + struct gl_shader_program *sh_prog, + struct gl_program *prog); +extern void +brw_deserialize_program_binary(struct gl_context *ctx, + struct gl_shader_program *shProg, + struct gl_program *prog); +void +brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog); +void +brw_program_deserialize_driver_blob(struct gl_context *ctx, + struct gl_program *prog, + gl_shader_stage stage); + /*====================================================================== * Inline conversion functions. These are better-typed than the * macros used previously: @@ -1585,45 +1604,6 @@ brw_depth_writes_enabled(const struct brw_context *brw) void brw_emit_depthbuffer(struct brw_context *brw); -void -brw_emit_depth_stencil_hiz(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); - -void -gen6_emit_depth_stencil_hiz(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); - -void -gen7_emit_depth_stencil_hiz(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); -void -gen8_emit_depth_stencil_hiz(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); - uint32_t get_hw_prim_for_gl_prim(int mode); void @@ -1636,22 +1616,6 @@ bool gen9_use_linear_1d_layout(const struct brw_context *brw, const struct intel_mipmap_tree *mt); -/* brw_pipe_control.c */ -int brw_init_pipe_control(struct brw_context *brw, - const struct gen_device_info *info); -void brw_fini_pipe_control(struct brw_context *brw); - -void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); -void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, - struct brw_bo *bo, uint32_t offset, - uint64_t imm); -void brw_emit_end_of_pipe_sync(struct brw_context *brw, uint32_t flags); -void brw_emit_mi_flush(struct brw_context *brw); -void brw_emit_post_sync_nonzero_flush(struct brw_context *brw); -void brw_emit_depth_stall_flushes(struct brw_context *brw); -void gen7_emit_vs_workaround_flush(struct brw_context *brw); -void gen7_emit_cs_stall_flush(struct brw_context *brw); - /* brw_queryformat.c */ void brw_query_internal_format(struct gl_context *ctx, GLenum target, GLenum internalFormat, GLenum pname,