X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_draw.c;h=ef0f2737ca11aba0da07aa794168d199c87b7dad;hb=cf40ebacb113a370c1b2445e881f8dc440a7d8f3;hp=15cc6e37bd06806b6bea27bf3c1986344d1705eb;hpb=02f9757ab5942ad6ad3b14f50459240f3dc2d897;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 15cc6e37bd0..ef0f2737ca1 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -1,8 +1,8 @@ /************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * + * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,19 +10,19 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ #include @@ -48,6 +48,7 @@ #include "brw_state.h" #include "intel_batchbuffer.h" +#include "intel_buffers.h" #include "intel_fbo.h" #include "intel_mipmap_tree.h" #include "intel_regions.h" @@ -73,7 +74,7 @@ const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1] = { }; -static const GLenum reduced_prim[GL_POLYGON+1] = { +static const GLenum reduced_prim[GL_POLYGON+1] = { GL_POINTS, GL_LINES, GL_LINES, @@ -156,7 +157,7 @@ static GLuint trim(GLenum prim, GLuint length) return length > 3 ? (length - length % 2) : 0; else if (prim == GL_QUADS) return length - length % 4; - else + else return length; } @@ -217,42 +218,33 @@ static void brw_emit_prim(struct brw_context *brw, indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE; - BEGIN_BATCH(15); - - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_VERTEX_COUNT); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 0); - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 4); - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_START_VERTEX); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 8); + brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 0); + brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 4); + brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 8); if (prim->indexed) { - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 12); - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_START_INSTANCE); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 16); - } - else { - OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2)); - OUT_BATCH(GEN7_3DPRIM_START_INSTANCE); - OUT_RELOC(bo, I915_GEM_DOMAIN_VERTEX, 0, - prim->indirect_offset + 12); + brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 12); + brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 16); + } else { + brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo, + I915_GEM_DOMAIN_VERTEX, 0, + prim->indirect_offset + 12); + BEGIN_BATCH(3); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX); OUT_BATCH(0); + ADVANCE_BATCH(); } - - ADVANCE_BATCH(); } else { indirect_flag = 0; @@ -306,8 +298,8 @@ static void brw_merge_inputs( struct brw_context *brw, /* * \brief Resolve buffers before drawing. * - * Resolve the depth buffer's HiZ buffer and resolve the depth buffer of each - * enabled depth texture. + * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each + * enabled depth texture, and flush the render cache for any dirty textures. * * (In the future, this will also perform MSAA resolves). */ @@ -323,10 +315,8 @@ brw_predraw_resolve_buffers(struct brw_context *brw) if (depth_irb) intel_renderbuffer_resolve_hiz(brw, depth_irb); - /* Resolve depth buffer of each enabled depth texture, and color buffer of - * each fast-clear-enabled color texture. - */ - for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) { + /* Resolve depth buffer and render cache of each enabled texture. */ + for (int i = 0; i < ctx->Const.MaxCombinedTextureImageUnits; i++) { if (!ctx->Texture.Unit[i]._ReallyEnabled) continue; tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current); @@ -334,6 +324,7 @@ brw_predraw_resolve_buffers(struct brw_context *brw) continue; intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt); intel_miptree_resolve_color(brw, tex_obj->mt); + brw_render_cache_set_check_flush(brw, tex_obj->mt->region->bo); } } @@ -345,6 +336,9 @@ brw_predraw_resolve_buffers(struct brw_context *brw) * * If the color buffer is a multisample window system buffer, then * mark that it needs a downsample. + * + * Also mark any render targets which will be textured as needing a render + * cache flush. */ static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) { @@ -354,17 +348,33 @@ static void brw_postdraw_set_buffers_need_resolve(struct brw_context *brw) struct intel_renderbuffer *front_irb = NULL; struct intel_renderbuffer *back_irb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT); struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); + struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH]; - if (brw->is_front_buffer_rendering) + if (brw_is_front_buffer_drawing(fb)) front_irb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT); if (front_irb) - intel_renderbuffer_set_needs_downsample(front_irb); + front_irb->need_downsample = true; if (back_irb) - intel_renderbuffer_set_needs_downsample(back_irb); - if (depth_irb && ctx->Depth.Mask) + back_irb->need_downsample = true; + if (depth_irb && ctx->Depth.Mask) { intel_renderbuffer_att_set_needs_depth_resolve(depth_att); + brw_render_cache_set_add_bo(brw, depth_irb->mt->region->bo); + } + + if (ctx->Extensions.ARB_stencil_texturing && + stencil_irb && ctx->Stencil._WriteEnabled) { + brw_render_cache_set_add_bo(brw, stencil_irb->mt->region->bo); + } + + for (int i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct intel_renderbuffer *irb = + intel_renderbuffer(fb->_ColorDrawBuffers[i]); + + if (irb) + brw_render_cache_set_add_bo(brw, irb->mt->region->bo); + } } /* May fail if out of video memory for texture or vbo upload, or on @@ -376,7 +386,8 @@ static bool brw_try_draw_prims( struct gl_context *ctx, GLuint nr_prims, const struct _mesa_index_buffer *ib, GLuint min_index, - GLuint max_index ) + GLuint max_index, + struct gl_buffer_object *indirect) { struct brw_context *brw = brw_context(ctx); bool retval = true; @@ -400,7 +411,7 @@ static bool brw_try_draw_prims( struct gl_context *ctx, /* We have to validate the textures *before* checking for fallbacks; * otherwise, the software fallback won't be able to rely on the * texture state, the firstLevel and lastLevel fields won't be - * set in the intel texture object (they'll both be 0), and the + * set in the intel texture object (they'll both be 0), and the * software fallback will segfault if it attempts to access any * texture level other than level 0. */ @@ -498,6 +509,12 @@ retry: } } } + + /* Now that we know we haven't run out of aperture space, we can safely + * reset the dirty bits. + */ + if (brw->state.dirty.brw) + brw_clear_dirty_bits(brw); } if (brw->always_flush_batch) @@ -528,7 +545,7 @@ void brw_draw_prims( struct gl_context *ctx, return; /* Handle primitive restart if needed */ - if (brw_handle_primitive_restart(ctx, prims, nr_prims, ib)) { + if (brw_handle_primitive_restart(ctx, prims, nr_prims, ib, indirect)) { /* The draw was handled, so we can exit now */ return; } @@ -537,7 +554,8 @@ void brw_draw_prims( struct gl_context *ctx, * get the minimum and maximum of their index buffer so we know what range * to upload. */ - if (!vbo_all_varyings_in_vbos(arrays) && !index_bounds_valid) { + if (!index_bounds_valid && + (ctx->RenderMode != GL_RENDER || !vbo_all_varyings_in_vbos(arrays))) { perf_debug("Scanning index buffer to compute index buffer bounds. " "Use glDrawRangeElements() to avoid this.\n"); vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index, nr_prims); @@ -559,7 +577,7 @@ void brw_draw_prims( struct gl_context *ctx, * manage it. swrast doesn't support our featureset, so we can't fall back * to it. */ - brw_try_draw_prims(ctx, arrays, prims, nr_prims, ib, min_index, max_index); + brw_try_draw_prims(ctx, arrays, prims, nr_prims, ib, min_index, max_index, indirect); } void brw_draw_init( struct brw_context *brw ) @@ -568,7 +586,7 @@ void brw_draw_init( struct brw_context *brw ) struct vbo_context *vbo = vbo_context(ctx); int i; - /* Register our drawing function: + /* Register our drawing function: */ vbo->draw_prims = brw_draw_prims;