X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_fs.cpp;h=8580c78fea1ac18ffcc86f0915bdb583fca49ebf;hb=c173541d9769d41a85cc899bc49699a3587df4bf;hp=bdf052300327c4a8487b899a6226a9fa41087deb;hpb=252eaa765e69a70036ec33a7e1e0ffeac1aab2ff;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index bdf05230032..8580c78fea1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -19,10 +19,13 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. + */ + +/** @file brw_fs.cpp * - * Authors: - * Eric Anholt - * + * This file drives the GLSL IR -> LIR translation, contains the + * optimizations on the LIR, and drives the generation of native code + * from the LIR. */ extern "C" { @@ -34,7 +37,6 @@ extern "C" { #include "main/uniforms.h" #include "program/prog_parameter.h" #include "program/prog_print.h" -#include "program/prog_optimize.h" #include "program/register_allocate.h" #include "program/sampler.h" #include "program/hash_table.h" @@ -42,113 +44,15 @@ extern "C" { #include "brw_eu.h" #include "brw_wm.h" } +#include "brw_shader.h" #include "brw_fs.h" #include "../glsl/glsl_types.h" -#include "../glsl/ir_optimization.h" #include "../glsl/ir_print_visitor.h" #define MAX_INSTRUCTION (1 << 30) -static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg); - -struct gl_shader * -brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type) -{ - struct brw_shader *shader; - - shader = rzalloc(NULL, struct brw_shader); - if (shader) { - shader->base.Type = type; - shader->base.Name = name; - _mesa_init_shader(ctx, &shader->base); - } - - return &shader->base; -} - -struct gl_shader_program * -brw_new_shader_program(struct gl_context *ctx, GLuint name) -{ - struct brw_shader_program *prog; - prog = rzalloc(NULL, struct brw_shader_program); - if (prog) { - prog->base.Name = name; - _mesa_init_shader_program(ctx, &prog->base); - } - return &prog->base; -} - -GLboolean -brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) -{ - struct brw_context *brw = brw_context(ctx); - struct intel_context *intel = &brw->intel; - - struct brw_shader *shader = - (struct brw_shader *)prog->_LinkedShaders[MESA_SHADER_FRAGMENT]; - if (shader != NULL) { - void *mem_ctx = ralloc_context(NULL); - bool progress; - - if (shader->ir) - ralloc_free(shader->ir); - shader->ir = new(shader) exec_list; - clone_ir_list(mem_ctx, shader->ir, shader->base.ir); - - do_mat_op_to_vec(shader->ir); - lower_instructions(shader->ir, - MOD_TO_FRACT | - DIV_TO_MUL_RCP | - SUB_TO_ADD_NEG | - EXP_TO_EXP2 | - LOG_TO_LOG2); - - /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, - * if-statements need to be flattened. - */ - if (intel->gen < 6) - lower_if_to_cond_assign(shader->ir, 16); - - do_lower_texture_projection(shader->ir); - do_vec_index_to_cond_assign(shader->ir); - brw_do_cubemap_normalize(shader->ir); - lower_noise(shader->ir); - lower_quadop_vector(shader->ir, false); - lower_variable_index_to_cond_assign(shader->ir, - GL_TRUE, /* input */ - GL_TRUE, /* output */ - GL_TRUE, /* temp */ - GL_TRUE /* uniform */ - ); - - do { - progress = false; - - brw_do_channel_expressions(shader->ir); - brw_do_vector_splitting(shader->ir); - - progress = do_lower_jumps(shader->ir, true, true, - true, /* main return */ - false, /* continue */ - false /* loops */ - ) || progress; - - progress = do_common_optimization(shader->ir, true, 32) || progress; - } while (progress); - - validate_ir_tree(shader->ir); - - reparent_ir(shader->ir, shader->ir); - ralloc_free(mem_ctx); - } - - if (!_mesa_ir_link_shader(ctx, prog)) - return GL_FALSE; - - return GL_TRUE; -} -static int -type_size(const struct glsl_type *type) +int +fs_visitor::type_size(const struct glsl_type *type) { unsigned int size, i; @@ -180,20 +84,52 @@ type_size(const struct glsl_type *type) void fs_visitor::fail(const char *format, ...) { - if (!failed) { - failed = true; + va_list va; + char *msg; + + if (failed) + return; - if (INTEL_DEBUG & DEBUG_WM) { - fprintf(stderr, "FS compile failed: "); + failed = true; - va_list va; - va_start(va, format); - vfprintf(stderr, format, va); - va_end(va); - } + va_start(va, format); + msg = ralloc_vasprintf(mem_ctx, format, va); + va_end(va); + msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg); + + this->fail_msg = msg; + + if (INTEL_DEBUG & DEBUG_WM) { + fprintf(stderr, "%s", msg); } } +void +fs_visitor::push_force_uncompressed() +{ + force_uncompressed_stack++; +} + +void +fs_visitor::pop_force_uncompressed() +{ + force_uncompressed_stack--; + assert(force_uncompressed_stack >= 0); +} + +void +fs_visitor::push_force_sechalf() +{ + force_sechalf_stack++; +} + +void +fs_visitor::pop_force_sechalf() +{ + force_sechalf_stack--; + assert(force_sechalf_stack >= 0); +} + /** * Returns how many MRFs an FS opcode will write over. * @@ -214,9 +150,9 @@ fs_visitor::implied_mrf_writes(fs_inst *inst) case FS_OPCODE_LOG2: case FS_OPCODE_SIN: case FS_OPCODE_COS: - return 1; + return 1 * c->dispatch_width / 8; case FS_OPCODE_POW: - return 2; + return 2 * c->dispatch_width / 8; case FS_OPCODE_TEX: case FS_OPCODE_TXB: case FS_OPCODE_TXD: @@ -271,38 +207,13 @@ fs_reg::fs_reg(enum register_file file, int hw_reg, uint32_t type) this->type = type; } -int -brw_type_for_base_type(const struct glsl_type *type) -{ - switch (type->base_type) { - case GLSL_TYPE_FLOAT: - return BRW_REGISTER_TYPE_F; - case GLSL_TYPE_INT: - case GLSL_TYPE_BOOL: - return BRW_REGISTER_TYPE_D; - case GLSL_TYPE_UINT: - return BRW_REGISTER_TYPE_UD; - case GLSL_TYPE_ARRAY: - case GLSL_TYPE_STRUCT: - case GLSL_TYPE_SAMPLER: - /* These should be overridden with the type of the member when - * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely - * way to trip up if we don't. - */ - return BRW_REGISTER_TYPE_UD; - default: - assert(!"not reached"); - return BRW_REGISTER_TYPE_F; - } -} - /** Automatic reg constructor. */ fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) { init(); this->file = GRF; - this->reg = v->virtual_grf_alloc(type_size(type)); + this->reg = v->virtual_grf_alloc(v->type_size(type)); this->reg_offset = 0; this->type = brw_type_for_base_type(type); } @@ -313,6 +224,31 @@ fs_visitor::variable_storage(ir_variable *var) return (fs_reg *)hash_table_find(this->variable_ht, var); } +void +import_uniforms_callback(const void *key, + void *data, + void *closure) +{ + struct hash_table *dst_ht = (struct hash_table *)closure; + const fs_reg *reg = (const fs_reg *)data; + + if (reg->file != UNIFORM) + return; + + hash_table_insert(dst_ht, data, key); +} + +/* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch. + * This brings in those uniform definitions + */ +void +fs_visitor::import_uniforms(struct hash_table *src_variable_ht) +{ + hash_table_call_foreach(src_variable_ht, + import_uniforms_callback, + variable_ht); +} + /* Our support for uniforms is piggy-backed on the struct * gl_fragment_program, because that's where the values actually * get stored, rather than in some global gl_shader_program uniform @@ -399,59 +335,32 @@ fs_visitor::setup_uniform_values(int loc, const glsl_type *type) void fs_visitor::setup_builtin_uniform_values(ir_variable *ir) { - const struct gl_builtin_uniform_desc *statevar = NULL; - - for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) { - statevar = &_mesa_builtin_uniform_desc[i]; - if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0) - break; - } - - if (!statevar->name) { - fail("Failed to find builtin uniform `%s'\n", ir->name); - return; - } - - int array_count; - if (ir->type->is_array()) { - array_count = ir->type->length; - } else { - array_count = 1; - } - - for (int a = 0; a < array_count; a++) { - for (unsigned int i = 0; i < statevar->num_elements; i++) { - struct gl_builtin_uniform_element *element = &statevar->elements[i]; - int tokens[STATE_LENGTH]; - - memcpy(tokens, element->tokens, sizeof(element->tokens)); - if (ir->type->is_array()) { - tokens[1] = a; - } + const ir_state_slot *const slots = ir->state_slots; + assert(ir->state_slots != NULL); - /* This state reference has already been setup by ir_to_mesa, - * but we'll get the same index back here. - */ - int index = _mesa_add_state_reference(this->fp->Base.Parameters, - (gl_state_index *)tokens); + for (unsigned int i = 0; i < ir->num_state_slots; i++) { + /* This state reference has already been setup by ir_to_mesa, but we'll + * get the same index back here. + */ + int index = _mesa_add_state_reference(this->fp->Base.Parameters, + (gl_state_index *)slots[i].tokens); - /* Add each of the unique swizzles of the element as a - * parameter. This'll end up matching the expected layout of - * the array/matrix/structure we're trying to fill in. - */ - int last_swiz = -1; - for (unsigned int j = 0; j < 4; j++) { - int swiz = GET_SWZ(element->swizzle, j); - if (swiz == last_swiz) - break; - last_swiz = swiz; + /* Add each of the unique swizzles of the element as a parameter. + * This'll end up matching the expected layout of the + * array/matrix/structure we're trying to fill in. + */ + int last_swiz = -1; + for (unsigned int j = 0; j < 4; j++) { + int swiz = GET_SWZ(slots[i].swizzle, j); + if (swiz == last_swiz) + break; + last_swiz = swiz; - c->prog_data.param_convert[c->prog_data.nr_params] = - PARAM_NO_CONVERT; - this->param_index[c->prog_data.nr_params] = index; - this->param_offset[c->prog_data.nr_params] = swiz; - c->prog_data.nr_params++; - } + c->prog_data.param_convert[c->prog_data.nr_params] = + PARAM_NO_CONVERT; + this->param_index[c->prog_data.nr_params] = index; + this->param_offset[c->prog_data.nr_params] = swiz; + c->prog_data.nr_params++; } } } @@ -461,8 +370,6 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir) { fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); fs_reg wpos = *reg; - fs_reg neg_y = this->pixel_y; - neg_y.negate = true; bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo; /* gl_FragCoord.x */ @@ -562,7 +469,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir) attr.reg_offset++; } - if (intel->gen < 6 && !(is_gl_Color && c->key.linear_color)) { + if (intel->gen < 6) { attr.reg_offset -= type->vector_elements; for (unsigned int k = 0; k < type->vector_elements; k++) { emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w); @@ -641,1909 +548,47 @@ fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src) if (intel->gen < 6) { inst->base_mrf = 2; - inst->mlen = 1; - } - - return inst; -} - -fs_inst * -fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1) -{ - int base_mrf = 2; - fs_inst *inst; - - assert(opcode == FS_OPCODE_POW); - - if (intel->gen >= 6) { - /* Can't do hstride == 0 args to gen6 math, so expand it out. - * - * The hardware ignores source modifiers (negate and abs) on math - * instructions, so we also move to a temp to set those up. - */ - if (src0.file == UNIFORM || src0.abs || src0.negate) { - fs_reg expanded = fs_reg(this, glsl_type::float_type); - emit(BRW_OPCODE_MOV, expanded, src0); - src0 = expanded; - } - - if (src1.file == UNIFORM || src1.abs || src1.negate) { - fs_reg expanded = fs_reg(this, glsl_type::float_type); - emit(BRW_OPCODE_MOV, expanded, src1); - src1 = expanded; - } - - inst = emit(opcode, dst, src0, src1); - } else { - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1); - inst = emit(opcode, dst, src0, reg_null_f); - - inst->base_mrf = base_mrf; - inst->mlen = 2; - } - return inst; -} - -void -fs_visitor::visit(ir_variable *ir) -{ - fs_reg *reg = NULL; - - if (variable_storage(ir)) - return; - - if (strcmp(ir->name, "gl_FragColor") == 0) { - this->frag_color = ir; - } else if (strcmp(ir->name, "gl_FragData") == 0) { - this->frag_data = ir; - } else if (strcmp(ir->name, "gl_FragDepth") == 0) { - this->frag_depth = ir; - } - - if (ir->mode == ir_var_in) { - if (!strcmp(ir->name, "gl_FragCoord")) { - reg = emit_fragcoord_interpolation(ir); - } else if (!strcmp(ir->name, "gl_FrontFacing")) { - reg = emit_frontfacing_interpolation(ir); - } else { - reg = emit_general_interpolation(ir); - } - assert(reg); - hash_table_insert(this->variable_ht, reg, ir); - return; - } - - if (ir->mode == ir_var_uniform) { - int param_index = c->prog_data.nr_params; - - if (!strncmp(ir->name, "gl_", 3)) { - setup_builtin_uniform_values(ir); - } else { - setup_uniform_values(ir->location, ir->type); - } - - reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index); - reg->type = brw_type_for_base_type(ir->type); - } - - if (!reg) - reg = new(this->mem_ctx) fs_reg(this, ir->type); - - hash_table_insert(this->variable_ht, reg, ir); -} - -void -fs_visitor::visit(ir_dereference_variable *ir) -{ - fs_reg *reg = variable_storage(ir->var); - this->result = *reg; -} - -void -fs_visitor::visit(ir_dereference_record *ir) -{ - const glsl_type *struct_type = ir->record->type; - - ir->record->accept(this); - - unsigned int offset = 0; - for (unsigned int i = 0; i < struct_type->length; i++) { - if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0) - break; - offset += type_size(struct_type->fields.structure[i].type); - } - this->result.reg_offset += offset; - this->result.type = brw_type_for_base_type(ir->type); -} - -void -fs_visitor::visit(ir_dereference_array *ir) -{ - ir_constant *index; - int element_size; - - ir->array->accept(this); - index = ir->array_index->as_constant(); - - element_size = type_size(ir->type); - this->result.type = brw_type_for_base_type(ir->type); - - if (index) { - assert(this->result.file == UNIFORM || - (this->result.file == GRF && - this->result.reg != 0)); - this->result.reg_offset += index->value.i[0] * element_size; - } else { - assert(!"FINISHME: non-constant array element"); - } -} - -/* Instruction selection: Produce a MOV.sat instead of - * MIN(MAX(val, 0), 1) when possible. - */ -bool -fs_visitor::try_emit_saturate(ir_expression *ir) -{ - ir_rvalue *sat_val = ir->as_rvalue_to_saturate(); - - if (!sat_val) - return false; - - sat_val->accept(this); - fs_reg src = this->result; - - this->result = fs_reg(this, ir->type); - fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src); - inst->saturate = true; - - return true; -} - -static uint32_t -brw_conditional_for_comparison(unsigned int op) -{ - switch (op) { - case ir_binop_less: - return BRW_CONDITIONAL_L; - case ir_binop_greater: - return BRW_CONDITIONAL_G; - case ir_binop_lequal: - return BRW_CONDITIONAL_LE; - case ir_binop_gequal: - return BRW_CONDITIONAL_GE; - case ir_binop_equal: - case ir_binop_all_equal: /* same as equal for scalars */ - return BRW_CONDITIONAL_Z; - case ir_binop_nequal: - case ir_binop_any_nequal: /* same as nequal for scalars */ - return BRW_CONDITIONAL_NZ; - default: - assert(!"not reached: bad operation for comparison"); - return BRW_CONDITIONAL_NZ; - } -} - -void -fs_visitor::visit(ir_expression *ir) -{ - unsigned int operand; - fs_reg op[2], temp; - fs_inst *inst; - - assert(ir->get_num_operands() <= 2); - - if (try_emit_saturate(ir)) - return; - - for (operand = 0; operand < ir->get_num_operands(); operand++) { - ir->operands[operand]->accept(this); - if (this->result.file == BAD_FILE) { - ir_print_visitor v; - fail("Failed to get tree for expression operand:\n"); - ir->operands[operand]->accept(&v); - } - op[operand] = this->result; - - /* Matrix expression operands should have been broken down to vector - * operations already. - */ - assert(!ir->operands[operand]->type->is_matrix()); - /* And then those vector operands should have been broken down to scalar. - */ - assert(!ir->operands[operand]->type->is_vector()); - } - - /* Storage for our result. If our result goes into an assignment, it will - * just get copy-propagated out, so no worries. - */ - this->result = fs_reg(this, ir->type); - - switch (ir->operation) { - case ir_unop_logic_not: - /* Note that BRW_OPCODE_NOT is not appropriate here, since it is - * ones complement of the whole register, not just bit 0. - */ - emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)); - break; - case ir_unop_neg: - op[0].negate = !op[0].negate; - this->result = op[0]; - break; - case ir_unop_abs: - op[0].abs = true; - op[0].negate = false; - this->result = op[0]; - break; - case ir_unop_sign: - temp = fs_reg(this, ir->type); - - emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)); - - inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); - inst->conditional_mod = BRW_CONDITIONAL_G; - inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)); - inst->predicated = true; - - inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)); - inst->conditional_mod = BRW_CONDITIONAL_L; - inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)); - inst->predicated = true; - - break; - case ir_unop_rcp: - emit_math(FS_OPCODE_RCP, this->result, op[0]); - break; - - case ir_unop_exp2: - emit_math(FS_OPCODE_EXP2, this->result, op[0]); - break; - case ir_unop_log2: - emit_math(FS_OPCODE_LOG2, this->result, op[0]); - break; - case ir_unop_exp: - case ir_unop_log: - assert(!"not reached: should be handled by ir_explog_to_explog2"); - break; - case ir_unop_sin: - case ir_unop_sin_reduced: - emit_math(FS_OPCODE_SIN, this->result, op[0]); - break; - case ir_unop_cos: - case ir_unop_cos_reduced: - emit_math(FS_OPCODE_COS, this->result, op[0]); - break; - - case ir_unop_dFdx: - emit(FS_OPCODE_DDX, this->result, op[0]); - break; - case ir_unop_dFdy: - emit(FS_OPCODE_DDY, this->result, op[0]); - break; - - case ir_binop_add: - emit(BRW_OPCODE_ADD, this->result, op[0], op[1]); - break; - case ir_binop_sub: - assert(!"not reached: should be handled by ir_sub_to_add_neg"); - break; - - case ir_binop_mul: - emit(BRW_OPCODE_MUL, this->result, op[0], op[1]); - break; - case ir_binop_div: - assert(!"not reached: should be handled by ir_div_to_mul_rcp"); - break; - case ir_binop_mod: - assert(!"ir_binop_mod should have been converted to b * fract(a/b)"); - break; - - case ir_binop_less: - case ir_binop_greater: - case ir_binop_lequal: - case ir_binop_gequal: - case ir_binop_equal: - case ir_binop_all_equal: - case ir_binop_nequal: - case ir_binop_any_nequal: - temp = this->result; - /* original gen4 does implicit conversion before comparison. */ - if (intel->gen < 5) - temp.type = op[0].type; - - inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]); - inst->conditional_mod = brw_conditional_for_comparison(ir->operation); - emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)); - break; - - case ir_binop_logic_xor: - emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); - break; - - case ir_binop_logic_or: - emit(BRW_OPCODE_OR, this->result, op[0], op[1]); - break; - - case ir_binop_logic_and: - emit(BRW_OPCODE_AND, this->result, op[0], op[1]); - break; - - case ir_binop_dot: - case ir_unop_any: - assert(!"not reached: should be handled by brw_fs_channel_expressions"); - break; - - case ir_unop_noise: - assert(!"not reached: should be handled by lower_noise"); - break; - - case ir_quadop_vector: - assert(!"not reached: should be handled by lower_quadop_vector"); - break; - - case ir_unop_sqrt: - emit_math(FS_OPCODE_SQRT, this->result, op[0]); - break; - - case ir_unop_rsq: - emit_math(FS_OPCODE_RSQ, this->result, op[0]); - break; - - case ir_unop_i2f: - case ir_unop_b2f: - case ir_unop_b2i: - case ir_unop_f2i: - emit(BRW_OPCODE_MOV, this->result, op[0]); - break; - case ir_unop_f2b: - case ir_unop_i2b: - temp = this->result; - /* original gen4 does implicit conversion before comparison. */ - if (intel->gen < 5) - temp.type = op[0].type; - - inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1)); - break; - - case ir_unop_trunc: - emit(BRW_OPCODE_RNDZ, this->result, op[0]); - break; - case ir_unop_ceil: - op[0].negate = !op[0].negate; - inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); - this->result.negate = true; - break; - case ir_unop_floor: - inst = emit(BRW_OPCODE_RNDD, this->result, op[0]); - break; - case ir_unop_fract: - inst = emit(BRW_OPCODE_FRC, this->result, op[0]); - break; - case ir_unop_round_even: - emit(BRW_OPCODE_RNDE, this->result, op[0]); - break; - - case ir_binop_min: - inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_L; - - inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); - inst->predicated = true; - break; - case ir_binop_max: - inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_G; - - inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]); - inst->predicated = true; - break; - - case ir_binop_pow: - emit_math(FS_OPCODE_POW, this->result, op[0], op[1]); - break; - - case ir_unop_bit_not: - inst = emit(BRW_OPCODE_NOT, this->result, op[0]); - break; - case ir_binop_bit_and: - inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]); - break; - case ir_binop_bit_xor: - inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]); - break; - case ir_binop_bit_or: - inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]); - break; - - case ir_unop_u2f: - case ir_binop_lshift: - case ir_binop_rshift: - assert(!"GLSL 1.30 features unsupported"); - break; - } -} - -void -fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r, - const glsl_type *type, bool predicated) -{ - switch (type->base_type) { - case GLSL_TYPE_FLOAT: - case GLSL_TYPE_UINT: - case GLSL_TYPE_INT: - case GLSL_TYPE_BOOL: - for (unsigned int i = 0; i < type->components(); i++) { - l.type = brw_type_for_base_type(type); - r.type = brw_type_for_base_type(type); - - fs_inst *inst = emit(BRW_OPCODE_MOV, l, r); - inst->predicated = predicated; - - l.reg_offset++; - r.reg_offset++; - } - break; - case GLSL_TYPE_ARRAY: - for (unsigned int i = 0; i < type->length; i++) { - emit_assignment_writes(l, r, type->fields.array, predicated); - } - break; - - case GLSL_TYPE_STRUCT: - for (unsigned int i = 0; i < type->length; i++) { - emit_assignment_writes(l, r, type->fields.structure[i].type, - predicated); - } - break; - - case GLSL_TYPE_SAMPLER: - break; - - default: - assert(!"not reached"); - break; - } -} - -void -fs_visitor::visit(ir_assignment *ir) -{ - struct fs_reg l, r; - fs_inst *inst; - - /* FINISHME: arrays on the lhs */ - ir->lhs->accept(this); - l = this->result; - - ir->rhs->accept(this); - r = this->result; - - assert(l.file != BAD_FILE); - assert(r.file != BAD_FILE); - - if (ir->condition) { - emit_bool_to_cond_code(ir->condition); - } - - if (ir->lhs->type->is_scalar() || - ir->lhs->type->is_vector()) { - for (int i = 0; i < ir->lhs->type->vector_elements; i++) { - if (ir->write_mask & (1 << i)) { - inst = emit(BRW_OPCODE_MOV, l, r); - if (ir->condition) - inst->predicated = true; - r.reg_offset++; - } - l.reg_offset++; - } - } else { - emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL); - } -} - -fs_inst * -fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate) -{ - int mlen; - int base_mrf = 1; - bool simd16 = false; - fs_reg orig_dst; - - /* g0 header. */ - mlen = 1; - - if (ir->shadow_comparitor) { - for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); - coordinate.reg_offset++; - } - /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ - mlen += 3; - - if (ir->op == ir_tex) { - /* There's no plain shadow compare message, so we use shadow - * compare with a bias of 0.0. - */ - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)); - mlen++; - } else if (ir->op == ir_txb) { - ir->lod_info.bias->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } else { - assert(ir->op == ir_txl); - ir->lod_info.lod->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } - - ir->shadow_comparitor->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } else if (ir->op == ir_tex) { - for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); - coordinate.reg_offset++; - } - /* gen4's SIMD8 sampler always has the slots for u,v,r present. */ - mlen += 3; - } else if (ir->op == ir_txd) { - assert(!"TXD isn't supported on gen4 yet."); - } else { - /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod - * instructions. We'll need to do SIMD16 here. - */ - assert(ir->op == ir_txb || ir->op == ir_txl); - - for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2), coordinate); - coordinate.reg_offset++; - } - - /* lod/bias appears after u/v/r. */ - mlen += 6; - - if (ir->op == ir_txb) { - ir->lod_info.bias->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } else { - ir->lod_info.lod->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } - - /* The unused upper half. */ - mlen++; - - /* Now, since we're doing simd16, the return is 2 interleaved - * vec4s where the odd-indexed ones are junk. We'll need to move - * this weirdness around to the expected layout. - */ - simd16 = true; - orig_dst = dst; - dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type, - 2)); - dst.type = BRW_REGISTER_TYPE_F; - } - - fs_inst *inst = NULL; - switch (ir->op) { - case ir_tex: - inst = emit(FS_OPCODE_TEX, dst); - break; - case ir_txb: - inst = emit(FS_OPCODE_TXB, dst); - break; - case ir_txl: - inst = emit(FS_OPCODE_TXL, dst); - break; - case ir_txd: - inst = emit(FS_OPCODE_TXD, dst); - break; - case ir_txf: - assert(!"GLSL 1.30 features unsupported"); - break; - } - inst->base_mrf = base_mrf; - inst->mlen = mlen; - - if (simd16) { - for (int i = 0; i < 4; i++) { - emit(BRW_OPCODE_MOV, orig_dst, dst); - orig_dst.reg_offset++; - dst.reg_offset += 2; - } - } - - return inst; -} - -fs_inst * -fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate) -{ - /* gen5's SIMD8 sampler has slots for u, v, r, array index, then - * optional parameters like shadow comparitor or LOD bias. If - * optional parameters aren't present, those base slots are - * optional and don't need to be included in the message. - * - * We don't fill in the unnecessary slots regardless, which may - * look surprising in the disassembly. - */ - int mlen = 1; /* g0 header always present. */ - int base_mrf = 1; - - for (int i = 0; i < ir->coordinate->type->vector_elements; i++) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate); - coordinate.reg_offset++; - } - mlen += ir->coordinate->type->vector_elements; - - if (ir->shadow_comparitor) { - mlen = MAX2(mlen, 5); - - ir->shadow_comparitor->accept(this); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - } - - fs_inst *inst = NULL; - switch (ir->op) { - case ir_tex: - inst = emit(FS_OPCODE_TEX, dst); - break; - case ir_txb: - ir->lod_info.bias->accept(this); - mlen = MAX2(mlen, 5); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - - inst = emit(FS_OPCODE_TXB, dst); - break; - case ir_txl: - ir->lod_info.lod->accept(this); - mlen = MAX2(mlen, 5); - emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result); - mlen++; - - inst = emit(FS_OPCODE_TXL, dst); - break; - case ir_txd: - case ir_txf: - assert(!"GLSL 1.30 features unsupported"); - break; - } - inst->base_mrf = base_mrf; - inst->mlen = mlen; - - return inst; -} - -void -fs_visitor::visit(ir_texture *ir) -{ - int sampler; - fs_inst *inst = NULL; - - ir->coordinate->accept(this); - fs_reg coordinate = this->result; - - if (ir->offset != NULL) { - ir_constant *offset = ir->offset->as_constant(); - assert(offset != NULL); - - signed char offsets[3]; - for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) - offsets[i] = (signed char) offset->value.i[i]; - - /* Combine all three offsets into a single unsigned dword: - * - * bits 11:8 - U Offset (X component) - * bits 7:4 - V Offset (Y component) - * bits 3:0 - R Offset (Z component) - */ - unsigned offset_bits = 0; - for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) { - const unsigned shift = 4 * (2 - i); - offset_bits |= (offsets[i] << shift) & (0xF << shift); - } - - /* Explicitly set up the message header by copying g0 to msg reg m1. */ - emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD), - fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD)); - - /* Then set the offset bits in DWord 2 of the message header. */ - emit(BRW_OPCODE_MOV, - fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2), - BRW_REGISTER_TYPE_UD)), - fs_reg(brw_imm_uw(offset_bits))); - } - - /* Should be lowered by do_lower_texture_projection */ - assert(!ir->projector); - - sampler = _mesa_get_sampler_uniform_value(ir->sampler, - ctx->Shader.CurrentFragmentProgram, - &brw->fragment_program->Base); - sampler = c->fp->program.Base.SamplerUnits[sampler]; - - /* The 965 requires the EU to do the normalization of GL rectangle - * texture coordinates. We use the program parameter state - * tracking to get the scaling factor. - */ - if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) { - struct gl_program_parameter_list *params = c->fp->program.Base.Parameters; - int tokens[STATE_LENGTH] = { - STATE_INTERNAL, - STATE_TEXRECT_SCALE, - sampler, - 0, - 0 - }; - - c->prog_data.param_convert[c->prog_data.nr_params] = - PARAM_NO_CONVERT; - c->prog_data.param_convert[c->prog_data.nr_params + 1] = - PARAM_NO_CONVERT; - - fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params); - fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1); - GLuint index = _mesa_add_state_reference(params, - (gl_state_index *)tokens); - - this->param_index[c->prog_data.nr_params] = index; - this->param_offset[c->prog_data.nr_params] = 0; - c->prog_data.nr_params++; - this->param_index[c->prog_data.nr_params] = index; - this->param_offset[c->prog_data.nr_params] = 1; - c->prog_data.nr_params++; - - fs_reg dst = fs_reg(this, ir->coordinate->type); - fs_reg src = coordinate; - coordinate = dst; - - emit(BRW_OPCODE_MUL, dst, src, scale_x); - dst.reg_offset++; - src.reg_offset++; - emit(BRW_OPCODE_MUL, dst, src, scale_y); - } - - /* Writemasking doesn't eliminate channels on SIMD8 texture - * samples, so don't worry about them. - */ - fs_reg dst = fs_reg(this, glsl_type::vec4_type); - - if (intel->gen < 5) { - inst = emit_texture_gen4(ir, dst, coordinate); - } else { - inst = emit_texture_gen5(ir, dst, coordinate); - } - - /* If there's an offset, we already set up m1. To avoid the implied move, - * use the null register. Otherwise, we want an implied move from g0. - */ - if (ir->offset != NULL) - inst->src[0] = fs_reg(brw_null_reg()); - else - inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW)); - - inst->sampler = sampler; - - this->result = dst; - - if (ir->shadow_comparitor) - inst->shadow_compare = true; - - if (ir->type == glsl_type::float_type) { - /* Ignore DEPTH_TEXTURE_MODE swizzling. */ - assert(ir->sampler->type->sampler_shadow); - } else if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) { - fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type); - - for (int i = 0; i < 4; i++) { - int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i); - fs_reg l = swizzle_dst; - l.reg_offset += i; - - if (swiz == SWIZZLE_ZERO) { - emit(BRW_OPCODE_MOV, l, fs_reg(0.0f)); - } else if (swiz == SWIZZLE_ONE) { - emit(BRW_OPCODE_MOV, l, fs_reg(1.0f)); - } else { - fs_reg r = dst; - r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i); - emit(BRW_OPCODE_MOV, l, r); - } - } - this->result = swizzle_dst; - } -} - -void -fs_visitor::visit(ir_swizzle *ir) -{ - ir->val->accept(this); - fs_reg val = this->result; - - if (ir->type->vector_elements == 1) { - this->result.reg_offset += ir->mask.x; - return; - } - - fs_reg result = fs_reg(this, ir->type); - this->result = result; - - for (unsigned int i = 0; i < ir->type->vector_elements; i++) { - fs_reg channel = val; - int swiz = 0; - - switch (i) { - case 0: - swiz = ir->mask.x; - break; - case 1: - swiz = ir->mask.y; - break; - case 2: - swiz = ir->mask.z; - break; - case 3: - swiz = ir->mask.w; - break; - } - - channel.reg_offset += swiz; - emit(BRW_OPCODE_MOV, result, channel); - result.reg_offset++; - } -} - -void -fs_visitor::visit(ir_discard *ir) -{ - fs_reg temp = fs_reg(this, glsl_type::uint_type); - - assert(ir->condition == NULL); /* FINISHME */ - - emit(FS_OPCODE_DISCARD_NOT, temp, reg_null_d); - emit(FS_OPCODE_DISCARD_AND, reg_null_d, temp); - kill_emitted = true; -} - -void -fs_visitor::visit(ir_constant *ir) -{ - /* Set this->result to reg at the bottom of the function because some code - * paths will cause this visitor to be applied to other fields. This will - * cause the value stored in this->result to be modified. - * - * Make reg constant so that it doesn't get accidentally modified along the - * way. Yes, I actually had this problem. :( - */ - const fs_reg reg(this, ir->type); - fs_reg dst_reg = reg; - - if (ir->type->is_array()) { - const unsigned size = type_size(ir->type->fields.array); - - for (unsigned i = 0; i < ir->type->length; i++) { - ir->array_elements[i]->accept(this); - fs_reg src_reg = this->result; - - dst_reg.type = src_reg.type; - for (unsigned j = 0; j < size; j++) { - emit(BRW_OPCODE_MOV, dst_reg, src_reg); - src_reg.reg_offset++; - dst_reg.reg_offset++; - } - } - } else if (ir->type->is_record()) { - foreach_list(node, &ir->components) { - ir_instruction *const field = (ir_instruction *) node; - const unsigned size = type_size(field->type); - - field->accept(this); - fs_reg src_reg = this->result; - - dst_reg.type = src_reg.type; - for (unsigned j = 0; j < size; j++) { - emit(BRW_OPCODE_MOV, dst_reg, src_reg); - src_reg.reg_offset++; - dst_reg.reg_offset++; - } - } - } else { - const unsigned size = type_size(ir->type); - - for (unsigned i = 0; i < size; i++) { - switch (ir->type->base_type) { - case GLSL_TYPE_FLOAT: - emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])); - break; - case GLSL_TYPE_UINT: - emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])); - break; - case GLSL_TYPE_INT: - emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])); - break; - case GLSL_TYPE_BOOL: - emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])); - break; - default: - assert(!"Non-float/uint/int/bool constant"); - } - dst_reg.reg_offset++; - } - } - - this->result = reg; -} - -void -fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir) -{ - ir_expression *expr = ir->as_expression(); - - if (expr) { - fs_reg op[2]; - fs_inst *inst; - - assert(expr->get_num_operands() <= 2); - for (unsigned int i = 0; i < expr->get_num_operands(); i++) { - assert(expr->operands[i]->type->is_scalar()); - - expr->operands[i]->accept(this); - op[i] = this->result; - } - - switch (expr->operation) { - case ir_unop_logic_not: - inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)); - inst->conditional_mod = BRW_CONDITIONAL_Z; - break; - - case ir_binop_logic_xor: - inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - break; - - case ir_binop_logic_or: - inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - break; - - case ir_binop_logic_and: - inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - break; - - case ir_unop_f2b: - if (intel->gen >= 6) { - inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f)); - } else { - inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]); - } - inst->conditional_mod = BRW_CONDITIONAL_NZ; - break; - - case ir_unop_i2b: - if (intel->gen >= 6) { - inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)); - } else { - inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]); - } - inst->conditional_mod = BRW_CONDITIONAL_NZ; - break; - - case ir_binop_greater: - case ir_binop_gequal: - case ir_binop_less: - case ir_binop_lequal: - case ir_binop_equal: - case ir_binop_all_equal: - case ir_binop_nequal: - case ir_binop_any_nequal: - inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]); - inst->conditional_mod = - brw_conditional_for_comparison(expr->operation); - break; - - default: - assert(!"not reached"); - fail("bad cond code\n"); - break; - } - return; - } - - ir->accept(this); - - if (intel->gen >= 6) { - fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - } else { - fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - } -} - -/** - * Emit a gen6 IF statement with the comparison folded into the IF - * instruction. - */ -void -fs_visitor::emit_if_gen6(ir_if *ir) -{ - ir_expression *expr = ir->condition->as_expression(); - - if (expr) { - fs_reg op[2]; - fs_inst *inst; - fs_reg temp; - - assert(expr->get_num_operands() <= 2); - for (unsigned int i = 0; i < expr->get_num_operands(); i++) { - assert(expr->operands[i]->type->is_scalar()); - - expr->operands[i]->accept(this); - op[i] = this->result; - } - - switch (expr->operation) { - case ir_unop_logic_not: - inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_Z; - return; - - case ir_binop_logic_xor: - inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - return; - - case ir_binop_logic_or: - temp = fs_reg(this, glsl_type::bool_type); - emit(BRW_OPCODE_OR, temp, op[0], op[1]); - inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - return; - - case ir_binop_logic_and: - temp = fs_reg(this, glsl_type::bool_type); - emit(BRW_OPCODE_AND, temp, op[0], op[1]); - inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - return; - - case ir_unop_f2b: - inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - return; - - case ir_unop_i2b: - inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - return; - - case ir_binop_greater: - case ir_binop_gequal: - case ir_binop_less: - case ir_binop_lequal: - case ir_binop_equal: - case ir_binop_all_equal: - case ir_binop_nequal: - case ir_binop_any_nequal: - inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]); - inst->conditional_mod = - brw_conditional_for_comparison(expr->operation); - return; - default: - assert(!"not reached"); - inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; - fail("bad condition\n"); - return; - } - return; - } - - ir->condition->accept(this); - - fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)); - inst->conditional_mod = BRW_CONDITIONAL_NZ; -} - -void -fs_visitor::visit(ir_if *ir) -{ - fs_inst *inst; - - /* Don't point the annotation at the if statement, because then it plus - * the then and else blocks get printed. - */ - this->base_ir = ir->condition; - - if (intel->gen >= 6) { - emit_if_gen6(ir); - } else { - emit_bool_to_cond_code(ir->condition); - - inst = emit(BRW_OPCODE_IF); - inst->predicated = true; - } - - foreach_iter(exec_list_iterator, iter, ir->then_instructions) { - ir_instruction *ir = (ir_instruction *)iter.get(); - this->base_ir = ir; - - ir->accept(this); - } - - if (!ir->else_instructions.is_empty()) { - emit(BRW_OPCODE_ELSE); - - foreach_iter(exec_list_iterator, iter, ir->else_instructions) { - ir_instruction *ir = (ir_instruction *)iter.get(); - this->base_ir = ir; - - ir->accept(this); - } - } - - emit(BRW_OPCODE_ENDIF); -} - -void -fs_visitor::visit(ir_loop *ir) -{ - fs_reg counter = reg_undef; - - if (ir->counter) { - this->base_ir = ir->counter; - ir->counter->accept(this); - counter = *(variable_storage(ir->counter)); - - if (ir->from) { - this->base_ir = ir->from; - ir->from->accept(this); - - emit(BRW_OPCODE_MOV, counter, this->result); - } - } - - emit(BRW_OPCODE_DO); - - if (ir->to) { - this->base_ir = ir->to; - ir->to->accept(this); - - fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result); - inst->conditional_mod = brw_conditional_for_comparison(ir->cmp); - - inst = emit(BRW_OPCODE_BREAK); - inst->predicated = true; - } - - foreach_iter(exec_list_iterator, iter, ir->body_instructions) { - ir_instruction *ir = (ir_instruction *)iter.get(); - - this->base_ir = ir; - ir->accept(this); - } - - if (ir->increment) { - this->base_ir = ir->increment; - ir->increment->accept(this); - emit(BRW_OPCODE_ADD, counter, counter, this->result); - } - - emit(BRW_OPCODE_WHILE); -} - -void -fs_visitor::visit(ir_loop_jump *ir) -{ - switch (ir->mode) { - case ir_loop_jump::jump_break: - emit(BRW_OPCODE_BREAK); - break; - case ir_loop_jump::jump_continue: - emit(BRW_OPCODE_CONTINUE); - break; - } -} - -void -fs_visitor::visit(ir_call *ir) -{ - assert(!"FINISHME"); -} - -void -fs_visitor::visit(ir_return *ir) -{ - assert(!"FINISHME"); -} - -void -fs_visitor::visit(ir_function *ir) -{ - /* Ignore function bodies other than main() -- we shouldn't see calls to - * them since they should all be inlined before we get to ir_to_mesa. - */ - if (strcmp(ir->name, "main") == 0) { - const ir_function_signature *sig; - exec_list empty; - - sig = ir->matching_signature(&empty); - - assert(sig); - - foreach_iter(exec_list_iterator, iter, sig->body) { - ir_instruction *ir = (ir_instruction *)iter.get(); - this->base_ir = ir; - - ir->accept(this); - } - } -} - -void -fs_visitor::visit(ir_function_signature *ir) -{ - assert(!"not reached"); - (void)ir; -} - -fs_inst * -fs_visitor::emit(fs_inst inst) -{ - fs_inst *list_inst = new(mem_ctx) fs_inst; - *list_inst = inst; - - list_inst->annotation = this->current_annotation; - list_inst->ir = this->base_ir; - - this->instructions.push_tail(list_inst); - - return list_inst; -} - -/** Emits a dummy fragment shader consisting of magenta for bringup purposes. */ -void -fs_visitor::emit_dummy_fs() -{ - /* Everyone's favorite color. */ - emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f)); - emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f)); - - fs_inst *write; - write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0)); - write->base_mrf = 0; -} - -/* The register location here is relative to the start of the URB - * data. It will get adjusted to be a real location before - * generate_code() time. - */ -struct brw_reg -fs_visitor::interp_reg(int location, int channel) -{ - int regnr = urb_setup[location] * 2 + channel / 2; - int stride = (channel & 1) * 4; - - assert(urb_setup[location] != -1); - - return brw_vec1_grf(regnr, stride); -} - -/** Emits the interpolation for the varying inputs. */ -void -fs_visitor::emit_interpolation_setup_gen4() -{ - struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); - - this->current_annotation = "compute pixel centers"; - this->pixel_x = fs_reg(this, glsl_type::uint_type); - this->pixel_y = fs_reg(this, glsl_type::uint_type); - this->pixel_x.type = BRW_REGISTER_TYPE_UW; - this->pixel_y.type = BRW_REGISTER_TYPE_UW; - emit(BRW_OPCODE_ADD, - this->pixel_x, - fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), - fs_reg(brw_imm_v(0x10101010))); - emit(BRW_OPCODE_ADD, - this->pixel_y, - fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), - fs_reg(brw_imm_v(0x11001100))); - - this->current_annotation = "compute pixel deltas from v0"; - if (brw->has_pln) { - this->delta_x = fs_reg(this, glsl_type::vec2_type); - this->delta_y = this->delta_x; - this->delta_y.reg_offset++; - } else { - this->delta_x = fs_reg(this, glsl_type::float_type); - this->delta_y = fs_reg(this, glsl_type::float_type); - } - emit(BRW_OPCODE_ADD, this->delta_x, - this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))); - emit(BRW_OPCODE_ADD, this->delta_y, - this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))); - - this->current_annotation = "compute pos.w and 1/pos.w"; - /* Compute wpos.w. It's always in our setup, since it's needed to - * interpolate the other attributes. - */ - this->wpos_w = fs_reg(this, glsl_type::float_type); - emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y, - interp_reg(FRAG_ATTRIB_WPOS, 3)); - /* Compute the pixel 1/W value from wpos.w. */ - this->pixel_w = fs_reg(this, glsl_type::float_type); - emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); - this->current_annotation = NULL; -} - -/** Emits the interpolation for the varying inputs. */ -void -fs_visitor::emit_interpolation_setup_gen6() -{ - struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); - - /* If the pixel centers end up used, the setup is the same as for gen4. */ - this->current_annotation = "compute pixel centers"; - fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type); - fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type); - int_pixel_x.type = BRW_REGISTER_TYPE_UW; - int_pixel_y.type = BRW_REGISTER_TYPE_UW; - emit(BRW_OPCODE_ADD, - int_pixel_x, - fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)), - fs_reg(brw_imm_v(0x10101010))); - emit(BRW_OPCODE_ADD, - int_pixel_y, - fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)), - fs_reg(brw_imm_v(0x11001100))); - - /* As of gen6, we can no longer mix float and int sources. We have - * to turn the integer pixel centers into floats for their actual - * use. - */ - this->pixel_x = fs_reg(this, glsl_type::float_type); - this->pixel_y = fs_reg(this, glsl_type::float_type); - emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x); - emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y); - - this->current_annotation = "compute 1/pos.w"; - this->wpos_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0)); - this->pixel_w = fs_reg(this, glsl_type::float_type); - emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w); - - this->delta_x = fs_reg(brw_vec8_grf(2, 0)); - this->delta_y = fs_reg(brw_vec8_grf(3, 0)); - - this->current_annotation = NULL; -} - -void -fs_visitor::emit_fb_writes() -{ - this->current_annotation = "FB write header"; - GLboolean header_present = GL_TRUE; - int nr = 0; - - if (intel->gen >= 6 && - !this->kill_emitted && - c->key.nr_color_regions == 1) { - header_present = false; - } - - if (header_present) { - /* m0, m1 header */ - nr += 2; - } - - if (c->aa_dest_stencil_reg) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), - fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))); - } - - /* Reserve space for color. It'll be filled in per MRT below. */ - int color_mrf = nr; - nr += 4; - - if (c->source_depth_to_render_target) { - if (c->computes_depth) { - /* Hand over gl_FragDepth. */ - assert(this->frag_depth); - fs_reg depth = *(variable_storage(this->frag_depth)); - - emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth); - } else { - /* Pass through the payload depth. */ - emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), - fs_reg(brw_vec8_grf(c->source_depth_reg, 0))); - } - } - - if (c->dest_depth_reg) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), - fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))); - } - - fs_reg color = reg_undef; - if (this->frag_color) - color = *(variable_storage(this->frag_color)); - else if (this->frag_data) { - color = *(variable_storage(this->frag_data)); - color.type = BRW_REGISTER_TYPE_F; - } - - for (int target = 0; target < c->key.nr_color_regions; target++) { - this->current_annotation = ralloc_asprintf(this->mem_ctx, - "FB write target %d", - target); - if (this->frag_color || this->frag_data) { - for (int i = 0; i < 4; i++) { - emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + i), color); - color.reg_offset++; - } - } - - if (this->frag_color) - color.reg_offset -= 4; - - fs_inst *inst = emit(FS_OPCODE_FB_WRITE); - inst->target = target; - inst->base_mrf = 0; - inst->mlen = nr; - if (target == c->key.nr_color_regions - 1) - inst->eot = true; - inst->header_present = header_present; - } - - if (c->key.nr_color_regions == 0) { - if (c->key.alpha_test && (this->frag_color || this->frag_data)) { - /* If the alpha test is enabled but there's no color buffer, - * we still need to send alpha out the pipeline to our null - * renderbuffer. - */ - color.reg_offset += 3; - emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + 3), color); - } - - fs_inst *inst = emit(FS_OPCODE_FB_WRITE); - inst->base_mrf = 0; - inst->mlen = nr; - inst->eot = true; - inst->header_present = header_present; - } - - this->current_annotation = NULL; -} - -void -fs_visitor::generate_fb_write(fs_inst *inst) -{ - GLboolean eot = inst->eot; - struct brw_reg implied_header; - - /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied - * move, here's g1. - */ - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - - if (inst->header_present) { - if (intel->gen >= 6) { - brw_MOV(p, - brw_message_reg(inst->base_mrf), - brw_vec8_grf(0, 0)); - - if (inst->target > 0) { - /* Set the render target index for choosing BLEND_STATE. */ - brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 0, 2), - BRW_REGISTER_TYPE_UD), - brw_imm_ud(inst->target)); - } - - /* Clear viewport index, render target array index. */ - brw_AND(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 0, 0), - BRW_REGISTER_TYPE_UD), - retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0xf7ff)); - - implied_header = brw_null_reg(); - } else { - implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW); - } - - brw_MOV(p, - brw_message_reg(inst->base_mrf + 1), - brw_vec8_grf(1, 0)); - } else { - implied_header = brw_null_reg(); - } - - brw_pop_insn_state(p); - - brw_fb_WRITE(p, - 8, /* dispatch_width */ - retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), - inst->base_mrf, - implied_header, - inst->target, - inst->mlen, - 0, - eot, - inst->header_present); -} - -void -fs_visitor::generate_linterp(fs_inst *inst, - struct brw_reg dst, struct brw_reg *src) -{ - struct brw_reg delta_x = src[0]; - struct brw_reg delta_y = src[1]; - struct brw_reg interp = src[2]; - - if (brw->has_pln && - delta_y.nr == delta_x.nr + 1 && - (intel->gen >= 6 || (delta_x.nr & 1) == 0)) { - brw_PLN(p, dst, interp, delta_x); - } else { - brw_LINE(p, brw_null_reg(), interp, delta_x); - brw_MAC(p, dst, suboffset(interp, 1), delta_y); - } -} - -void -fs_visitor::generate_math(fs_inst *inst, - struct brw_reg dst, struct brw_reg *src) -{ - int op; - - switch (inst->opcode) { - case FS_OPCODE_RCP: - op = BRW_MATH_FUNCTION_INV; - break; - case FS_OPCODE_RSQ: - op = BRW_MATH_FUNCTION_RSQ; - break; - case FS_OPCODE_SQRT: - op = BRW_MATH_FUNCTION_SQRT; - break; - case FS_OPCODE_EXP2: - op = BRW_MATH_FUNCTION_EXP; - break; - case FS_OPCODE_LOG2: - op = BRW_MATH_FUNCTION_LOG; - break; - case FS_OPCODE_POW: - op = BRW_MATH_FUNCTION_POW; - break; - case FS_OPCODE_SIN: - op = BRW_MATH_FUNCTION_SIN; - break; - case FS_OPCODE_COS: - op = BRW_MATH_FUNCTION_COS; - break; - default: - assert(!"not reached: unknown math function"); - op = 0; - break; - } - - if (intel->gen >= 6) { - assert(inst->mlen == 0); - - if (inst->opcode == FS_OPCODE_POW) { - brw_math2(p, dst, op, src[0], src[1]); - } else { - brw_math(p, dst, - op, - inst->saturate ? BRW_MATH_SATURATE_SATURATE : - BRW_MATH_SATURATE_NONE, - 0, src[0], - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); - } - } else { - assert(inst->mlen >= 1); - - brw_math(p, dst, - op, - inst->saturate ? BRW_MATH_SATURATE_SATURATE : - BRW_MATH_SATURATE_NONE, - inst->base_mrf, src[0], - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); - } -} - -void -fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src) -{ - int msg_type = -1; - int rlen = 4; - uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; - - if (intel->gen >= 5) { - switch (inst->opcode) { - case FS_OPCODE_TEX: - if (inst->shadow_compare) { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE; - } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE; - } - break; - case FS_OPCODE_TXB: - if (inst->shadow_compare) { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE; - } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS; - } - break; - case FS_OPCODE_TXL: - if (inst->shadow_compare) { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE; - } else { - msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD; - } - break; - case FS_OPCODE_TXD: - assert(!"TXD isn't supported on gen5+ yet."); - break; - } - } else { - switch (inst->opcode) { - case FS_OPCODE_TEX: - /* Note that G45 and older determines shadow compare and dispatch width - * from message length for most messages. - */ - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; - if (inst->shadow_compare) { - assert(inst->mlen == 6); - } else { - assert(inst->mlen <= 4); - } - break; - case FS_OPCODE_TXB: - if (inst->shadow_compare) { - assert(inst->mlen == 6); - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE; - } else { - assert(inst->mlen == 9); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; - } - break; - case FS_OPCODE_TXL: - if (inst->shadow_compare) { - assert(inst->mlen == 6); - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE; - } else { - assert(inst->mlen == 9); - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD; - simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; - } - break; - case FS_OPCODE_TXD: - assert(!"TXD isn't supported on gen4 yet."); - break; - } - } - assert(msg_type != -1); - - if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) { - rlen = 8; - dst = vec16(dst); - } - - brw_SAMPLE(p, - retype(dst, BRW_REGISTER_TYPE_UW), - inst->base_mrf, - src, - SURF_INDEX_TEXTURE(inst->sampler), - inst->sampler, - WRITEMASK_XYZW, - msg_type, - rlen, - inst->mlen, - 0, - 1, - simd_mode); -} - - -/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input - * looking like: - * - * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br - * - * and we're trying to produce: - * - * DDX DDY - * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl) - * (ss0.tr - ss0.tl) (ss0.tr - ss0.br) - * (ss0.br - ss0.bl) (ss0.tl - ss0.bl) - * (ss0.br - ss0.bl) (ss0.tr - ss0.br) - * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl) - * (ss1.tr - ss1.tl) (ss1.tr - ss1.br) - * (ss1.br - ss1.bl) (ss1.tl - ss1.bl) - * (ss1.br - ss1.bl) (ss1.tr - ss1.br) - * - * and add another set of two more subspans if in 16-pixel dispatch mode. - * - * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result - * for each pair, and vertstride = 2 jumps us 2 elements after processing a - * pair. But for DDY, it's harder, as we want to produce the pairs swizzled - * between each other. We could probably do it like ddx and swizzle the right - * order later, but bail for now and just produce - * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4) - */ -void -fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src) -{ - struct brw_reg src0 = brw_reg(src.file, src.nr, 1, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_2, - BRW_WIDTH_2, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - struct brw_reg src1 = brw_reg(src.file, src.nr, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_2, - BRW_WIDTH_2, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - brw_ADD(p, dst, src0, negate(src1)); -} - -void -fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src) -{ - struct brw_reg src0 = brw_reg(src.file, src.nr, 0, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_4, - BRW_WIDTH_4, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - struct brw_reg src1 = brw_reg(src.file, src.nr, 2, - BRW_REGISTER_TYPE_F, - BRW_VERTICAL_STRIDE_4, - BRW_WIDTH_4, - BRW_HORIZONTAL_STRIDE_0, - BRW_SWIZZLE_XYZW, WRITEMASK_XYZW); - brw_ADD(p, dst, src0, negate(src1)); -} - -void -fs_visitor::generate_discard_not(fs_inst *inst, struct brw_reg mask) -{ - if (intel->gen >= 6) { - /* Gen6 no longer has the mask reg for us to just read the - * active channels from. However, cmp updates just the channels - * of the flag reg that are enabled, so we can get at the - * channel enables that way. In this step, make a reg of ones - * we'll compare to. - */ - brw_MOV(p, mask, brw_imm_ud(1)); - } else { - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_NOT(p, mask, brw_mask_reg(1)); /* IMASK */ - brw_pop_insn_state(p); - } -} - -void -fs_visitor::generate_discard_and(fs_inst *inst, struct brw_reg mask) -{ - if (intel->gen >= 6) { - struct brw_reg f0 = brw_flag_reg(); - struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, f0, brw_imm_uw(0xffff)); /* inactive channels undiscarded */ - brw_pop_insn_state(p); - - brw_CMP(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD), - BRW_CONDITIONAL_Z, mask, brw_imm_ud(0)); /* active channels fail test */ - /* Undo CMP's whacking of predication*/ - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_AND(p, g1, f0, g1); - brw_pop_insn_state(p); - } else { - struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); - - mask = brw_uw1_reg(mask.file, mask.nr, 0); - - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_AND(p, g0, mask, g0); - brw_pop_insn_state(p); - } -} - -void -fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src) -{ - assert(inst->mlen != 0); - - brw_MOV(p, - retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD), - retype(src, BRW_REGISTER_TYPE_UD)); - brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1, - inst->offset); -} - -void -fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst) -{ - assert(inst->mlen != 0); - - /* Clear any post destination dependencies that would be ignored by - * the block read. See the B-Spec for pre-gen5 send instruction. - * - * This could use a better solution, since texture sampling and - * math reads could potentially run into it as well -- anywhere - * that we have a SEND with a destination that is a register that - * was written but not read within the last N instructions (what's - * N? unsure). This is rare because of dead code elimination, but - * not impossible. - */ - if (intel->gen == 4 && !intel->is_g4x) - brw_MOV(p, brw_null_reg(), dst); - - brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1, - inst->offset); - - if (intel->gen == 4 && !intel->is_g4x) { - /* gen4 errata: destination from a send can't be used as a - * destination until it's been read. Just read it so we don't - * have to worry. - */ - brw_MOV(p, brw_null_reg(), dst); + inst->mlen = c->dispatch_width / 8; } -} + return inst; +} -void -fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst) +fs_inst * +fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1) { - assert(inst->mlen != 0); - - /* Clear any post destination dependencies that would be ignored by - * the block read. See the B-Spec for pre-gen5 send instruction. - * - * This could use a better solution, since texture sampling and - * math reads could potentially run into it as well -- anywhere - * that we have a SEND with a destination that is a register that - * was written but not read within the last N instructions (what's - * N? unsure). This is rare because of dead code elimination, but - * not impossible. - */ - if (intel->gen == 4 && !intel->is_g4x) - brw_MOV(p, brw_null_reg(), dst); + int base_mrf = 2; + fs_inst *inst; - brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf), - inst->offset, SURF_INDEX_FRAG_CONST_BUFFER); + assert(opcode == FS_OPCODE_POW); - if (intel->gen == 4 && !intel->is_g4x) { - /* gen4 errata: destination from a send can't be used as a - * destination until it's been read. Just read it so we don't - * have to worry. + if (intel->gen >= 6) { + /* Can't do hstride == 0 args to gen6 math, so expand it out. + * + * The hardware ignores source modifiers (negate and abs) on math + * instructions, so we also move to a temp to set those up. */ - brw_MOV(p, brw_null_reg(), dst); + if (src0.file == UNIFORM || src0.abs || src0.negate) { + fs_reg expanded = fs_reg(this, glsl_type::float_type); + emit(BRW_OPCODE_MOV, expanded, src0); + src0 = expanded; + } + + if (src1.file == UNIFORM || src1.abs || src1.negate) { + fs_reg expanded = fs_reg(this, glsl_type::float_type); + emit(BRW_OPCODE_MOV, expanded, src1); + src1 = expanded; + } + + inst = emit(opcode, dst, src0, src1); + } else { + emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1); + inst = emit(opcode, dst, src0, reg_null_f); + + inst->base_mrf = base_mrf; + inst->mlen = 2 * c->dispatch_width / 8; } + return inst; } /** @@ -2554,6 +599,9 @@ fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst) void fs_visitor::setup_paramvalues_refs() { + if (c->dispatch_width != 8) + return; + /* Set up the pointers to ParamValues now that that array is finalized. */ for (unsigned int i = 0; i < c->prog_data.nr_params; i++) { c->prog_data.param[i] = @@ -2565,8 +613,12 @@ fs_visitor::setup_paramvalues_refs() void fs_visitor::assign_curb_setup() { - c->prog_data.first_curbe_grf = c->nr_payload_regs; c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8; + if (c->dispatch_width == 8) { + c->prog_data.first_curbe_grf = c->nr_payload_regs; + } else { + c->prog_data.first_curbe_grf_16 = c->nr_payload_regs; + } /* Map the offsets in the UNIFORM file to fixed HW regs. */ foreach_iter(exec_list_iterator, iter, this->instructions) { @@ -2575,7 +627,7 @@ fs_visitor::assign_curb_setup() for (unsigned int i = 0; i < 3; i++) { if (inst->src[i].file == UNIFORM) { int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset; - struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf + + struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs + constant_nr / 8, constant_nr % 8); @@ -2597,7 +649,7 @@ fs_visitor::calculate_urb_setup() /* Figure out where each of the incoming setup attributes lands. */ if (intel->gen >= 6) { for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) { - if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) { + if (fp->Base.InputsRead & BITFIELD64_BIT(i)) { urb_setup[i] = urb_next++; } } @@ -2627,7 +679,7 @@ fs_visitor::calculate_urb_setup() void fs_visitor::assign_urb_setup() { - int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length; + int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length; /* Offset all the urb_setup[] index by the actual position of the * setup regs, now that the location of the constants has been chosen. @@ -2752,6 +804,11 @@ fs_visitor::setup_pull_constants() if (c->prog_data.nr_params <= max_uniform_components) return; + if (c->dispatch_width == 16) { + fail("Pull constants not supported in 16-wide\n"); + return; + } + /* Just demote the end of the list. We could probably do better * here, demoting things that are rarely used in the program first. */ @@ -2804,7 +861,6 @@ fs_visitor::calculate_live_intervals() int *use = ralloc_array(mem_ctx, int, num_vars); int loop_depth = 0; int loop_start = 0; - int bb_header_ip = 0; if (this->live_intervals_valid) return; @@ -2839,8 +895,7 @@ fs_visitor::calculate_live_intervals() if (inst->src[i].file == GRF && inst->src[i].reg != 0) { int reg = inst->src[i].reg; - if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 && - def[reg] >= bb_header_ip)) { + if (!loop_depth) { use[reg] = ip; } else { def[reg] = MIN2(loop_start, def[reg]); @@ -2856,8 +911,7 @@ fs_visitor::calculate_live_intervals() if (inst->dst.file == GRF && inst->dst.reg != 0) { int reg = inst->dst.reg; - if (!loop_depth || (this->virtual_grf_sizes[reg] == 1 && - !inst->predicated)) { + if (!loop_depth) { def[reg] = MIN2(def[reg], ip); } else { def[reg] = MIN2(def[reg], loop_start); @@ -2866,22 +920,6 @@ fs_visitor::calculate_live_intervals() } ip++; - - /* Set the basic block header IP. This is used for determining - * if a complete def of single-register virtual GRF in a loop - * dominates a use in the same basic block. It's a quick way to - * reduce the live interval range of most register used in a - * loop. - */ - if (inst->opcode == BRW_OPCODE_IF || - inst->opcode == BRW_OPCODE_ELSE || - inst->opcode == BRW_OPCODE_ENDIF || - inst->opcode == BRW_OPCODE_DO || - inst->opcode == BRW_OPCODE_WHILE || - inst->opcode == BRW_OPCODE_BREAK || - inst->opcode == BRW_OPCODE_CONTINUE) { - bb_header_ip = ip; - } } ralloc_free(this->virtual_grf_def); @@ -2913,7 +951,9 @@ fs_visitor::propagate_constants() if (inst->opcode != BRW_OPCODE_MOV || inst->predicated || inst->dst.file != GRF || inst->src[0].file != IMM || - inst->dst.type != inst->src[0].type) + inst->dst.type != inst->src[0].type || + (c->dispatch_width == 16 && + (inst->force_uncompressed || inst->force_sechalf))) continue; /* Don't bother with cases where we should have had the @@ -2967,12 +1007,45 @@ fs_visitor::propagate_constants() progress = true; } break; + case BRW_OPCODE_CMP: + if (i == 1) { + scan_inst->src[i] = inst->src[0]; + progress = true; + } else if (i == 0 && scan_inst->src[1].file != IMM) { + uint32_t new_cmod; + + new_cmod = brw_swap_cmod(scan_inst->conditional_mod); + if (new_cmod != ~0u) { + /* Fit this constant in by swapping the operands and + * flipping the test + */ + scan_inst->src[0] = scan_inst->src[1]; + scan_inst->src[1] = inst->src[0]; + scan_inst->conditional_mod = new_cmod; + progress = true; + } + } + break; + case BRW_OPCODE_SEL: if (i == 1) { scan_inst->src[i] = inst->src[0]; progress = true; + } else if (i == 0 && scan_inst->src[1].file != IMM) { + scan_inst->src[0] = scan_inst->src[1]; + scan_inst->src[1] = inst->src[0]; + + /* If this was predicated, flipping operands means + * we also need to flip the predicate. + */ + if (scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) { + scan_inst->predicate_inverse = + !scan_inst->predicate_inverse; + } + progress = true; } + break; } } @@ -3091,7 +1164,7 @@ fs_visitor::register_coalesce() /* The gen6 MATH instruction can't handle source modifiers, so avoid * coalescing those for now. We should do something more specific. */ - if (intel->gen == 6 && scan_inst->is_math() && has_source_modifiers) { + if (intel->gen >= 6 && scan_inst->is_math() && has_source_modifiers) { interfered = true; break; } @@ -3152,6 +1225,20 @@ fs_visitor::compute_to_mrf() inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1) continue; + /* Work out which hardware MRF registers are written by this + * instruction. + */ + int mrf_low = inst->dst.hw_reg & ~BRW_MRF_COMPR4; + int mrf_high; + if (inst->dst.hw_reg & BRW_MRF_COMPR4) { + mrf_high = mrf_low + 4; + } else if (c->dispatch_width == 16 && + (!inst->force_uncompressed && !inst->force_sechalf)) { + mrf_high = mrf_low + 1; + } else { + mrf_high = mrf_low; + } + /* Can't compute-to-MRF this GRF if someone else was going to * read it later. */ @@ -3179,11 +1266,21 @@ fs_visitor::compute_to_mrf() } /* If it's predicated, it (probably) didn't populate all - * the channels. + * the channels. We might be able to rewrite everything + * that writes that reg, but it would require smarter + * tracking to delay the rewriting until complete success. */ if (scan_inst->predicated) break; + /* If it's half of register setup and not the same half as + * our MOV we're trying to remove, bail for now. + */ + if (scan_inst->force_uncompressed != inst->force_uncompressed || + scan_inst->force_sechalf != inst->force_sechalf) { + break; + } + /* SEND instructions can't have MRF as a destination. */ if (scan_inst->mlen) break; @@ -3233,12 +1330,29 @@ fs_visitor::compute_to_mrf() if (interfered) break; - if (scan_inst->dst.file == MRF && - scan_inst->dst.hw_reg == inst->dst.hw_reg) { - /* Somebody else wrote our MRF here, so we can't can't + if (scan_inst->dst.file == MRF) { + /* If somebody else writes our MRF here, we can't * compute-to-MRF before that. */ - break; + int scan_mrf_low = scan_inst->dst.hw_reg & ~BRW_MRF_COMPR4; + int scan_mrf_high; + + if (scan_inst->dst.hw_reg & BRW_MRF_COMPR4) { + scan_mrf_high = scan_mrf_low + 4; + } else if (c->dispatch_width == 16 && + (!scan_inst->force_uncompressed && + !scan_inst->force_sechalf)) { + scan_mrf_high = scan_mrf_low + 1; + } else { + scan_mrf_high = scan_mrf_low; + } + + if (mrf_low == scan_mrf_low || + mrf_low == scan_mrf_high || + mrf_high == scan_mrf_low || + mrf_high == scan_mrf_high) { + break; + } } if (scan_inst->mlen > 0) { @@ -3247,8 +1361,12 @@ fs_visitor::compute_to_mrf() * scan_inst->mlen - 1. Don't go pushing our MRF write up * above it. */ - if (inst->dst.hw_reg >= scan_inst->base_mrf && - inst->dst.hw_reg < scan_inst->base_mrf + scan_inst->mlen) { + if (mrf_low >= scan_inst->base_mrf && + mrf_low < scan_inst->base_mrf + scan_inst->mlen) { + break; + } + if (mrf_high >= scan_inst->base_mrf && + mrf_high < scan_inst->base_mrf + scan_inst->mlen) { break; } } @@ -3268,6 +1386,10 @@ fs_visitor::remove_duplicate_mrf_writes() fs_inst *last_mrf_move[16]; bool progress = false; + /* Need to update the MRF tracking for compressed instructions. */ + if (c->dispatch_width == 16) + return false; + memset(last_mrf_move, 0, sizeof(last_mrf_move)); foreach_iter(exec_list_iterator, iter, this->instructions) { @@ -3347,453 +1469,241 @@ fs_visitor::virtual_grf_interferes(int a, int b) (this->virtual_grf_use[b] != -1 || this->virtual_grf_def[b] == MAX_INSTRUCTION)); - return start < end; -} - -static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg) -{ - struct brw_reg brw_reg; - - switch (reg->file) { - case GRF: - case ARF: - case MRF: - if (reg->smear == -1) { - brw_reg = brw_vec8_reg(reg->file, - reg->hw_reg, 0); - } else { - brw_reg = brw_vec1_reg(reg->file, - reg->hw_reg, reg->smear); - } - brw_reg = retype(brw_reg, reg->type); - break; - case IMM: - switch (reg->type) { - case BRW_REGISTER_TYPE_F: - brw_reg = brw_imm_f(reg->imm.f); - break; - case BRW_REGISTER_TYPE_D: - brw_reg = brw_imm_d(reg->imm.i); - break; - case BRW_REGISTER_TYPE_UD: - brw_reg = brw_imm_ud(reg->imm.u); - break; - default: - assert(!"not reached"); - brw_reg = brw_null_reg(); - break; - } - break; - case FIXED_HW_REG: - brw_reg = reg->fixed_hw_reg; - break; - case BAD_FILE: - /* Probably unused. */ - brw_reg = brw_null_reg(); - break; - case UNIFORM: - assert(!"not reached"); - brw_reg = brw_null_reg(); - break; - default: - assert(!"not reached"); - brw_reg = brw_null_reg(); - break; + /* If the register is used to store 16 values of less than float + * size (only the case for pixel_[xy]), then we can't allocate + * another dword-sized thing to that register that would be used in + * the same instruction. This is because when the GPU decodes (for + * example): + * + * (declare (in ) vec4 gl_FragCoord@0x97766a0) + * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr }; + * + * it's actually processed as: + * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 }; + * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf }; + * + * so our second half values in g6 got overwritten in the first + * half. + */ + if (c->dispatch_width == 16 && (this->pixel_x.reg == a || + this->pixel_x.reg == b || + this->pixel_y.reg == a || + this->pixel_y.reg == b)) { + return start <= end; } - if (reg->abs) - brw_reg = brw_abs(brw_reg); - if (reg->negate) - brw_reg = negate(brw_reg); - return brw_reg; + return start < end; } -void -fs_visitor::generate_code() +bool +fs_visitor::run() { - int last_native_inst = 0; - const char *last_annotation_string = NULL; - ir_instruction *last_annotation_ir = NULL; - - int if_stack_array_size = 16; - int loop_stack_array_size = 16; - int if_stack_depth = 0, loop_stack_depth = 0; - brw_instruction **if_stack = - rzalloc_array(this->mem_ctx, brw_instruction *, if_stack_array_size); - brw_instruction **loop_stack = - rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size); - int *if_depth_in_loop = - rzalloc_array(this->mem_ctx, int, loop_stack_array_size); - - - if (unlikely(INTEL_DEBUG & DEBUG_WM)) { - printf("Native code for fragment shader %d:\n", - ctx->Shader.CurrentFragmentProgram->Name); - } + uint32_t prog_offset_16 = 0; + uint32_t orig_nr_params = c->prog_data.nr_params; - foreach_iter(exec_list_iterator, iter, this->instructions) { - fs_inst *inst = (fs_inst *)iter.get(); - struct brw_reg src[3], dst; - - if (unlikely(INTEL_DEBUG & DEBUG_WM)) { - if (last_annotation_ir != inst->ir) { - last_annotation_ir = inst->ir; - if (last_annotation_ir) { - printf(" "); - last_annotation_ir->print(); - printf("\n"); - } - } - if (last_annotation_string != inst->annotation) { - last_annotation_string = inst->annotation; - if (last_annotation_string) - printf(" %s\n", last_annotation_string); - } - } + brw_wm_payload_setup(brw, c); - for (unsigned int i = 0; i < 3; i++) { - src[i] = brw_reg_from_fs_reg(&inst->src[i]); + if (c->dispatch_width == 16) { + /* align to 64 byte boundary. */ + while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) { + brw_NOP(p); } - dst = brw_reg_from_fs_reg(&inst->dst); - - brw_set_conditionalmod(p, inst->conditional_mod); - brw_set_predicate_control(p, inst->predicated); - brw_set_saturate(p, inst->saturate); - - switch (inst->opcode) { - case BRW_OPCODE_MOV: - brw_MOV(p, dst, src[0]); - break; - case BRW_OPCODE_ADD: - brw_ADD(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_MUL: - brw_MUL(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_FRC: - brw_FRC(p, dst, src[0]); - break; - case BRW_OPCODE_RNDD: - brw_RNDD(p, dst, src[0]); - break; - case BRW_OPCODE_RNDE: - brw_RNDE(p, dst, src[0]); - break; - case BRW_OPCODE_RNDZ: - brw_RNDZ(p, dst, src[0]); - break; + /* Save off the start of this 16-wide program in case we succeed. */ + prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction); - case BRW_OPCODE_AND: - brw_AND(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_OR: - brw_OR(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_XOR: - brw_XOR(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_NOT: - brw_NOT(p, dst, src[0]); - break; - case BRW_OPCODE_ASR: - brw_ASR(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_SHR: - brw_SHR(p, dst, src[0], src[1]); - break; - case BRW_OPCODE_SHL: - brw_SHL(p, dst, src[0], src[1]); - break; + brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); + } - case BRW_OPCODE_CMP: - brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]); - break; - case BRW_OPCODE_SEL: - brw_SEL(p, dst, src[0], src[1]); - break; + if (0) { + emit_dummy_fs(); + } else { + calculate_urb_setup(); + if (intel->gen < 6) + emit_interpolation_setup_gen4(); + else + emit_interpolation_setup_gen6(); - case BRW_OPCODE_IF: - if (inst->src[0].file != BAD_FILE) { - assert(intel->gen >= 6); - if_stack[if_stack_depth] = gen6_IF(p, inst->conditional_mod, src[0], src[1]); - } else { - if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8); - } - if_depth_in_loop[loop_stack_depth]++; - if_stack_depth++; - if (if_stack_array_size <= if_stack_depth) { - if_stack_array_size *= 2; - if_stack = reralloc(this->mem_ctx, if_stack, brw_instruction *, - if_stack_array_size); - } - break; + /* Generate FS IR for main(). (the visitor only descends into + * functions called "main"). + */ + foreach_iter(exec_list_iterator, iter, *shader->ir) { + ir_instruction *ir = (ir_instruction *)iter.get(); + base_ir = ir; + this->result = reg_undef; + ir->accept(this); + } - case BRW_OPCODE_ELSE: - if_stack[if_stack_depth - 1] = - brw_ELSE(p, if_stack[if_stack_depth - 1]); - break; - case BRW_OPCODE_ENDIF: - if_stack_depth--; - brw_ENDIF(p , if_stack[if_stack_depth]); - if_depth_in_loop[loop_stack_depth]--; - break; + emit_fb_writes(); - case BRW_OPCODE_DO: - loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8); - if (loop_stack_array_size <= loop_stack_depth) { - loop_stack_array_size *= 2; - loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *, - loop_stack_array_size); - if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int, - loop_stack_array_size); - } - if_depth_in_loop[loop_stack_depth] = 0; - break; + split_virtual_grfs(); - case BRW_OPCODE_BREAK: - brw_BREAK(p, if_depth_in_loop[loop_stack_depth]); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - break; - case BRW_OPCODE_CONTINUE: - /* FINISHME: We need to write the loop instruction support still. */ - if (intel->gen >= 6) - gen6_CONT(p, loop_stack[loop_stack_depth - 1]); - else - brw_CONT(p, if_depth_in_loop[loop_stack_depth]); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); - break; + setup_paramvalues_refs(); + setup_pull_constants(); - case BRW_OPCODE_WHILE: { - struct brw_instruction *inst0, *inst1; - GLuint br = 1; - - if (intel->gen >= 5) - br = 2; - - assert(loop_stack_depth > 0); - loop_stack_depth--; - inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]); - if (intel->gen < 6) { - /* patch all the BREAK/CONT instructions from last BGNLOOP */ - while (inst0 > loop_stack[loop_stack_depth]) { - inst0--; - if (inst0->header.opcode == BRW_OPCODE_BREAK && - inst0->bits3.if_else.jump_count == 0) { - inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1); - } - else if (inst0->header.opcode == BRW_OPCODE_CONTINUE && - inst0->bits3.if_else.jump_count == 0) { - inst0->bits3.if_else.jump_count = br * (inst1 - inst0); - } - } - } - } - break; + bool progress; + do { + progress = false; - case FS_OPCODE_RCP: - case FS_OPCODE_RSQ: - case FS_OPCODE_SQRT: - case FS_OPCODE_EXP2: - case FS_OPCODE_LOG2: - case FS_OPCODE_POW: - case FS_OPCODE_SIN: - case FS_OPCODE_COS: - generate_math(inst, dst, src); - break; - case FS_OPCODE_CINTERP: - brw_MOV(p, dst, src[0]); - break; - case FS_OPCODE_LINTERP: - generate_linterp(inst, dst, src); - break; - case FS_OPCODE_TEX: - case FS_OPCODE_TXB: - case FS_OPCODE_TXD: - case FS_OPCODE_TXL: - generate_tex(inst, dst, src[0]); - break; - case FS_OPCODE_DISCARD_NOT: - generate_discard_not(inst, dst); - break; - case FS_OPCODE_DISCARD_AND: - generate_discard_and(inst, src[0]); - break; - case FS_OPCODE_DDX: - generate_ddx(inst, dst, src[0]); - break; - case FS_OPCODE_DDY: - generate_ddy(inst, dst, src[0]); - break; + progress = remove_duplicate_mrf_writes() || progress; - case FS_OPCODE_SPILL: - generate_spill(inst, src[0]); - break; + progress = propagate_constants() || progress; + progress = register_coalesce() || progress; + progress = compute_to_mrf() || progress; + progress = dead_code_eliminate() || progress; + } while (progress); - case FS_OPCODE_UNSPILL: - generate_unspill(inst, dst); - break; + schedule_instructions(); - case FS_OPCODE_PULL_CONSTANT_LOAD: - generate_pull_constant_load(inst, dst); - break; + assign_curb_setup(); + assign_urb_setup(); - case FS_OPCODE_FB_WRITE: - generate_fb_write(inst); - break; - default: - if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { - _mesa_problem(ctx, "Unsupported opcode `%s' in FS", - brw_opcodes[inst->opcode].name); - } else { - _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); + if (0) { + /* Debug of register spilling: Go spill everything. */ + int virtual_grf_count = virtual_grf_next; + for (int i = 1; i < virtual_grf_count; i++) { + spill_reg(i); } - fail("unsupported opcode in FS\n"); } - if (unlikely(INTEL_DEBUG & DEBUG_WM)) { - for (unsigned int i = last_native_inst; i < p->nr_insn; i++) { - if (0) { - printf("0x%08x 0x%08x 0x%08x 0x%08x ", - ((uint32_t *)&p->store[i])[3], - ((uint32_t *)&p->store[i])[2], - ((uint32_t *)&p->store[i])[1], - ((uint32_t *)&p->store[i])[0]); - } - brw_disasm(stdout, &p->store[i], intel->gen); + if (0) + assign_regs_trivial(); + else { + while (!assign_regs()) { + if (failed) + break; } } - - last_native_inst = p->nr_insn; } + assert(force_uncompressed_stack == 0); + assert(force_sechalf_stack == 0); - ralloc_free(if_stack); - ralloc_free(loop_stack); - ralloc_free(if_depth_in_loop); + if (failed) + return false; - brw_set_uip_jip(p); + generate_code(); - /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS - * emit issues, it doesn't get the jump distances into the output, - * which is often something we want to debug. So this is here in - * case you're doing that. - */ - if (0) { - if (unlikely(INTEL_DEBUG & DEBUG_WM)) { - for (unsigned int i = 0; i < p->nr_insn; i++) { - printf("0x%08x 0x%08x 0x%08x 0x%08x ", - ((uint32_t *)&p->store[i])[3], - ((uint32_t *)&p->store[i])[2], - ((uint32_t *)&p->store[i])[1], - ((uint32_t *)&p->store[i])[0]); - brw_disasm(stdout, &p->store[i], intel->gen); - } - } + if (c->dispatch_width == 8) { + c->prog_data.reg_blocks = brw_register_blocks(grf_used); + } else { + c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used); + c->prog_data.prog_offset_16 = prog_offset_16; + + /* Make sure we didn't try to sneak in an extra uniform */ + assert(orig_nr_params == c->prog_data.nr_params); } + + return !failed; } -GLboolean -brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) +bool +brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c, + struct gl_shader_program *prog) { struct intel_context *intel = &brw->intel; - struct gl_context *ctx = &intel->ctx; - struct gl_shader_program *prog = ctx->Shader.CurrentFragmentProgram; if (!prog) - return GL_FALSE; + return false; struct brw_shader *shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT]; if (!shader) - return GL_FALSE; - - /* We always use 8-wide mode, at least for now. For one, flow - * control only works in 8-wide. Also, when we're fragment shader - * bound, we're almost always under register pressure as well, so - * 8-wide would save us from the performance cliff of spilling - * regs. - */ - c->dispatch_width = 8; + return false; if (unlikely(INTEL_DEBUG & DEBUG_WM)) { printf("GLSL IR for native fragment shader %d:\n", prog->Name); _mesa_print_ir(shader->ir, NULL); - printf("\n"); + printf("\n\n"); } /* Now the main event: Visit the shader IR and generate our FS IR for it. */ - fs_visitor v(c, shader); + c->dispatch_width = 8; - if (0) { - v.emit_dummy_fs(); - } else { - v.calculate_urb_setup(); - if (intel->gen < 6) - v.emit_interpolation_setup_gen4(); - else - v.emit_interpolation_setup_gen6(); + fs_visitor v(c, prog, shader); + if (!v.run()) { + prog->LinkStatus = GL_FALSE; + prog->InfoLog = ralloc_strdup(prog, v.fail_msg); - /* Generate FS IR for main(). (the visitor only descends into - * functions called "main"). - */ - foreach_iter(exec_list_iterator, iter, *shader->ir) { - ir_instruction *ir = (ir_instruction *)iter.get(); - v.base_ir = ir; - ir->accept(&v); - } + return false; + } - v.emit_fb_writes(); + if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) { + c->dispatch_width = 16; + fs_visitor v2(c, prog, shader); + v2.import_uniforms(v.variable_ht); + v2.run(); + } - v.split_virtual_grfs(); + c->prog_data.dispatch_width = 8; - v.setup_paramvalues_refs(); - v.setup_pull_constants(); + return true; +} - bool progress; - do { - progress = false; +bool +brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog) +{ + struct brw_context *brw = brw_context(ctx); + struct brw_wm_prog_key key; + struct gl_fragment_program *fp = prog->FragmentProgram; + struct brw_fragment_program *bfp = brw_fragment_program(fp); - progress = v.remove_duplicate_mrf_writes() || progress; + if (!fp) + return true; - progress = v.propagate_constants() || progress; - progress = v.register_coalesce() || progress; - progress = v.compute_to_mrf() || progress; - progress = v.dead_code_eliminate() || progress; - } while (progress); + memset(&key, 0, sizeof(key)); - v.schedule_instructions(); + if (fp->UsesKill) + key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT; - v.assign_curb_setup(); - v.assign_urb_setup(); + if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) + key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT; - if (0) { - /* Debug of register spilling: Go spill everything. */ - int virtual_grf_count = v.virtual_grf_next; - for (int i = 1; i < virtual_grf_count; i++) { - v.spill_reg(i); - } - } + /* Just assume depth testing. */ + key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT; + key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT; - if (0) - v.assign_regs_trivial(); - else { - while (!v.assign_regs()) { - if (v.failed) - break; - } - } + key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS); + for (int i = 0; i < FRAG_ATTRIB_MAX; i++) { + int vp_index = -1; + + if (!(fp->Base.InputsRead & BITFIELD64_BIT(i))) + continue; + + key.proj_attrib_mask |= 1 << i; + + if (i <= FRAG_ATTRIB_TEX7) + vp_index = i; + else if (i >= FRAG_ATTRIB_VAR0) + vp_index = i - FRAG_ATTRIB_VAR0 + VERT_RESULT_VAR0; + + if (vp_index >= 0) + key.vp_outputs_written |= BITFIELD64_BIT(vp_index); + } + + key.clamp_fragment_color = true; + + for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) { + /* FINISHME: depth compares might use (0,0,0,W) for example */ + key.tex_swizzles[i] = SWIZZLE_XYZW; + } + + if (fp->Base.InputsRead & FRAG_BIT_WPOS) { + key.drawable_height = ctx->DrawBuffer->Height; + key.render_to_fbo = ctx->DrawBuffer->Name != 0; } - if (!v.failed) - v.generate_code(); + key.nr_color_regions = 1; + + key.program_string_id = bfp->id; - assert(!v.failed); /* FINISHME: Cleanly fail, tested at link time, etc. */ + uint32_t old_prog_offset = brw->wm.prog_offset; + struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data; - if (v.failed) - return GL_FALSE; + bool success = do_wm_prog(brw, prog, bfp, &key); - c->prog_data.total_grf = v.grf_used; + brw->wm.prog_offset = old_prog_offset; + brw->wm.prog_data = old_prog_data; - return GL_TRUE; + return success; }