X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_fs.h;h=3769d9fbfd0f40d825e72849bfa5be93d0f17254;hb=a9f31a032b0a1068a4e2ceed9ed4680ecf13e28b;hp=58bb3ae1ce006c830185dcd84f5eefc984225e60;hpb=7ff457b93028d1884c7952080edd919008edf141;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 58bb3ae1ce0..3769d9fbfd0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -28,6 +28,8 @@ #pragma once #include "brw_shader.h" +#include "brw_ir_fs.h" +#include "brw_fs_builder.h" extern "C" { @@ -40,19 +42,16 @@ extern "C" { #include "program/prog_print.h" #include "program/prog_optimize.h" #include "util/register_allocate.h" -#include "program/sampler.h" #include "program/hash_table.h" #include "brw_context.h" #include "brw_eu.h" #include "brw_wm.h" -#include "brw_shader.h" #include "intel_asm_annotation.h" } #include "glsl/glsl_types.h" #include "glsl/ir.h" - -#define MAX_SAMPLER_MESSAGE_SIZE 11 -#define MAX_VGRF_SIZE 16 +#include "glsl/nir/nir.h" +#include "program/sampler.h" struct bblock_t; namespace { @@ -63,376 +62,87 @@ namespace brw { class fs_live_variables; } -class fs_inst; -class fs_visitor; - -class fs_reg : public backend_reg { -public: - DECLARE_RALLOC_CXX_OPERATORS(fs_reg) - - void init(); - - fs_reg(); - explicit fs_reg(float f); - explicit fs_reg(int32_t i); - explicit fs_reg(uint32_t u); - explicit fs_reg(uint8_t vf[4]); - explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3); - fs_reg(struct brw_reg fixed_hw_reg); - fs_reg(enum register_file file, int reg); - fs_reg(enum register_file file, int reg, enum brw_reg_type type); - fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width); - fs_reg(fs_visitor *v, const struct glsl_type *type); - - bool equals(const fs_reg &r) const; - bool is_contiguous() const; - - /** Smear a channel of the reg to all channels. */ - fs_reg &set_smear(unsigned subreg); - - /** - * Offset in bytes from the start of the register. Values up to a - * backend_reg::reg_offset unit are valid. - */ - int subreg_offset; - - fs_reg *reladdr; - - /** - * The register width. This indicates how many hardware values are - * represented by each virtual value. Valid values are 1, 8, or 16. - * For immediate values, this is 1. Most of the rest of the time, it - * will be equal to the dispatch width. - */ - uint8_t width; - - /** - * Returns the effective register width when used as a source in the - * given instruction. Registers such as uniforms and immediates - * effectively take on the width of the instruction in which they are - * used. - */ - uint8_t effective_width; - - /** Register region horizontal stride */ - uint8_t stride; -}; - -static inline fs_reg -negate(fs_reg reg) -{ - assert(reg.file != HW_REG && reg.file != IMM); - reg.negate = !reg.negate; - return reg; -} - -static inline fs_reg -retype(fs_reg reg, enum brw_reg_type type) -{ - reg.fixed_hw_reg.type = reg.type = type; - return reg; -} - -static inline fs_reg -byte_offset(fs_reg reg, unsigned delta) -{ - switch (reg.file) { - case BAD_FILE: - break; - case GRF: - case ATTR: - reg.reg_offset += delta / 32; - break; - case MRF: - reg.reg += delta / 32; - break; - default: - assert(delta == 0); - } - reg.subreg_offset += delta % 32; - return reg; -} - -static inline fs_reg -horiz_offset(fs_reg reg, unsigned delta) -{ - switch (reg.file) { - case BAD_FILE: - case UNIFORM: - case IMM: - /* These only have a single component that is implicitly splatted. A - * horizontal offset should be a harmless no-op. - */ - break; - case GRF: - case MRF: - case ATTR: - return byte_offset(reg, delta * reg.stride * type_sz(reg.type)); - default: - assert(delta == 0); - } - return reg; -} - static inline fs_reg -offset(fs_reg reg, unsigned delta) +offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta) { - assert(reg.stride > 0); switch (reg.file) { case BAD_FILE: break; case GRF: case MRF: + case HW_REG: case ATTR: - return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type)); + return byte_offset(reg, + delta * reg.component_size(bld.dispatch_width())); case UNIFORM: reg.reg_offset += delta; break; - default: + case IMM: assert(delta == 0); } return reg; } -static inline fs_reg -component(fs_reg reg, unsigned idx) -{ - assert(reg.subreg_offset == 0); - assert(idx < reg.width); - reg.subreg_offset = idx * type_sz(reg.type); - reg.width = 1; - return reg; -} - -/** - * Get either of the 8-component halves of a 16-component register. - * - * Note: this also works if \c reg represents a SIMD16 pair of registers. - */ -static inline fs_reg -half(fs_reg reg, unsigned idx) -{ - assert(idx < 2); - - if (reg.file == UNIFORM) - return reg; - - assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM)); - assert(reg.width == 16); - reg.width = 8; - return horiz_offset(reg, 8 * idx); -} - -static const fs_reg reg_undef; - -class fs_inst : public backend_instruction { - fs_inst &operator=(const fs_inst &); - - void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst, - fs_reg *src, int sources); - -public: - DECLARE_RALLOC_CXX_OPERATORS(fs_inst) - - fs_inst(); - fs_inst(enum opcode opcode, uint8_t exec_size); - fs_inst(enum opcode opcode, const fs_reg &dst); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0); - fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1); - fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0, - const fs_reg &src1); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1, const fs_reg &src2); - fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0, - const fs_reg &src1, const fs_reg &src2); - fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources); - fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, - fs_reg src[], int sources); - fs_inst(const fs_inst &that); - - void resize_sources(uint8_t num_sources); - - bool equals(fs_inst *inst) const; - bool overwrites_reg(const fs_reg ®) const; - bool is_send_from_grf() const; - bool is_partial_write() const; - int regs_read(fs_visitor *v, int arg) const; - bool can_do_source_mods(struct brw_context *brw); - - bool reads_flag() const; - bool writes_flag() const; - - fs_reg dst; - fs_reg *src; - - uint8_t sources; /**< Number of fs_reg sources. */ - - /** - * Execution size of the instruction. This is used by the generator to - * generate the correct binary for the given fs_inst. Current valid - * values are 1, 8, 16. - */ - uint8_t exec_size; - - /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional - * mod and predication. - */ - uint8_t flag_subreg; - - uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */ - bool eot:1; - bool force_uncompressed:1; - bool force_sechalf:1; - bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */ -}; - /** * The fragment shader front-end. * * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR. */ -class fs_visitor : public backend_visitor +class fs_visitor : public backend_shader { public: - const fs_reg reg_null_f; - const fs_reg reg_null_d; - const fs_reg reg_null_ud; - - fs_visitor(struct brw_context *brw, - void *mem_ctx, - const struct brw_wm_prog_key *key, - struct brw_wm_prog_data *prog_data, - struct gl_shader_program *shader_prog, - struct gl_fragment_program *fp, - unsigned dispatch_width); - - fs_visitor(struct brw_context *brw, + fs_visitor(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, - const struct brw_vs_prog_key *key, - struct brw_vs_prog_data *prog_data, + gl_shader_stage stage, + const void *key, + struct brw_stage_prog_data *prog_data, struct gl_shader_program *shader_prog, - struct gl_vertex_program *cp, - unsigned dispatch_width); + struct gl_program *prog, + unsigned dispatch_width, + int shader_time_index); ~fs_visitor(); - void init(); - fs_reg *variable_storage(ir_variable *var); - int virtual_grf_alloc(int size); + fs_reg vgrf(const glsl_type *const type); void import_uniforms(fs_visitor *v); - void setup_uniform_clipplane_values(); - void compute_clip_distance(); - - void visit(ir_variable *ir); - void visit(ir_assignment *ir); - void visit(ir_dereference_variable *ir); - void visit(ir_dereference_record *ir); - void visit(ir_dereference_array *ir); - void visit(ir_expression *ir); - void visit(ir_texture *ir); - void visit(ir_if *ir); - void visit(ir_constant *ir); - void visit(ir_swizzle *ir); - void visit(ir_return *ir); - void visit(ir_loop *ir); - void visit(ir_loop_jump *ir); - void visit(ir_discard *ir); - void visit(ir_call *ir); - void visit(ir_function *ir); - void visit(ir_function_signature *ir); - void visit(ir_emit_vertex *); - void visit(ir_end_primitive *); + void setup_uniform_clipplane_values(gl_clip_plane *clip_planes); + void compute_clip_distance(gl_clip_plane *clip_planes); uint32_t gather_channel(int orig_chan, uint32_t sampler); void swizzle_result(ir_texture_opcode op, int dest_components, fs_reg orig_val, uint32_t sampler); - fs_inst *emit(fs_inst *inst); - void emit(exec_list list); - - fs_inst *emit(enum opcode opcode); - fs_inst *emit(enum opcode opcode, const fs_reg &dst); - fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0); - fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0, - const fs_reg &src1); - fs_inst *emit(enum opcode opcode, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1, const fs_reg &src2); - fs_inst *emit(enum opcode opcode, const fs_reg &dst, - fs_reg src[], int sources); - - fs_inst *MOV(const fs_reg &dst, const fs_reg &src); - fs_inst *NOT(const fs_reg &dst, const fs_reg &src); - fs_inst *RNDD(const fs_reg &dst, const fs_reg &src); - fs_inst *RNDE(const fs_reg &dst, const fs_reg &src); - fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src); - fs_inst *FRC(const fs_reg &dst, const fs_reg &src); - fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *IF(enum brw_predicate predicate); - fs_inst *IF(const fs_reg &src0, const fs_reg &src1, - enum brw_conditional_mod condition); - fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1, - enum brw_conditional_mod condition); - fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y, - const fs_reg &x); - fs_inst *DEP_RESOLVE_MOV(int grf); - fs_inst *BFREV(const fs_reg &dst, const fs_reg &value); - fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset, - const fs_reg &value); - fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset); - fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst, - const fs_reg &insert, const fs_reg &base); - fs_inst *FBH(const fs_reg &dst, const fs_reg &value); - fs_inst *FBL(const fs_reg &dst, const fs_reg &value); - fs_inst *CBIT(const fs_reg &dst, const fs_reg &value); - fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b, - const fs_reg &a); - fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1); - int type_size(const struct glsl_type *type); fs_inst *get_instruction_generating_reg(fs_inst *start, fs_inst *end, const fs_reg ®); - fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources); - - exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst, - const fs_reg &surf_index, - const fs_reg &varying_offset, - uint32_t const_offset); + void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld, + const fs_reg &dst, + const fs_reg &surf_index, + const fs_reg &varying_offset, + uint32_t const_offset); + void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf); - bool run_fs(); - bool run_vs(); + bool run_fs(bool do_rep_send); + bool run_vs(gl_clip_plane *clip_planes); + bool run_cs(); void optimize(); void allocate_registers(); void assign_binding_table_offsets(); void setup_payload_gen4(); void setup_payload_gen6(); void setup_vs_payload(); + void setup_cs_payload(); + void fixup_3src_null_dest(); void assign_curb_setup(); void calculate_urb_setup(); void assign_urb_setup(); void assign_vs_urb_setup(); bool assign_regs(bool allow_spilling); void assign_regs_trivial(); - void get_used_mrfs(bool *mrf_used); void setup_payload_interference(struct ra_graph *g, int payload_reg_count, int first_payload_node); - void setup_mrf_hack_interference(struct ra_graph *g, - int first_mrf_hack_node); int choose_spill_reg(struct ra_graph *g); void spill_reg(int spill_reg); void split_virtual_grfs(); @@ -444,6 +154,7 @@ public: void calculate_live_intervals(); void calculate_register_pressure(); bool opt_algebraic(); + bool opt_redundant_discard_jumps(); bool opt_cse(); bool opt_cse_local(bblock_t *block); bool opt_copy_propagate(); @@ -454,8 +165,11 @@ public: bool opt_register_renaming(); bool register_coalesce(); bool compute_to_mrf(); + bool eliminate_find_live_channel(); bool dead_code_eliminate(); bool remove_duplicate_mrf_writes(); + + bool opt_sampler_eot(); bool virtual_grf_interferes(int a, int b); void schedule_instructions(instruction_scheduler_mode mode); void insert_gen4_send_dependency_workarounds(); @@ -465,31 +179,44 @@ public: fs_inst *inst); void vfail(const char *msg, va_list args); void fail(const char *msg, ...); - void no16(const char *msg, ...); + void no16(const char *msg); void lower_uniform_pull_constant_loads(); bool lower_load_payload(); + bool lower_logical_sends(); + bool lower_integer_multiplication(); + bool lower_simd_width(); + bool opt_combine_constants(); void emit_dummy_fs(); void emit_repclear_shader(); - fs_reg *emit_fragcoord_interpolation(ir_variable *ir); + fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer, + bool origin_upper_left); fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp, glsl_interp_qualifier interpolation_mode, bool is_centroid, bool is_sample); fs_reg *emit_frontfacing_interpolation(); fs_reg *emit_samplepos_setup(); fs_reg *emit_sampleid_setup(); - fs_reg *emit_general_interpolation(ir_variable *ir); - fs_reg *emit_vs_system_value(enum brw_reg_type type, int location); + void emit_general_interpolation(fs_reg attr, const char *name, + const glsl_type *type, + glsl_interp_qualifier interpolation_mode, + int location, bool mod_centroid, + bool mod_sample); + fs_reg *emit_vs_system_value(int location); void emit_interpolation_setup_gen4(); void emit_interpolation_setup_gen6(); void compute_sample_position(fs_reg dst, fs_reg int_sample_pos); - fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type, + fs_reg rescale_texcoord(fs_reg coordinate, int coord_components, bool is_rect, uint32_t sampler, int texunit); fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst, fs_reg coordinate, int coord_components, fs_reg shadow_comp, fs_reg lod, fs_reg lod2, int grad_components, uint32_t sampler); + fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst, + fs_reg coordinate, int vector_elements, + fs_reg shadow_c, fs_reg lod, + uint32_t sampler); fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst, fs_reg coordinate, int coord_components, fs_reg shadow_comp, @@ -504,11 +231,11 @@ public: fs_reg offset_value); void emit_texture(ir_texture_opcode op, const glsl_type *dest_type, - fs_reg coordinate, const struct glsl_type *coord_type, + fs_reg coordinate, int components, fs_reg shadow_c, fs_reg lod, fs_reg dpdy, int grad_components, fs_reg sample_index, - fs_reg offset, unsigned offset_components, + fs_reg offset, fs_reg mcs, int gather_component, bool is_cube_array, @@ -518,61 +245,69 @@ public: int texunit); fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler); void emit_gen6_gather_wa(uint8_t wa, fs_reg dst); - fs_reg fix_math_operand(fs_reg src); - fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0); - fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1); - void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y, - const fs_reg &a); - void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst, - const fs_reg &src0, const fs_reg &src1); - bool try_emit_saturate(ir_expression *ir); - bool try_emit_line(ir_expression *ir); - bool try_emit_mad(ir_expression *ir); - void try_replace_with_sel(); + void resolve_source_modifiers(fs_reg *src); + void emit_discard_jump(); + bool try_replace_with_sel(); bool opt_peephole_sel(); bool opt_peephole_predicated_break(); bool opt_saturate_propagation(); - void emit_bool_to_cond_code(ir_rvalue *condition); - void emit_if_gen6(ir_if *ir); + bool opt_cmod_propagation(); + bool opt_zero_samples(); void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg, uint32_t spill_offset, int count); void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg, uint32_t spill_offset, int count); - void emit_fragment_program_code(); - void setup_fp_regs(); - fs_reg get_fp_src_reg(const prog_src_register *src); - fs_reg get_fp_dst_reg(const prog_dst_register *dst); - void emit_fp_alu1(enum opcode opcode, - const struct prog_instruction *fpi, - fs_reg dst, fs_reg src); - void emit_fp_alu2(enum opcode opcode, - const struct prog_instruction *fpi, - fs_reg dst, fs_reg src0, fs_reg src1); - void emit_fp_scalar_write(const struct prog_instruction *fpi, - fs_reg dst, fs_reg src); - void emit_fp_scalar_math(enum opcode opcode, - const struct prog_instruction *fpi, - fs_reg dst, fs_reg src); - - void emit_fp_minmax(const struct prog_instruction *fpi, - fs_reg dst, fs_reg src0, fs_reg src1); - - void emit_fp_sop(enum brw_conditional_mod conditional_mod, - const struct prog_instruction *fpi, - fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one); - - int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components); + void emit_nir_code(); + void nir_setup_inputs(nir_shader *shader); + void nir_setup_outputs(nir_shader *shader); + void nir_setup_uniforms(nir_shader *shader); + void nir_setup_uniform(nir_variable *var); + void nir_setup_builtin_uniform(nir_variable *var); + void nir_emit_system_values(nir_shader *shader); + void nir_emit_impl(nir_function_impl *impl); + void nir_emit_cf_list(exec_list *list); + void nir_emit_if(nir_if *if_stmt); + void nir_emit_loop(nir_loop *loop); + void nir_emit_block(nir_block *block); + void nir_emit_instr(nir_instr *instr); + void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr); + void nir_emit_load_const(const brw::fs_builder &bld, + nir_load_const_instr *instr); + void nir_emit_undef(const brw::fs_builder &bld, + nir_ssa_undef_instr *instr); + void nir_emit_intrinsic(const brw::fs_builder &bld, + nir_intrinsic_instr *instr); + void nir_emit_texture(const brw::fs_builder &bld, + nir_tex_instr *instr); + void nir_emit_jump(const brw::fs_builder &bld, + nir_jump_instr *instr); + fs_reg get_nir_src(nir_src src); + fs_reg get_nir_dest(nir_dest dest); + void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst, + unsigned wr_mask); + + bool optimize_frontfacing_ternary(nir_alu_instr *instr, + const fs_reg &result); + + void setup_color_payload(fs_reg *dst, fs_reg color, unsigned components, + unsigned exec_size, bool use_2nd_half); void emit_alpha_test(); - fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2, - fs_reg src0_alpha, unsigned components); + fs_inst *emit_single_fb_write(const brw::fs_builder &bld, + fs_reg color1, fs_reg color2, + fs_reg src0_alpha, unsigned components, + unsigned exec_size, bool use_2nd_half = false); void emit_fb_writes(); void emit_urb_writes(); + void emit_cs_terminate(); + + void emit_barrier(); void emit_shader_time_begin(); void emit_shader_time_end(); - void emit_shader_time_write(enum shader_time_shader_type type, - fs_reg value); + void SHADER_TIME_ADD(const brw::fs_builder &bld, + int shader_time_subindex, + fs_reg value); void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, fs_reg dst, fs_reg offset, fs_reg src0, @@ -581,23 +316,9 @@ public: void emit_untyped_surface_read(unsigned surf_index, fs_reg dst, fs_reg offset); - void emit_interpolate_expression(ir_expression *ir); - - bool try_rewrite_rhs_to_dst(ir_assignment *ir, - fs_reg dst, - fs_reg src, - fs_inst *pre_rhs_inst, - fs_inst *last_rhs_inst); - void emit_assignment_writes(fs_reg &l, fs_reg &r, - const glsl_type *type, bool predicated); - void resolve_ud_negate(fs_reg *reg); - void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg); - - fs_reg get_timestamp(); + fs_reg get_timestamp(const brw::fs_builder &bld); struct brw_reg interp_reg(int location, int channel); - void setup_uniform_values(ir_variable *ir); - void setup_builtin_uniform_values(ir_variable *ir); int implied_mrf_writes(fs_inst *inst); virtual void dump_instructions(); @@ -605,17 +326,14 @@ public: void dump_instruction(backend_instruction *inst); void dump_instruction(backend_instruction *inst, FILE *file); - void visit_atomic_counter_intrinsic(ir_call *ir); - const void *const key; + const struct brw_sampler_prog_key_data *key_tex; + struct brw_stage_prog_data *prog_data; unsigned int sanity_param_count; int *param_size; - int *virtual_grf_sizes; - int virtual_grf_count; - int virtual_grf_array_size; int *virtual_grf_start; int *virtual_grf_end; brw::fs_live_variables *live_intervals; @@ -625,6 +343,9 @@ public: /** Number of uniform variable components visited. */ unsigned uniforms; + /** Total number of direct uniforms we can get from NIR */ + unsigned num_direct_uniforms; + /** Byte-offset for the next available spot in the scratch space buffer. */ unsigned last_scratch; @@ -640,7 +361,6 @@ public: */ int *push_constant_loc; - struct hash_table *variable_ht; fs_reg frag_depth; fs_reg sample_mask; fs_reg outputs[VARYING_SLOT_MAX]; @@ -649,26 +369,24 @@ public: bool do_dual_src; int first_non_payload_grf; /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */ - int max_grf; - - fs_reg *fp_temp_regs; - fs_reg *fp_input_regs; + unsigned max_grf; - /** @{ debug annotation info */ - const char *current_annotation; - const void *base_ir; - /** @} */ + fs_reg *nir_locals; + fs_reg *nir_ssa_values; + fs_reg nir_inputs; + fs_reg nir_outputs; + fs_reg *nir_system_values; bool failed; char *fail_msg; bool simd16_unsupported; char *no16_msg; - /* Result of last visit() method. */ + /* Result of last visit() method. Still used by emit_texture() */ fs_reg result; /** Register numbers for thread payload fields. */ - struct { + struct thread_payload { uint8_t source_depth_reg; uint8_t source_w_reg; uint8_t aa_dest_stencil_reg; @@ -688,15 +406,19 @@ public: fs_reg pixel_y; fs_reg wpos_w; fs_reg pixel_w; - fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; - fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; + fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT]; fs_reg shader_start_time; fs_reg userplane[MAX_CLIP_PLANES]; - int grf_used; + unsigned grf_used; bool spilled_any_registers; const unsigned dispatch_width; /**< 8 or 16 */ + + int shader_time_index; + + unsigned promoted_constants; + brw::fs_builder bld; }; /** @@ -707,12 +429,14 @@ public: class fs_generator { public: - fs_generator(struct brw_context *brw, + fs_generator(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, const void *key, struct brw_stage_prog_data *prog_data, struct gl_program *fp, - bool runtime_check_aads_emit); + unsigned promoted_constants, + bool runtime_check_aads_emit, + const char *stage_abbrev); ~fs_generator(); void enable_debug(const char *shader_name); @@ -726,8 +450,9 @@ private: GLuint nr); void generate_fb_write(fs_inst *inst, struct brw_reg payload); void generate_urb_write(fs_inst *inst, struct brw_reg payload); + void generate_cs_terminate(fs_inst *inst, struct brw_reg payload); + void generate_barrier(fs_inst *inst, struct brw_reg src); void generate_blorp_fb_write(fs_inst *inst); - void generate_pixel_xy(struct brw_reg dst, bool is_x); void generate_linterp(fs_inst *inst, struct brw_reg dst, struct brw_reg *src); void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src, @@ -797,23 +522,14 @@ private: struct brw_reg offset, struct brw_reg value); - void generate_untyped_atomic(fs_inst *inst, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg atomic_op, - struct brw_reg surf_index); - - void generate_untyped_surface_read(fs_inst *inst, - struct brw_reg dst, - struct brw_reg payload, - struct brw_reg surf_index); - bool patch_discard_jumps_to_fb_writes(); - struct brw_context *brw; - struct gl_context *ctx; + const struct brw_compiler *compiler; + void *log_data; /* Passed to compiler->*_log functions */ + + const struct brw_device_info *devinfo; - struct brw_compile *p; + struct brw_codegen *p; const void * const key; struct brw_stage_prog_data * const prog_data; @@ -822,11 +538,16 @@ private: unsigned dispatch_width; /**< 8 or 16 */ exec_list discard_halt_patches; + unsigned promoted_constants; bool runtime_check_aads_emit; bool debug_flag; const char *shader_name; + const char *stage_abbrev; void *mem_ctx; }; bool brw_do_channel_expressions(struct exec_list *instructions); bool brw_do_vector_splitting(struct exec_list *instructions); +void brw_setup_tex_for_precompile(struct brw_context *brw, + struct brw_sampler_prog_key_data *tex, + struct gl_program *prog);