X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_fs_reg_allocate.cpp;h=5c6f3d490f01185e94f1aafd9ce39c17c2e89708;hb=d0d4a5f43b4dd79bd7bfff7c7deaade10bfebf7c;hp=eba2fdd0816fdd8d05c1376701a9d38e8a037097;hpb=d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index eba2fdd0816..5c6f3d490f0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -25,35 +25,36 @@ * */ +#include "brw_eu.h" #include "brw_fs.h" #include "brw_cfg.h" -#include "glsl/glsl_types.h" -#include "glsl/ir_optimization.h" +#include "util/register_allocate.h" + +using namespace brw; static void -assign_reg(int *reg_hw_locations, fs_reg *reg) +assign_reg(unsigned *reg_hw_locations, fs_reg *reg) { - if (reg->file == GRF) { - assert(reg->reg_offset >= 0); - reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset; - reg->reg_offset = 0; + if (reg->file == VGRF) { + reg->nr = reg_hw_locations[reg->nr] + reg->offset / REG_SIZE; + reg->offset %= REG_SIZE; } } void fs_visitor::assign_regs_trivial() { - int hw_reg_mapping[this->virtual_grf_count + 1]; - int i; + unsigned hw_reg_mapping[this->alloc.count + 1]; + unsigned i; int reg_width = dispatch_width / 8; /* Note that compressed instructions require alignment to 2 registers. */ hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width); - for (i = 1; i <= this->virtual_grf_count; i++) { + for (i = 1; i <= this->alloc.count; i++) { hw_reg_mapping[i] = (hw_reg_mapping[i - 1] + - this->virtual_grf_sizes[i - 1]); + this->alloc.sizes[i - 1]); } - this->grf_used = hw_reg_mapping[this->virtual_grf_count]; + this->grf_used = hw_reg_mapping[this->alloc.count]; foreach_block_and_inst(block, fs_inst, inst, cfg) { assign_reg(hw_reg_mapping, &inst->dst); @@ -66,17 +67,26 @@ fs_visitor::assign_regs_trivial() fail("Ran out of regs on trivial allocator (%d/%d)\n", this->grf_used, max_grf); } else { - this->virtual_grf_count = this->grf_used; + this->alloc.count = this->grf_used; } } static void -brw_alloc_reg_set(struct intel_screen *screen, int reg_width) +brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) { - const struct brw_device_info *devinfo = screen->devinfo; + const struct gen_device_info *devinfo = compiler->devinfo; int base_reg_count = BRW_MAX_GRF; - int index = reg_width - 1; + const int index = _mesa_logbase2(dispatch_width / 8); + + if (dispatch_width > 8 && devinfo->gen >= 7) { + /* For IVB+, we don't need the PLN hacks or the even-reg alignment in + * SIMD16. Therefore, we can use the exact same register sets for + * SIMD16 as we do for SIMD8 and we don't need to recalculate them. + */ + compiler->fs_reg_sets[index] = compiler->fs_reg_sets[0]; + return; + } /* The registers used to make up almost all values handled in the compiler * are a scalar value occupying a single register (or 2 registers in the @@ -92,35 +102,20 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) * Additionally, on gen5 we need aligned pairs of registers for the PLN * instruction, and on gen4 we need 8 contiguous regs for workaround simd16 * texturing. - * - * So we have a need for classes for 1, 2, 4, and 8 registers currently, - * and we add in '3' to make indexing the array easier for the common case - * (since we'll probably want it for texturing later). - * - * And, on gen7 and newer, we do texturing SEND messages from GRFs, which - * means that we may need any size up to the sampler message size limit (11 - * regs). */ - int class_count; + const int class_count = MAX_VGRF_SIZE; int class_sizes[MAX_VGRF_SIZE]; + for (unsigned i = 0; i < MAX_VGRF_SIZE; i++) + class_sizes[i] = i + 1; - if (devinfo->gen >= 7) { - for (class_count = 0; class_count < MAX_VGRF_SIZE; class_count++) - class_sizes[class_count] = class_count + 1; - } else { - for (class_count = 0; class_count < 4; class_count++) - class_sizes[class_count] = class_count + 1; - class_sizes[class_count++] = 8; - } - - memset(screen->wm_reg_sets[index].class_to_ra_reg_range, 0, - sizeof(screen->wm_reg_sets[index].class_to_ra_reg_range)); - int *class_to_ra_reg_range = screen->wm_reg_sets[index].class_to_ra_reg_range; + memset(compiler->fs_reg_sets[index].class_to_ra_reg_range, 0, + sizeof(compiler->fs_reg_sets[index].class_to_ra_reg_range)); + int *class_to_ra_reg_range = compiler->fs_reg_sets[index].class_to_ra_reg_range; /* Compute the total number of registers across all classes. */ int ra_reg_count = 0; for (int i = 0; i < class_count; i++) { - if (devinfo->gen <= 5 && reg_width == 2) { + if (devinfo->gen <= 5 && dispatch_width >= 16) { /* From the G45 PRM: * * In order to reduce the hardware complexity, the following @@ -145,16 +140,16 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) class_to_ra_reg_range[i] = class_to_ra_reg_range[i-1]; } - uint8_t *ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count); - struct ra_regs *regs = ra_alloc_reg_set(screen, ra_reg_count); + uint8_t *ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count); + struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count, false); if (devinfo->gen >= 6) ra_set_allocate_round_robin(regs); - int *classes = ralloc_array(screen, int, class_count); + int *classes = ralloc_array(compiler, int, class_count); int aligned_pairs_class = -1; /* Allocate space for q values. We allocate class_count + 1 because we * want to leave room for the aligned pairs class if we have it. */ - unsigned int **q_values = ralloc_array(screen, unsigned int *, + unsigned int **q_values = ralloc_array(compiler, unsigned int *, class_count + 1); for (int i = 0; i < class_count + 1; ++i) q_values[i] = ralloc_array(q_values, unsigned int, class_count + 1); @@ -167,7 +162,7 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) int pairs_reg_count = 0; for (int i = 0; i < class_count; i++) { int class_reg_count; - if (devinfo->gen <= 5 && reg_width == 2) { + if (devinfo->gen <= 5 && dispatch_width >= 16) { class_reg_count = (base_reg_count - (class_sizes[i] - 1)) / 2; /* See comment below. The only difference here is that we are @@ -213,7 +208,7 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) pairs_reg_count = class_reg_count; } - if (devinfo->gen <= 5 && reg_width == 2) { + if (devinfo->gen <= 5 && dispatch_width >= 16) { for (int j = 0; j < class_reg_count; j++) { ra_class_add_reg(regs, classes[i], reg); @@ -222,7 +217,7 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) for (int base_reg = j; base_reg < j + (class_sizes[i] + 1) / 2; base_reg++) { - ra_add_transitive_reg_conflict(regs, base_reg, reg); + ra_add_reg_conflict(regs, base_reg, reg); } reg++; @@ -236,7 +231,7 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) for (int base_reg = j; base_reg < j + class_sizes[i]; base_reg++) { - ra_add_transitive_reg_conflict(regs, base_reg, reg); + ra_add_reg_conflict(regs, base_reg, reg); } reg++; @@ -245,10 +240,16 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) } assert(reg == ra_reg_count); - /* Add a special class for aligned pairs, which we'll put delta_x/y - * in on gen5 so that we can do PLN. + /* Applying transitivity to all of the base registers gives us the + * appropreate register conflict relationships everywhere. + */ + for (int reg = 0; reg < base_reg_count; reg++) + ra_make_reg_conflicts_transitive(regs, reg); + + /* Add a special class for aligned pairs, which we'll put delta_xy + * in on Gen <= 6 so that we can do PLN. */ - if (devinfo->has_pln && reg_width == 1 && devinfo->gen < 6) { + if (devinfo->has_pln && dispatch_width == 8 && devinfo->gen <= 6) { aligned_pairs_class = ra_alloc_reg_class(regs); for (int i = 0; i < pairs_reg_count; i++) { @@ -274,20 +275,21 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width) ralloc_free(q_values); - screen->wm_reg_sets[index].regs = regs; - for (unsigned i = 0; i < ARRAY_SIZE(screen->wm_reg_sets[index].classes); i++) - screen->wm_reg_sets[index].classes[i] = -1; + compiler->fs_reg_sets[index].regs = regs; + for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++) + compiler->fs_reg_sets[index].classes[i] = -1; for (int i = 0; i < class_count; i++) - screen->wm_reg_sets[index].classes[class_sizes[i] - 1] = classes[i]; - screen->wm_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf; - screen->wm_reg_sets[index].aligned_pairs_class = aligned_pairs_class; + compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i]; + compiler->fs_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf; + compiler->fs_reg_sets[index].aligned_pairs_class = aligned_pairs_class; } void -brw_fs_alloc_reg_sets(struct intel_screen *screen) +brw_fs_alloc_reg_sets(struct brw_compiler *compiler) { - brw_alloc_reg_set(screen, 1); - brw_alloc_reg_set(screen, 2); + brw_alloc_reg_set(compiler, 8); + brw_alloc_reg_set(compiler, 16); + brw_alloc_reg_set(compiler, 32); } static int @@ -314,33 +316,15 @@ count_to_loop_end(const bblock_t *block) unreachable("not reached"); } -/** - * Sets up interference between thread payload registers and the virtual GRFs - * to be allocated for program temporaries. - * - * We want to be able to reallocate the payload for our virtual GRFs, notably - * because the setup coefficients for a full set of 16 FS inputs takes up 8 of - * our 128 registers. - * - * The layout of the payload registers is: - * - * 0..payload.num_regs-1: fixed function setup (including bary coordinates). - * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data - * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients. - * - * And we have payload_node_count nodes covering these registers in order - * (note that in SIMD16, a node is two registers). - */ -void -fs_visitor::setup_payload_interference(struct ra_graph *g, - int payload_node_count, - int first_payload_node) +void fs_visitor::calculate_payload_ranges(int payload_node_count, + int *payload_last_use_ip) { int loop_depth = 0; int loop_end_ip = 0; - int payload_last_use_ip[payload_node_count]; - memset(payload_last_use_ip, 0, sizeof(payload_last_use_ip)); + for (int i = 0; i < payload_node_count; i++) + payload_last_use_ip[i] = -1; + int ip = 0; foreach_block_and_inst(block, fs_inst, inst, cfg) { switch (inst->opcode) { @@ -368,67 +352,82 @@ fs_visitor::setup_payload_interference(struct ra_graph *g, else use_ip = ip; - /* Note that UNIFORM args have been turned into FIXED_HW_REG by + /* Note that UNIFORM args have been turned into FIXED_GRF by * assign_curbe_setup(), and interpolation uses fixed hardware regs from * the start (see interp_reg()). */ for (int i = 0; i < inst->sources; i++) { - if (inst->src[i].file == HW_REG && - inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) { - int node_nr = inst->src[i].fixed_hw_reg.nr; + if (inst->src[i].file == FIXED_GRF) { + int node_nr = inst->src[i].nr; if (node_nr >= payload_node_count) continue; - payload_last_use_ip[node_nr] = use_ip; + for (unsigned j = 0; j < regs_read(inst, i); j++) { + payload_last_use_ip[node_nr + j] = use_ip; + assert(node_nr + j < unsigned(payload_node_count)); + } } } /* Special case instructions which have extra implied registers used. */ switch (inst->opcode) { - case SHADER_OPCODE_URB_WRITE_SIMD8: - case FS_OPCODE_FB_WRITE: - /* We could omit this for the !inst->header_present case, except that - * the simulator apparently incorrectly reads from g0/g1 instead of - * sideband. It also really freaks out driver developers to see g0 - * used in unusual places, so just always reserve it. - */ + case CS_OPCODE_CS_TERMINATE: payload_last_use_ip[0] = use_ip; - payload_last_use_ip[1] = use_ip; - break; - - case FS_OPCODE_LINTERP: - /* On gen6+ in SIMD16, there are 4 adjacent registers used by - * PLN's sourcing of the deltas, while we list only the first one - * in the arguments. Pre-gen6, the deltas are computed in normal - * VGRFs. - */ - if (brw->gen >= 6) { - int delta_x_arg = 0; - if (inst->src[delta_x_arg].file == HW_REG && - inst->src[delta_x_arg].fixed_hw_reg.file == - BRW_GENERAL_REGISTER_FILE) { - for (int i = 1; i < 4; ++i) { - int node = inst->src[delta_x_arg].fixed_hw_reg.nr + i; - assert(node < payload_node_count); - payload_last_use_ip[node] = use_ip; - } - } - } break; default: + if (inst->eot) { + /* We could omit this for the !inst->header_present case, except + * that the simulator apparently incorrectly reads from g0/g1 + * instead of sideband. It also really freaks out driver + * developers to see g0 used in unusual places, so just always + * reserve it. + */ + payload_last_use_ip[0] = use_ip; + payload_last_use_ip[1] = use_ip; + } break; } ip++; } +} + + +/** + * Sets up interference between thread payload registers and the virtual GRFs + * to be allocated for program temporaries. + * + * We want to be able to reallocate the payload for our virtual GRFs, notably + * because the setup coefficients for a full set of 16 FS inputs takes up 8 of + * our 128 registers. + * + * The layout of the payload registers is: + * + * 0..payload.num_regs-1: fixed function setup (including bary coordinates). + * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data + * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients. + * + * And we have payload_node_count nodes covering these registers in order + * (note that in SIMD16, a node is two registers). + */ +void +fs_visitor::setup_payload_interference(struct ra_graph *g, + int payload_node_count, + int first_payload_node) +{ + int payload_last_use_ip[payload_node_count]; + calculate_payload_ranges(payload_node_count, payload_last_use_ip); for (int i = 0; i < payload_node_count; i++) { + if (payload_last_use_ip[i] == -1) + continue; + /* Mark the payload node as interfering with any virtual grf that is * live between the start of the program and our last use of the payload * node. */ - for (int j = 0; j < this->virtual_grf_count; j++) { + for (unsigned j = 0; j < this->alloc.count; j++) { /* Note that we use a <= comparison, unlike virtual_grf_interferes(), * in order to not have to worry about the uniform issue described in * calculate_live_intervals(). @@ -445,7 +444,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g, * The alternative would be to have per-physical-register classes, which * would just be silly. */ - if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) { + if (devinfo->gen <= 5 && dispatch_width >= 16) { /* We have to divide by 2 here because we only have even numbered * registers. Some of the payload registers will be odd, but * that's ok because their physical register numbers have already @@ -466,19 +465,19 @@ fs_visitor::setup_payload_interference(struct ra_graph *g, * see if we can actually use MRFs to do spills without overwriting normal MRF * contents. */ -void -fs_visitor::get_used_mrfs(bool *mrf_used) +static void +get_used_mrfs(fs_visitor *v, bool *mrf_used) { - int reg_width = dispatch_width / 8; + int reg_width = v->dispatch_width / 8; - memset(mrf_used, 0, BRW_MAX_MRF * sizeof(bool)); + memset(mrf_used, 0, BRW_MAX_MRF(v->devinfo->gen) * sizeof(bool)); - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, fs_inst, inst, v->cfg) { if (inst->dst.file == MRF) { - int reg = inst->dst.reg & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~BRW_MRF_COMPR4; mrf_used[reg] = true; if (reg_width == 2) { - if (inst->dst.reg & BRW_MRF_COMPR4) { + if (inst->dst.nr & BRW_MRF_COMPR4) { mrf_used[reg + 4] = true; } else { mrf_used[reg + 1] = true; @@ -487,7 +486,7 @@ fs_visitor::get_used_mrfs(bool *mrf_used) } if (inst->mlen > 0) { - for (int i = 0; i < implied_mrf_writes(inst); i++) { + for (int i = 0; i < v->implied_mrf_writes(inst); i++) { mrf_used[inst->base_mrf + i] = true; } } @@ -498,13 +497,15 @@ fs_visitor::get_used_mrfs(bool *mrf_used) * Sets interference between virtual GRFs and usage of the high GRFs for SEND * messages (treated as MRFs in code generation). */ -void -fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node) +static void +setup_mrf_hack_interference(fs_visitor *v, struct ra_graph *g, + int first_mrf_node, int *first_used_mrf) { - bool mrf_used[BRW_MAX_MRF]; - get_used_mrfs(mrf_used); + bool mrf_used[BRW_MAX_MRF(v->devinfo->gen)]; + get_used_mrfs(v, mrf_used); - for (int i = 0; i < BRW_MAX_MRF; i++) { + *first_used_mrf = BRW_MAX_MRF(v->devinfo->gen); + for (int i = 0; i < BRW_MAX_MRF(v->devinfo->gen); i++) { /* Mark each MRF reg node as being allocated to its physical register. * * The alternative would be to have per-physical-register classes, which @@ -516,30 +517,19 @@ fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node) * that are used as conflicting with all virtual GRFs. */ if (mrf_used[i]) { - for (int j = 0; j < this->virtual_grf_count; j++) { + if (i < *first_used_mrf) + *first_used_mrf = i; + + for (unsigned j = 0; j < v->alloc.count; j++) { ra_add_node_interference(g, first_mrf_node + i, j); } } } } -static bool -is_last_send(fs_inst *inst) -{ - switch (inst->opcode) { - case SHADER_OPCODE_URB_WRITE_SIMD8: - case FS_OPCODE_FB_WRITE: - return inst->eot; - default: - assert(!inst->eot); - return false; - } -} - bool -fs_visitor::assign_regs(bool allow_spilling) +fs_visitor::assign_regs(bool allow_spilling, bool spill_all) { - struct intel_screen *screen = brw->intelScreen; /* Most of this allocation was written for a reg_width of 1 * (dispatch_width == 8). In extending to SIMD16, the code was * left in place and it was converted to have the hardware @@ -547,55 +537,70 @@ fs_visitor::assign_regs(bool allow_spilling) * for reg_width == 2. */ int reg_width = dispatch_width / 8; - int hw_reg_mapping[this->virtual_grf_count]; + unsigned hw_reg_mapping[this->alloc.count]; int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width); - int rsi = reg_width - 1; /* Which screen->wm_reg_sets[] to use */ + int rsi = _mesa_logbase2(reg_width); /* Which compiler->fs_reg_sets[] to use */ calculate_live_intervals(); - int node_count = this->virtual_grf_count; + int node_count = this->alloc.count; int first_payload_node = node_count; node_count += payload_node_count; int first_mrf_hack_node = node_count; - if (brw->gen >= 7) + if (devinfo->gen >= 7) node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START; struct ra_graph *g = - ra_alloc_interference_graph(screen->wm_reg_sets[rsi].regs, node_count); + ra_alloc_interference_graph(compiler->fs_reg_sets[rsi].regs, node_count); - for (int i = 0; i < this->virtual_grf_count; i++) { - unsigned size = this->virtual_grf_sizes[i]; + for (unsigned i = 0; i < this->alloc.count; i++) { + unsigned size = this->alloc.sizes[i]; int c; - assert(size <= ARRAY_SIZE(screen->wm_reg_sets[rsi].classes) && + assert(size <= ARRAY_SIZE(compiler->fs_reg_sets[rsi].classes) && "Register allocation relies on split_virtual_grfs()"); - c = screen->wm_reg_sets[rsi].classes[size - 1]; + c = compiler->fs_reg_sets[rsi].classes[size - 1]; /* Special case: on pre-GEN6 hardware that supports PLN, the * second operand of a PLN instruction needs to be an * even-numbered register, so we have a special register class * wm_aligned_pairs_class to handle this case. pre-GEN6 always - * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the + * uses this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL] as the * second operand of a PLN instruction (since it doesn't support * any other interpolation modes). So all we need to do is find * that register and set it to the appropriate class. */ - if (screen->wm_reg_sets[rsi].aligned_pairs_class >= 0 && - this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF && - this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg == i) { - c = screen->wm_reg_sets[rsi].aligned_pairs_class; + if (compiler->fs_reg_sets[rsi].aligned_pairs_class >= 0 && + this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL].file == VGRF && + this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL].nr == i) { + c = compiler->fs_reg_sets[rsi].aligned_pairs_class; } ra_set_node_class(g, i, c); - for (int j = 0; j < i; j++) { + for (unsigned j = 0; j < i; j++) { if (virtual_grf_interferes(i, j)) { ra_add_node_interference(g, i, j); } } } + /* Certain instructions can't safely use the same register for their + * sources and destination. Add interference. + */ + foreach_block_and_inst(block, fs_inst, inst, cfg) { + if (inst->dst.file == VGRF && inst->has_source_and_destination_hazard()) { + for (unsigned i = 0; i < 3; i++) { + if (inst->src[i].file == VGRF) { + ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr); + } + } + } + } + setup_payload_interference(g, payload_node_count, first_payload_node); - if (brw->gen >= 7) { - setup_mrf_hack_interference(g, first_mrf_hack_node); + if (devinfo->gen >= 7) { + int first_used_mrf = BRW_MAX_MRF(devinfo->gen); + setup_mrf_hack_interference(this, g, first_mrf_hack_node, + &first_used_mrf); foreach_block_and_inst(block, fs_inst, inst, cfg) { /* When we do send-from-GRF for FB writes, we need to ensure that @@ -608,10 +613,17 @@ fs_visitor::assign_regs(bool allow_spilling) * We could just do "something high". Instead, we just pick the * highest register that works. */ - if (is_last_send(inst)) { - int size = virtual_grf_sizes[inst->src[0].reg]; - int reg = screen->wm_reg_sets[rsi].class_to_ra_reg_range[size] - 1; - ra_set_node_reg(g, inst->src[0].reg, reg); + if (inst->eot) { + int size = alloc.sizes[inst->src[0].nr]; + int reg = compiler->fs_reg_sets[rsi].class_to_ra_reg_range[size] - 1; + + /* If something happened to spill, we want to push the EOT send + * register early enough in the register file that we don't + * conflict with any used MRF hack registers. + */ + reg -= BRW_MAX_MRF(devinfo->gen) - first_used_mrf; + + ra_set_node_reg(g, inst->src[0].nr, reg); break; } } @@ -630,19 +642,19 @@ fs_visitor::assign_regs(bool allow_spilling) * destination interfere. */ foreach_block_and_inst(block, fs_inst, inst, cfg) { - if (inst->dst.file != GRF) + if (inst->dst.file != VGRF) continue; for (int i = 0; i < inst->sources; ++i) { - if (inst->src[i].file == GRF) { - ra_add_node_interference(g, inst->dst.reg, inst->src[i].reg); + if (inst->src[i].file == VGRF) { + ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr); } } } } /* Debug of register spilling: Go spill everything. */ - if (0) { + if (unlikely(spill_all)) { int reg = choose_spill_reg(g); if (reg != -1) { @@ -675,12 +687,12 @@ fs_visitor::assign_regs(bool allow_spilling) * numbers. */ this->grf_used = payload_node_count; - for (int i = 0; i < this->virtual_grf_count; i++) { + for (unsigned i = 0; i < this->alloc.count; i++) { int reg = ra_get_node_reg(g, i); - hw_reg_mapping[i] = screen->wm_reg_sets[rsi].ra_reg_to_grf[reg]; + hw_reg_mapping[i] = compiler->fs_reg_sets[rsi].ra_reg_to_grf[reg]; this->grf_used = MAX2(this->grf_used, - hw_reg_mapping[i] + this->virtual_grf_sizes[i]); + hw_reg_mapping[i] + this->alloc.sizes[i]); } foreach_block_and_inst(block, fs_inst, inst, cfg) { @@ -690,70 +702,104 @@ fs_visitor::assign_regs(bool allow_spilling) } } - this->virtual_grf_count = this->grf_used; + this->alloc.count = this->grf_used; ralloc_free(g); return true; } -void -fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst, - uint32_t spill_offset, int count) -{ - int reg_size = 1; - if (dispatch_width == 16 && count % 2 == 0) { - reg_size = 2; - dst.width = 16; +namespace { + /** + * Maximum spill block size we expect to encounter in 32B units. + * + * This is somewhat arbitrary and doesn't necessarily limit the maximum + * variable size that can be spilled -- A higher value will allow a + * variable of a given size to be spilled more efficiently with a smaller + * number of scratch messages, but will increase the likelihood of a + * collision between the MRFs reserved for spilling and other MRFs used by + * the program (and possibly increase GRF register pressure on platforms + * without hardware MRFs), what could cause register allocation to fail. + * + * For the moment reserve just enough space so a register of 32 bit + * component type and natural region width can be spilled without splitting + * into multiple (force_writemask_all) scratch messages. + */ + unsigned + spill_max_size(const backend_shader *s) + { + /* FINISHME - On Gen7+ it should be possible to avoid this limit + * altogether by spilling directly from the temporary GRF + * allocated to hold the result of the instruction (and the + * scratch write header). + */ + /* FINISHME - The shader's dispatch width probably belongs in + * backend_shader (or some nonexistent fs_shader class?) + * rather than in the visitor class. + */ + return static_cast(s)->dispatch_width / 8; } - for (int i = 0; i < count / reg_size; i++) { - /* The gen7 descriptor-based offset is 12 bits of HWORD units. */ - bool gen7_read = brw->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE; + /** + * First MRF register available for spilling. + */ + unsigned + spill_base_mrf(const backend_shader *s) + { + return BRW_MAX_MRF(s->devinfo->gen) - spill_max_size(s) - 1; + } +} - fs_inst *unspill_inst = - new(mem_ctx) fs_inst(gen7_read ? - SHADER_OPCODE_GEN7_SCRATCH_READ : - SHADER_OPCODE_GEN4_SCRATCH_READ, - dst); +static void +emit_unspill(const fs_builder &bld, fs_reg dst, + uint32_t spill_offset, unsigned count) +{ + const gen_device_info *devinfo = bld.shader->devinfo; + const unsigned reg_size = dst.component_size(bld.dispatch_width()) / + REG_SIZE; + assert(count % reg_size == 0); + + for (unsigned i = 0; i < count / reg_size; i++) { + /* The Gen7 descriptor-based offset is 12 bits of HWORD units. Because + * the Gen7-style scratch block read is hardwired to BTI 255, on Gen9+ + * it would cause the DC to do an IA-coherent read, what largely + * outweighs the slight advantage from not having to provide the address + * as part of the message header, so we're better off using plain old + * oword block reads. + */ + bool gen7_read = (devinfo->gen >= 7 && devinfo->gen < 9 && + spill_offset < (1 << 12) * REG_SIZE); + fs_inst *unspill_inst = bld.emit(gen7_read ? + SHADER_OPCODE_GEN7_SCRATCH_READ : + SHADER_OPCODE_GEN4_SCRATCH_READ, + dst); unspill_inst->offset = spill_offset; - unspill_inst->ir = inst->ir; - unspill_inst->annotation = inst->annotation; - unspill_inst->regs_written = reg_size; if (!gen7_read) { - unspill_inst->base_mrf = 14; + unspill_inst->base_mrf = spill_base_mrf(bld.shader); unspill_inst->mlen = 1; /* header contains offset */ } - inst->insert_before(block, unspill_inst); - dst.reg_offset += reg_size; + dst.offset += reg_size * REG_SIZE; spill_offset += reg_size * REG_SIZE; } } -void -fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src, - uint32_t spill_offset, int count) +static void +emit_spill(const fs_builder &bld, fs_reg src, + uint32_t spill_offset, unsigned count) { - int reg_size = 1; - int spill_base_mrf = 14; - if (dispatch_width == 16 && count % 2 == 0) { - spill_base_mrf = 13; - reg_size = 2; - } + const unsigned reg_size = src.component_size(bld.dispatch_width()) / + REG_SIZE; + assert(count % reg_size == 0); - for (int i = 0; i < count / reg_size; i++) { + for (unsigned i = 0; i < count / reg_size; i++) { fs_inst *spill_inst = - new(mem_ctx) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE, - reg_size * 8, reg_null_f, src); - src.reg_offset += reg_size; + bld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, bld.null_reg_f(), src); + src.offset += reg_size * REG_SIZE; spill_inst->offset = spill_offset + i * reg_size * REG_SIZE; - spill_inst->ir = inst->ir; - spill_inst->annotation = inst->annotation; spill_inst->mlen = 1 + reg_size; /* header, value */ - spill_inst->base_mrf = spill_base_mrf; - inst->insert_after(block, spill_inst); + spill_inst->base_mrf = spill_base_mrf(bld.shader); } } @@ -761,10 +807,10 @@ int fs_visitor::choose_spill_reg(struct ra_graph *g) { float loop_scale = 1.0; - float spill_costs[this->virtual_grf_count]; - bool no_spill[this->virtual_grf_count]; + float spill_costs[this->alloc.count]; + bool no_spill[this->alloc.count]; - for (int i = 0; i < this->virtual_grf_count; i++) { + for (unsigned i = 0; i < this->alloc.count; i++) { spill_costs[i] = 0.0; no_spill[i] = false; } @@ -775,29 +821,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) */ foreach_block_and_inst(block, fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { - if (inst->src[i].file == GRF) { - spill_costs[inst->src[i].reg] += loop_scale; - - /* Register spilling logic assumes full-width registers; smeared - * registers have a width of 1 so if we try to spill them we'll - * generate invalid assembly. This shouldn't be a problem because - * smeared registers are only used as short-term temporaries when - * loading pull constants, so spilling them is unlikely to reduce - * register pressure anyhow. - */ - if (!inst->src[i].is_contiguous()) { - no_spill[inst->src[i].reg] = true; - } - } + if (inst->src[i].file == VGRF) + spill_costs[inst->src[i].nr] += loop_scale; } - if (inst->dst.file == GRF) { - spill_costs[inst->dst.reg] += inst->regs_written * loop_scale; - - if (!inst->dst.is_contiguous()) { - no_spill[inst->dst.reg] = true; - } - } + if (inst->dst.file == VGRF) + spill_costs[inst->dst.nr] += DIV_ROUND_UP(inst->size_written, REG_SIZE) + * loop_scale; switch (inst->opcode) { @@ -810,14 +840,14 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) break; case SHADER_OPCODE_GEN4_SCRATCH_WRITE: - if (inst->src[0].file == GRF) - no_spill[inst->src[0].reg] = true; + if (inst->src[0].file == VGRF) + no_spill[inst->src[0].nr] = true; break; case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GEN7_SCRATCH_READ: - if (inst->dst.file == GRF) - no_spill[inst->dst.reg] = true; + if (inst->dst.file == VGRF) + no_spill[inst->dst.nr] = true; break; default: @@ -825,7 +855,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) } } - for (int i = 0; i < this->virtual_grf_count; i++) { + for (unsigned i = 0; i < this->alloc.count; i++) { if (!no_spill[i]) ra_set_node_spill_cost(g, i, spill_costs[i]); } @@ -836,10 +866,9 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) void fs_visitor::spill_reg(int spill_reg) { - int size = virtual_grf_sizes[spill_reg]; + int size = alloc.sizes[spill_reg]; unsigned int spill_offset = last_scratch; assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */ - int spill_base_mrf = dispatch_width > 8 ? 13 : 14; /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done * using up to 11 MRFs starting from either m1 or m2, and fb writes can use @@ -849,10 +878,10 @@ fs_visitor::spill_reg(int spill_reg) * SIMD16 mode, because we'd stomp the FB writes. */ if (!spilled_any_registers) { - bool mrf_used[BRW_MAX_MRF]; - get_used_mrfs(mrf_used); + bool mrf_used[BRW_MAX_MRF(devinfo->gen)]; + get_used_mrfs(this, mrf_used); - for (int i = spill_base_mrf; i < BRW_MAX_MRF; i++) { + for (int i = spill_base_mrf(this); i < BRW_MAX_MRF(devinfo->gen); i++) { if (mrf_used[i]) { fail("Register spilling not supported with m%d used", i); return; @@ -870,30 +899,46 @@ fs_visitor::spill_reg(int spill_reg) * could just spill/unspill the GRF being accessed. */ foreach_block_and_inst (block, fs_inst, inst, cfg) { + const fs_builder ibld = fs_builder(this, block, inst); + for (unsigned int i = 0; i < inst->sources; i++) { - if (inst->src[i].file == GRF && - inst->src[i].reg == spill_reg) { - int regs_read = inst->regs_read(this, i); - int subset_spill_offset = (spill_offset + - REG_SIZE * inst->src[i].reg_offset); - fs_reg unspill_dst(GRF, virtual_grf_alloc(regs_read)); - - inst->src[i].reg = unspill_dst.reg; - inst->src[i].reg_offset = 0; - - emit_unspill(block, inst, unspill_dst, subset_spill_offset, - regs_read); + if (inst->src[i].file == VGRF && + inst->src[i].nr == spill_reg) { + int count = regs_read(inst, i); + int subset_spill_offset = spill_offset + + ROUND_DOWN_TO(inst->src[i].offset, REG_SIZE); + fs_reg unspill_dst(VGRF, alloc.allocate(count)); + + inst->src[i].nr = unspill_dst.nr; + inst->src[i].offset %= REG_SIZE; + + /* We read the largest power-of-two divisor of the register count + * (because only POT scratch read blocks are allowed by the + * hardware) up to the maximum supported block size. + */ + const unsigned width = + MIN2(32, 1u << (ffs(MAX2(1, count) * 8) - 1)); + + /* Set exec_all() on unspill messages under the (rather + * pessimistic) assumption that there is no one-to-one + * correspondence between channels of the spilled variable in + * scratch space and the scratch read message, which operates on + * 32 bit channels. It shouldn't hurt in any case because the + * unspill destination is a block-local temporary. + */ + emit_unspill(ibld.exec_all().group(width, 0), + unspill_dst, subset_spill_offset, count); } } - if (inst->dst.file == GRF && - inst->dst.reg == spill_reg) { - int subset_spill_offset = (spill_offset + - REG_SIZE * inst->dst.reg_offset); - fs_reg spill_src(GRF, virtual_grf_alloc(inst->regs_written)); + if (inst->dst.file == VGRF && + inst->dst.nr == spill_reg) { + int subset_spill_offset = spill_offset + + ROUND_DOWN_TO(inst->dst.offset, REG_SIZE); + fs_reg spill_src(VGRF, alloc.allocate(regs_written(inst))); - inst->dst.reg = spill_src.reg; - inst->dst.reg_offset = 0; + inst->dst.nr = spill_src.nr; + inst->dst.offset %= REG_SIZE; /* If we're immediately spilling the register, we should not use * destination dependency hints. Doing so will cause the GPU do @@ -903,16 +948,43 @@ fs_visitor::spill_reg(int spill_reg) inst->no_dd_clear = false; inst->no_dd_check = false; + /* Calculate the execution width of the scratch messages (which work + * in terms of 32 bit components so we have a fixed number of eight + * channels per spilled register). We attempt to write one + * exec_size-wide component of the variable at a time without + * exceeding the maximum number of (fake) MRF registers reserved for + * spills. + */ + const unsigned width = 8 * MIN2( + DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE), + spill_max_size(this)); + + /* Spills should only write data initialized by the instruction for + * whichever channels are enabled in the excution mask. If that's + * not possible we'll have to emit a matching unspill before the + * instruction and set force_writemask_all on the spill. + */ + const bool per_channel = + inst->dst.is_contiguous() && type_sz(inst->dst.type) == 4 && + inst->exec_size == width; + + /* Builder used to emit the scratch messages. */ + const fs_builder ubld = ibld.exec_all(!per_channel).group(width, 0); + /* If our write is going to affect just part of the - * inst->regs_written(), then we need to unspill the destination - * since we write back out all of the regs_written(). + * regs_written(inst), then we need to unspill the destination since + * we write back out all of the regs_written(). If the original + * instruction had force_writemask_all set and is not a partial + * write, there should be no need for the unspill since the + * instruction will be overwriting the whole destination in any case. */ - if (inst->is_partial_write()) - emit_unspill(block, inst, spill_src, subset_spill_offset, - inst->regs_written); + if (inst->is_partial_write() || + (!inst->force_writemask_all && !per_channel)) + emit_unspill(ubld, spill_src, subset_spill_offset, + regs_written(inst)); - emit_spill(block, inst, spill_src, subset_spill_offset, - inst->regs_written); + emit_spill(ubld.at(block, inst->next), spill_src, + subset_spill_offset, regs_written(inst)); } }