X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_gs.c;h=26c91e4c76acea56ab8b6ac01c1cadfa276f5431;hb=ba71d581aeb96c4626500eb5b19f3bef2f40d586;hp=3171e97d7af912b00bb8f0a059417a922053933d;hpb=c173541d9769d41a85cc899bc49699a3587df4bf;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 3171e97d7af..26c91e4c76a 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -1,206 +1,420 @@ /* - Copyright (C) Intel Corp. 2006. All Rights Reserved. - Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to - develop this 3D driver. - - Permission is hereby granted, free of charge, to any person obtaining - a copy of this software and associated documentation files (the - "Software"), to deal in the Software without restriction, including - without limitation the rights to use, copy, modify, merge, publish, - distribute, sublicense, and/or sell copies of the Software, and to - permit persons to whom the Software is furnished to do so, subject to - the following conditions: - - The above copyright notice and this permission notice (including the - next paragraph) shall be included in all copies or substantial - portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - **********************************************************************/ - /* - * Authors: - * Keith Whitwell - */ - -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" - -#include "intel_batchbuffer.h" - -#include "brw_defines.h" + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/** + * \file brw_vec4_gs.c + * + * State atom for client-programmable geometry shaders, and support code. + */ + +#include "brw_gs.h" #include "brw_context.h" -#include "brw_eu.h" -#include "brw_util.h" +#include "brw_vec4_gs_visitor.h" #include "brw_state.h" -#include "brw_gs.h" - -#include "../glsl/ralloc.h" +#include "brw_ff_gs.h" +#include "brw_nir.h" -static void compile_gs_prog( struct brw_context *brw, - struct brw_gs_prog_key *key ) +static void +assign_gs_binding_table_offsets(const struct brw_device_info *devinfo, + const struct gl_shader_program *shader_prog, + const struct gl_program *prog, + struct brw_gs_prog_data *prog_data) { - struct intel_context *intel = &brw->intel; - struct brw_gs_compile c; - const GLuint *program; - void *mem_ctx; - GLuint program_size; - - /* Gen6: VF has already converted into polygon, and LINELOOP is - * converted to LINESTRIP at the beginning of the 3D pipeline. + /* In gen6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform + * feedback surfaces. */ - if (intel->gen >= 6) - return; + uint32_t reserved = devinfo->gen == 6 ? BRW_MAX_SOL_BINDINGS : 0; + + brw_assign_common_binding_table_offsets(MESA_SHADER_GEOMETRY, devinfo, + shader_prog, prog, + &prog_data->base.base, + reserved); +} +bool +brw_codegen_gs_prog(struct brw_context *brw, + struct gl_shader_program *prog, + struct brw_geometry_program *gp, + struct brw_gs_prog_key *key) +{ + struct brw_stage_state *stage_state = &brw->gs.base; + struct brw_gs_compile c; memset(&c, 0, sizeof(c)); - c.key = *key; - /* Need to locate the two positions present in vertex + header. - * These are currently hardcoded: + c.gp = gp; + + c.prog_data.include_primitive_id = + (gp->program.Base.InputsRead & VARYING_BIT_PRIMITIVE_ID) != 0; + + c.prog_data.invocations = gp->program.Invocations; + + assign_gs_binding_table_offsets(brw->intelScreen->devinfo, prog, + &gp->program.Base, &c.prog_data); + + /* Allocate the references to the uniforms that will end up in the + * prog_data associated with the compiled program, and which will be freed + * by the state cache. + * + * Note: param_count needs to be num_uniform_components * 4, since we add + * padding around uniform values below vec4 size, so the worst case is that + * every uniform is a float which gets padded to the size of a vec4. */ - c.nr_attrs = brw_count_bits(c.key.attrs); + struct gl_shader *gs = prog->_LinkedShaders[MESA_SHADER_GEOMETRY]; + int param_count = gp->program.Base.nir->num_uniforms * 4; - if (intel->gen >= 5) - c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ - else - c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ + c.prog_data.base.base.param = + rzalloc_array(NULL, const gl_constant_value *, param_count); + c.prog_data.base.base.pull_param = + rzalloc_array(NULL, const gl_constant_value *, param_count); + c.prog_data.base.base.image_param = + rzalloc_array(NULL, struct brw_image_param, gs->NumImages); + c.prog_data.base.base.nr_params = param_count; + c.prog_data.base.base.nr_image_params = gs->NumImages; + + brw_nir_setup_glsl_uniforms(gp->program.Base.nir, prog, &gp->program.Base, + &c.prog_data.base.base, false); + + if (brw->gen >= 8) { + c.prog_data.static_vertex_count = !gp->program.Base.nir ? -1 : + nir_gs_count_vertices(gp->program.Base.nir); + } + + if (brw->gen >= 7) { + if (gp->program.OutputType == GL_POINTS) { + /* When the output type is points, the geometry shader may output data + * to multiple streams, and EndPrimitive() has no effect. So we + * configure the hardware to interpret the control data as stream ID. + */ + c.prog_data.control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID; - c.nr_bytes = c.nr_regs * REG_SIZE; + /* We only have to emit control bits if we are using streams */ + if (prog->Geom.UsesStreams) + c.control_data_bits_per_vertex = 2; + else + c.control_data_bits_per_vertex = 0; + } else { + /* When the output type is triangle_strip or line_strip, EndPrimitive() + * may be used to terminate the current strip and start a new one + * (similar to primitive restart), and outputting data to multiple + * streams is not supported. So we configure the hardware to interpret + * the control data as EndPrimitive information (a.k.a. "cut bits"). + */ + c.prog_data.control_data_format = GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT; + + /* We only need to output control data if the shader actually calls + * EndPrimitive(). + */ + c.control_data_bits_per_vertex = gp->program.UsesEndPrimitive ? 1 : 0; + } + } else { + /* There are no control data bits in gen6. */ + c.control_data_bits_per_vertex = 0; + + /* If it is using transform feedback, enable it */ + if (prog->TransformFeedback.NumVarying) + c.prog_data.gen6_xfb_enabled = true; + else + c.prog_data.gen6_xfb_enabled = false; + } + c.control_data_header_size_bits = + gp->program.VerticesOut * c.control_data_bits_per_vertex; - mem_ctx = NULL; - - /* Begin the compilation: + /* 1 HWORD = 32 bytes = 256 bits */ + c.prog_data.control_data_header_size_hwords = + ALIGN(c.control_data_header_size_bits, 256) / 256; + + GLbitfield64 outputs_written = gp->program.Base.OutputsWritten; + + brw_compute_vue_map(brw->intelScreen->devinfo, + &c.prog_data.base.vue_map, outputs_written, + prog ? prog->SeparateShader : false); + + /* Compute the output vertex size. + * + * From the Ivy Bridge PRM, Vol2 Part1 7.2.1.1 STATE_GS - Output Vertex + * Size (p168): + * + * [0,62] indicating [1,63] 16B units + * + * Specifies the size of each vertex stored in the GS output entry + * (following any Control Header data) as a number of 128-bit units + * (minus one). + * + * Programming Restrictions: The vertex size must be programmed as a + * multiple of 32B units with the following exception: Rendering is + * disabled (as per SOL stage state) and the vertex size output by the + * GS thread is 16B. + * + * If rendering is enabled (as per SOL state) the vertex size must be + * programmed as a multiple of 32B units. In other words, the only time + * software can program a vertex size with an odd number of 16B units + * is when rendering is disabled. + * + * Note: B=bytes in the above text. + * + * It doesn't seem worth the extra trouble to optimize the case where the + * vertex size is 16B (especially since this would require special-casing + * the GEN assembly that writes to the URB). So we just set the vertex + * size to a multiple of 32B (2 vec4's) in all cases. + * + * The maximum output vertex size is 62*16 = 992 bytes (31 hwords). We + * budget that as follows: + * + * 512 bytes for varyings (a varying component is 4 bytes and + * gl_MaxGeometryOutputComponents = 128) + * 16 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16 + * bytes) + * 16 bytes overhead for gl_Position (we allocate it a slot in the VUE + * even if it's not used) + * 32 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots + * whenever clip planes are enabled, even if the shader doesn't + * write to gl_ClipDistance) + * 16 bytes overhead since the VUE size must be a multiple of 32 bytes + * (see below)--this causes up to 1 VUE slot to be wasted + * 400 bytes available for varying packing overhead + * + * Worst-case varying packing overhead is 3/4 of a varying slot (12 bytes) + * per interpolation type, so this is plenty. + * */ - brw_init_compile(brw, &c.func, mem_ctx); + unsigned output_vertex_size_bytes = c.prog_data.base.vue_map.num_slots * 16; + assert(brw->gen == 6 || + output_vertex_size_bytes <= GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES); + c.prog_data.output_vertex_size_hwords = + ALIGN(output_vertex_size_bytes, 32) / 32; - c.func.single_program_flow = 1; + /* Compute URB entry size. The maximum allowed URB entry size is 32k. + * That divides up as follows: + * + * 64 bytes for the control data header (cut indices or StreamID bits) + * 4096 bytes for varyings (a varying component is 4 bytes and + * gl_MaxGeometryTotalOutputComponents = 1024) + * 4096 bytes overhead for VARYING_SLOT_PSIZ (each varying slot is 16 + * bytes/vertex and gl_MaxGeometryOutputVertices is 256) + * 4096 bytes overhead for gl_Position (we allocate it a slot in the VUE + * even if it's not used) + * 8192 bytes overhead for gl_ClipDistance (we allocate it 2 VUE slots + * whenever clip planes are enabled, even if the shader doesn't + * write to gl_ClipDistance) + * 4096 bytes overhead since the VUE size must be a multiple of 32 + * bytes (see above)--this causes up to 1 VUE slot to be wasted + * 8128 bytes available for varying packing overhead + * + * Worst-case varying packing overhead is 3/4 of a varying slot per + * interpolation type, which works out to 3072 bytes, so this would allow + * us to accommodate 2 interpolation types without any danger of running + * out of URB space. + * + * In practice, the risk of running out of URB space is very small, since + * the above figures are all worst-case, and most of them scale with the + * number of output vertices. So we'll just calculate the amount of space + * we need, and if it's too large, fail to compile. + * + * The above is for gen7+ where we have a single URB entry that will hold + * all the output. In gen6, we will have to allocate URB entries for every + * vertex we emit, so our URB entries only need to be large enough to hold + * a single vertex. Also, gen6 does not have a control data header. + */ + unsigned output_size_bytes; + if (brw->gen >= 7) { + output_size_bytes = + c.prog_data.output_vertex_size_hwords * 32 * gp->program.VerticesOut; + output_size_bytes += 32 * c.prog_data.control_data_header_size_hwords; + } else { + output_size_bytes = c.prog_data.output_vertex_size_hwords * 32; + } - /* For some reason the thread is spawned with only 4 channels - * unmasked. + /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output, + * which comes before the control header. */ - brw_set_mask_control(&c.func, BRW_MASK_DISABLE); + if (brw->gen >= 8) + output_size_bytes += 32; + + assert(output_size_bytes >= 1); + int max_output_size_bytes = GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES; + if (brw->gen == 6) + max_output_size_bytes = GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES; + if (output_size_bytes > max_output_size_bytes) + return false; - /* Note that primitives which don't require a GS program have - * already been weeded out by this stage: + /* URB entry sizes are stored as a multiple of 64 bytes in gen7+ and + * a multiple of 128 bytes in gen6. */ + if (brw->gen >= 7) + c.prog_data.base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; + else + c.prog_data.base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128; + + c.prog_data.output_topology = + get_hw_prim_for_gl_prim(gp->program.OutputType); - switch (key->primitive) { - case GL_QUADS: - brw_gs_quads( &c, key ); - break; - case GL_QUAD_STRIP: - brw_gs_quad_strip( &c, key ); - break; - case GL_LINE_LOOP: - brw_gs_lines( &c ); - break; - default: + /* The GLSL linker will have already matched up GS inputs and the outputs + * of prior stages. The driver does extend VS outputs in some cases, but + * only for legacy OpenGL or Gen4-5 hardware, neither of which offer + * geometry shader support. So we can safely ignore that. + * + * For SSO pipelines, we use a fixed VUE map layout based on variable + * locations, so we can rely on rendezvous-by-location making this work. + * + * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not + * written by previous stages and shows up via payload magic. + */ + GLbitfield64 inputs_read = + gp->program.Base.InputsRead & ~VARYING_BIT_PRIMITIVE_ID; + brw_compute_vue_map(brw->intelScreen->devinfo, + &c.input_vue_map, inputs_read, + prog->SeparateShader); + + /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we + * need to program a URB read length of ceiling(num_slots / 2). + */ + c.prog_data.base.urb_read_length = (c.input_vue_map.num_slots + 1) / 2; + + if (unlikely(INTEL_DEBUG & DEBUG_GS)) + brw_dump_ir("geometry", prog, gs, NULL); + + void *mem_ctx = ralloc_context(NULL); + unsigned program_size; + const unsigned *program = + brw_gs_emit(brw, prog, &c, mem_ctx, &program_size); + if (program == NULL) { ralloc_free(mem_ctx); - return; + return false; } - /* get the program - */ - program = brw_get_program(&c.func, &program_size); - - if (unlikely(INTEL_DEBUG & DEBUG_GS)) { - int i; - - printf("gs:\n"); - for (i = 0; i < program_size / sizeof(struct brw_instruction); i++) - brw_disasm(stdout, &((struct brw_instruction *)program)[i], - intel->gen); - printf("\n"); - } - - brw_upload_cache(&brw->cache, BRW_GS_PROG, - &c.key, sizeof(c.key), - program, program_size, - &c.prog_data, sizeof(c.prog_data), - &brw->gs.prog_offset, &brw->gs.prog_data); + /* Scratch space is used for register spilling */ + if (c.prog_data.base.base.total_scratch) { + brw_get_scratch_bo(brw, &stage_state->scratch_bo, + c.prog_data.base.base.total_scratch * + brw->max_gs_threads); + } + + brw_upload_cache(&brw->cache, BRW_CACHE_GS_PROG, + &c.key, sizeof(c.key), + program, program_size, + &c.prog_data, sizeof(c.prog_data), + &stage_state->prog_offset, &brw->gs.prog_data); ralloc_free(mem_ctx); + + return true; +} + +static bool +brw_gs_state_dirty(struct brw_context *brw) +{ + return brw_state_dirty(brw, + _NEW_TEXTURE, + BRW_NEW_GEOMETRY_PROGRAM | + BRW_NEW_TRANSFORM_FEEDBACK); } -static const GLenum gs_prim[GL_POLYGON+1] = { - GL_POINTS, - GL_LINES, - GL_LINE_LOOP, - GL_LINES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_TRIANGLES, - GL_QUADS, - GL_QUAD_STRIP, - GL_TRIANGLES -}; - -static void populate_key( struct brw_context *brw, - struct brw_gs_prog_key *key ) +static void +brw_gs_populate_key(struct brw_context *brw, + struct brw_gs_prog_key *key) { - struct gl_context *ctx = &brw->intel.ctx; - struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &brw->ctx; + struct brw_stage_state *stage_state = &brw->gs.base; + struct brw_geometry_program *gp = + (struct brw_geometry_program *) brw->geometry_program; + struct gl_program *prog = &gp->program.Base; memset(key, 0, sizeof(*key)); - /* CACHE_NEW_VS_PROG */ - key->attrs = brw->vs.prog_data->outputs_written; + key->program_string_id = gp->id; + + /* _NEW_TEXTURE */ + brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count, + &key->tex); +} + +void +brw_upload_gs_prog(struct brw_context *brw) +{ + struct gl_context *ctx = &brw->ctx; + struct gl_shader_program **current = ctx->_Shader->CurrentProgram; + struct brw_stage_state *stage_state = &brw->gs.base; + struct brw_gs_prog_key key; + /* BRW_NEW_GEOMETRY_PROGRAM */ + struct brw_geometry_program *gp = + (struct brw_geometry_program *) brw->geometry_program; + + if (!brw_gs_state_dirty(brw)) + return; - /* BRW_NEW_PRIMITIVE */ - key->primitive = gs_prim[brw->primitive]; + if (gp == NULL) { + /* No geometry shader. Vertex data just passes straight through. */ + if (brw->gen == 6 && + (brw->ctx.NewDriverState & BRW_NEW_TRANSFORM_FEEDBACK)) { + gen6_brw_upload_ff_gs_prog(brw); + return; + } - /* _NEW_LIGHT */ - key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION); - if (key->primitive == GL_QUADS && ctx->Light.ShadeModel != GL_FLAT) { - /* Provide consistent primitive order with brw_set_prim's - * optimization of single quads to trifans. + /* Other state atoms had better not try to access prog_data, since + * there's no GS program. */ - key->pv_first = GL_TRUE; + brw->gs.prog_data = NULL; + brw->gs.base.prog_data = NULL; + + return; } - key->need_gs_prog = (intel->gen >= 6) - ? 0 - : (brw->primitive == GL_QUADS || - brw->primitive == GL_QUAD_STRIP || - brw->primitive == GL_LINE_LOOP); + brw_gs_populate_key(brw, &key); + + if (!brw_search_cache(&brw->cache, BRW_CACHE_GS_PROG, + &key, sizeof(key), + &stage_state->prog_offset, &brw->gs.prog_data)) { + bool success = brw_codegen_gs_prog(brw, current[MESA_SHADER_GEOMETRY], + gp, &key); + assert(success); + (void)success; + } + brw->gs.base.prog_data = &brw->gs.prog_data->base.base; } -/* Calculate interpolants for triangle and line rasterization. - */ -static void prepare_gs_prog(struct brw_context *brw) +bool +brw_gs_precompile(struct gl_context *ctx, + struct gl_shader_program *shader_prog, + struct gl_program *prog) { + struct brw_context *brw = brw_context(ctx); struct brw_gs_prog_key key; - /* Populate the key: - */ - populate_key(brw, &key); + uint32_t old_prog_offset = brw->gs.base.prog_offset; + struct brw_gs_prog_data *old_prog_data = brw->gs.prog_data; + bool success; - if (brw->gs.prog_active != key.need_gs_prog) { - brw->state.dirty.cache |= CACHE_NEW_GS_PROG; - brw->gs.prog_active = key.need_gs_prog; - } + struct gl_geometry_program *gp = (struct gl_geometry_program *) prog; + struct brw_geometry_program *bgp = brw_geometry_program(gp); - if (brw->gs.prog_active) { - if (!brw_search_cache(&brw->cache, BRW_GS_PROG, - &key, sizeof(key), - &brw->gs.prog_offset, &brw->gs.prog_data)) { - compile_gs_prog( brw, &key ); - } - } -} + memset(&key, 0, sizeof(key)); + + brw_setup_tex_for_precompile(brw, &key.tex, prog); + key.program_string_id = bgp->id; + success = brw_codegen_gs_prog(brw, shader_prog, bgp, &key); -const struct brw_tracked_state brw_gs_prog = { - .dirty = { - .mesa = _NEW_LIGHT, - .brw = BRW_NEW_PRIMITIVE, - .cache = CACHE_NEW_VS_PROG - }, - .prepare = prepare_gs_prog -}; + brw->gs.base.prog_offset = old_prog_offset; + brw->gs.prog_data = old_prog_data; + + return success; +}