X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_nir_uniforms.cpp;h=69da83ad364bbddfb2750fbb7b43f5d7cff63b47;hb=156d2c6e621d836c4d45c636b87669e1de3d4464;hp=0849ca40046961abb5bc48420a427a6dbf4db5e3;hpb=d5c9955d3eaa7311e2b2350b6964bae516c7b7b2;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp index 0849ca40046..69da83ad364 100644 --- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp +++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp @@ -21,9 +21,9 @@ * IN THE SOFTWARE. */ -#include "brw_shader.h" -#include "brw_nir.h" -#include "glsl/ir_uniform.h" +#include "compiler/brw_nir.h" +#include "compiler/glsl/ir_uniform.h" +#include "brw_program.h" static void brw_nir_setup_glsl_builtin_uniform(nir_variable *var, @@ -40,7 +40,7 @@ brw_nir_setup_glsl_builtin_uniform(nir_variable *var, * get the same index back here. */ int index = _mesa_add_state_reference(prog->Parameters, - (gl_state_index *)slots[i].tokens); + slots[i].tokens); /* Add each of the unique swizzles of the element as a parameter. * This'll end up matching the expected layout of the @@ -61,30 +61,83 @@ brw_nir_setup_glsl_builtin_uniform(nir_variable *var, last_swiz = swiz; stage_prog_data->param[uniform_index++] = - &prog->Parameters->ParameterValues[index][swiz]; + BRW_PARAM_PARAMETER(index, swiz); } } } +static void +setup_vec4_image_param(uint32_t *params, uint32_t idx, + unsigned offset, unsigned n) +{ + assert(offset % sizeof(uint32_t) == 0); + for (unsigned i = 0; i < n; ++i) + params[i] = BRW_PARAM_IMAGE(idx, offset / sizeof(uint32_t) + i); + + for (unsigned i = n; i < 4; ++i) + params[i] = BRW_PARAM_BUILTIN_ZERO; +} + +static void +brw_setup_image_uniform_values(gl_shader_stage stage, + struct brw_stage_prog_data *stage_prog_data, + unsigned param_start_index, + const gl_uniform_storage *storage) +{ + uint32_t *param = &stage_prog_data->param[param_start_index]; + + for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) { + const unsigned image_idx = storage->opaque[stage].index + i; + + /* Upload the brw_image_param structure. The order is expected to match + * the BRW_IMAGE_PARAM_*_OFFSET defines. + */ + setup_vec4_image_param(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET, + image_idx, + offsetof(brw_image_param, surface_idx), 1); + setup_vec4_image_param(param + BRW_IMAGE_PARAM_OFFSET_OFFSET, + image_idx, + offsetof(brw_image_param, offset), 2); + setup_vec4_image_param(param + BRW_IMAGE_PARAM_SIZE_OFFSET, + image_idx, + offsetof(brw_image_param, size), 3); + setup_vec4_image_param(param + BRW_IMAGE_PARAM_STRIDE_OFFSET, + image_idx, + offsetof(brw_image_param, stride), 4); + setup_vec4_image_param(param + BRW_IMAGE_PARAM_TILING_OFFSET, + image_idx, + offsetof(brw_image_param, tiling), 3); + setup_vec4_image_param(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET, + image_idx, + offsetof(brw_image_param, swizzling), 2); + param += BRW_IMAGE_PARAM_SIZE; + + brw_mark_surface_used( + stage_prog_data, + stage_prog_data->binding_table.image_start + image_idx); + } +} + static void brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var, - struct gl_shader_program *shader_prog, + const struct gl_program *prog, struct brw_stage_prog_data *stage_prog_data, bool is_scalar) { int namelen = strlen(var->name); /* The data for our (non-builtin) uniforms is stored in a series of - * gl_uniform_driver_storage structs for each subcomponent that + * gl_uniform_storage structs for each subcomponent that * glGetUniformLocation() could name. We know it's been set up in the same * order we'd walk the type, so walk the list of storage and find anything * with our name, or the prefix of a component that starts with our name. */ unsigned uniform_index = var->data.driver_location / 4; - for (unsigned u = 0; u < shader_prog->NumUniformStorage; u++) { - struct gl_uniform_storage *storage = &shader_prog->UniformStorage[u]; + for (unsigned u = 0; u < prog->sh.data->NumUniformStorage; u++) { + struct gl_uniform_storage *storage = + &prog->sh.data->UniformStorage[u]; - if (storage->builtin) + if (storage->builtin || storage->type->is_sampler()) continue; if (strncmp(var->name, storage->name, namelen) != 0 || @@ -104,18 +157,28 @@ brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var, unsigned vector_count = (MAX2(storage->array_elements, 1) * storage->type->matrix_columns); unsigned vector_size = storage->type->vector_elements; + unsigned max_vector_size = 4; + if (storage->type->base_type == GLSL_TYPE_DOUBLE || + storage->type->base_type == GLSL_TYPE_UINT64 || + storage->type->base_type == GLSL_TYPE_INT64) { + vector_size *= 2; + if (vector_size > 4) + max_vector_size = 8; + } for (unsigned s = 0; s < vector_count; s++) { unsigned i; for (i = 0; i < vector_size; i++) { - stage_prog_data->param[uniform_index++] = components++; + uint32_t idx = components - prog->sh.data->UniformDataSlots; + stage_prog_data->param[uniform_index++] = BRW_PARAM_UNIFORM(idx); + components++; } if (!is_scalar) { /* Pad out with zeros if needed (only needed for vec4) */ - for (; i < 4; i++) { - static const gl_constant_value zero = { 0.0 }; - stage_prog_data->param[uniform_index++] = &zero; + for (; i < max_vector_size; i++) { + stage_prog_data->param[uniform_index++] = + BRW_PARAM_BUILTIN_ZERO; } } } @@ -124,12 +187,15 @@ brw_nir_setup_glsl_uniform(gl_shader_stage stage, nir_variable *var, } void -brw_nir_setup_glsl_uniforms(nir_shader *shader, - struct gl_shader_program *shader_prog, +brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader, const struct gl_program *prog, struct brw_stage_prog_data *stage_prog_data, bool is_scalar) { + unsigned nr_params = shader->num_uniforms / 4; + stage_prog_data->nr_params = nr_params; + stage_prog_data->param = rzalloc_array(mem_ctx, uint32_t, nr_params); + nir_foreach_variable(var, &shader->uniforms) { /* UBO's, atomics and samplers don't take up space in the uniform file */ @@ -140,29 +206,28 @@ brw_nir_setup_glsl_uniforms(nir_shader *shader, brw_nir_setup_glsl_builtin_uniform(var, prog, stage_prog_data, is_scalar); } else { - brw_nir_setup_glsl_uniform(shader->stage, var, shader_prog, + brw_nir_setup_glsl_uniform(shader->info.stage, var, prog, stage_prog_data, is_scalar); } } } void -brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog, +brw_nir_setup_arb_uniforms(void *mem_ctx, nir_shader *shader, + struct gl_program *prog, struct brw_stage_prog_data *stage_prog_data) { struct gl_program_parameter_list *plist = prog->Parameters; -#ifndef NDEBUG - if (!shader->uniforms.is_empty()) { - /* For ARB programs, only a single "parameters" variable is generated to - * support uniform data. - */ - assert(shader->uniforms.length() == 1); - nir_variable *var = (nir_variable *) shader->uniforms.get_head(); - assert(strcmp(var->name, "parameters") == 0); - assert(var->type->array_size() == (int)plist->NumParameters); - } -#endif + unsigned nr_params = plist->NumParameters * 4; + stage_prog_data->nr_params = nr_params; + stage_prog_data->param = rzalloc_array(mem_ctx, uint32_t, nr_params); + + /* For ARB programs, prog_to_nir generates a single "parameters" variable + * for all uniform data. nir_lower_wpos_ytransform may also create an + * additional variable. + */ + assert(shader->uniforms.length() <= 2); for (unsigned p = 0; p < plist->NumParameters; p++) { /* Parameters should be either vec4 uniforms or single component @@ -172,12 +237,35 @@ brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog, assert(plist->Parameters[p].Size <= 4); unsigned i; - for (i = 0; i < plist->Parameters[p].Size; i++) { - stage_prog_data->param[4 * p + i] = &plist->ParameterValues[p][i]; - } - for (; i < 4; i++) { - static const gl_constant_value zero = { 0.0 }; - stage_prog_data->param[4 * p + i] = &zero; - } + for (i = 0; i < plist->Parameters[p].Size; i++) + stage_prog_data->param[4 * p + i] = BRW_PARAM_PARAMETER(p, i); + for (; i < 4; i++) + stage_prog_data->param[4 * p + i] = BRW_PARAM_BUILTIN_ZERO; + } +} + +void +brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir) +{ + nir_foreach_variable_safe(var, &nir->system_values) { + if (var->data.location != SYSTEM_VALUE_VERTICES_IN) + continue; + + gl_state_index16 tokens[STATE_LENGTH] = { + STATE_INTERNAL, + nir->info.stage == MESA_SHADER_TESS_CTRL ? + (gl_state_index16)STATE_TCS_PATCH_VERTICES_IN : + (gl_state_index16)STATE_TES_PATCH_VERTICES_IN, + }; + var->num_state_slots = 1; + var->state_slots = + ralloc_array(var, nir_state_slot, var->num_state_slots); + memcpy(var->state_slots[0].tokens, tokens, sizeof(tokens)); + var->state_slots[0].swizzle = SWIZZLE_XXXX; + + var->data.mode = nir_var_uniform; + var->data.location = -1; + exec_node_remove(&var->node); + exec_list_push_tail(&nir->uniforms, &var->node); } }