X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_shader.cpp;h=f4f1334d9ef56d6c7e03f4f03eae77c8e98241a6;hb=2747f6a1f9d27826346d330cceef44b800267bcb;hp=c0d6aa27eeb48ec4989e44a4f53f3e4d5e94027d;hpb=65511e5f22e2ba0a5ebd9210319a55d80ea5334e;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index c0d6aa27eeb..f4f1334d9ef 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -28,6 +28,7 @@ extern "C" { #include "brw_vs.h" #include "brw_vec4_gs.h" #include "brw_fs.h" +#include "brw_cfg.h" #include "glsl/ir_optimization.h" #include "glsl/glsl_parser_extras.h" #include "main/shaderapi.h" @@ -120,6 +121,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) unsigned int stage; for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) { + const struct gl_shader_compiler_options *options = + &ctx->ShaderCompilerOptions[stage]; struct brw_shader *shader = (struct brw_shader *)shProg->_LinkedShaders[stage]; @@ -127,7 +130,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) continue; struct gl_program *prog = - ctx->Driver.NewProgram(ctx, _mesa_program_index_to_target(stage), + ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage), shader->base.Name); if (!prog) return false; @@ -135,82 +138,71 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog); - void *mem_ctx = ralloc_context(NULL); bool progress; - if (shader->ir) - ralloc_free(shader->ir); - shader->ir = new(shader) exec_list; - clone_ir_list(mem_ctx, shader->ir, shader->base.ir); - /* lower_packing_builtins() inserts arithmetic instructions, so it * must precede lower_instructions(). */ - brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->ir); - do_mat_op_to_vec(shader->ir); + brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir); + do_mat_op_to_vec(shader->base.ir); const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0; - const int lrp_to_arith = brw->gen < 6 ? LRP_TO_ARITH : 0; - lower_instructions(shader->ir, + lower_instructions(shader->base.ir, MOD_TO_FRACT | DIV_TO_MUL_RCP | SUB_TO_ADD_NEG | EXP_TO_EXP2 | LOG_TO_LOG2 | bitfield_insert | - lrp_to_arith | LDEXP_TO_ARITH); /* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this, * if-statements need to be flattened. */ if (brw->gen < 6) - lower_if_to_cond_assign(shader->ir, 16); - - do_lower_texture_projection(shader->ir); - brw_lower_texture_gradients(brw, shader->ir); - do_vec_index_to_cond_assign(shader->ir); - lower_vector_insert(shader->ir, true); - brw_do_cubemap_normalize(shader->ir); - brw_do_lower_offset_arrays(shader->ir); - brw_do_lower_unnormalized_offset(shader->ir); - lower_noise(shader->ir); - lower_quadop_vector(shader->ir, false); - - bool input = true; - bool output = stage == MESA_SHADER_FRAGMENT; - bool temp = stage == MESA_SHADER_FRAGMENT; - bool uniform = false; + lower_if_to_cond_assign(shader->base.ir, 16); + + do_lower_texture_projection(shader->base.ir); + brw_lower_texture_gradients(brw, shader->base.ir); + do_vec_index_to_cond_assign(shader->base.ir); + lower_vector_insert(shader->base.ir, true); + brw_do_cubemap_normalize(shader->base.ir); + lower_offset_arrays(shader->base.ir); + brw_do_lower_unnormalized_offset(shader->base.ir); + lower_noise(shader->base.ir); + lower_quadop_vector(shader->base.ir, false); bool lowered_variable_indexing = - lower_variable_index_to_cond_assign(shader->ir, - input, output, temp, uniform); + lower_variable_index_to_cond_assign(shader->base.ir, + options->EmitNoIndirectInput, + options->EmitNoIndirectOutput, + options->EmitNoIndirectTemp, + options->EmitNoIndirectUniform); if (unlikely(brw->perf_debug && lowered_variable_indexing)) { perf_debug("Unsupported form of variable indexing in FS; falling " "back to very inefficient code generation\n"); } - /* FINISHME: Do this before the variable index lowering. */ - lower_ubo_reference(&shader->base, shader->ir); + lower_ubo_reference(&shader->base, shader->base.ir); do { progress = false; if (stage == MESA_SHADER_FRAGMENT) { - brw_do_channel_expressions(shader->ir); - brw_do_vector_splitting(shader->ir); + brw_do_channel_expressions(shader->base.ir); + brw_do_vector_splitting(shader->base.ir); } - progress = do_lower_jumps(shader->ir, true, true, + progress = do_lower_jumps(shader->base.ir, true, true, true, /* main return */ false, /* continue */ false /* loops */ ) || progress; - progress = do_common_optimization(shader->ir, true, true, 32, - &ctx->ShaderCompilerOptions[stage]) + progress = do_common_optimization(shader->base.ir, true, true, + options, ctx->Const.NativeIntegers) || progress; } while (progress); @@ -221,7 +213,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) * too late. At that point, the values for the built-in uniforms won't * get sent to the shader. */ - foreach_list(node, shader->ir) { + foreach_list(node, shader->base.ir) { ir_variable *var = ((ir_instruction *) node)->as_variable(); if ((var == NULL) || (var->data.mode != ir_var_uniform) @@ -237,12 +229,9 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) } } - validate_ir_tree(shader->ir); - - reparent_ir(shader->ir, shader->ir); - ralloc_free(mem_ctx); + validate_ir_tree(shader->base.ir); - do_set_program_inouts(shader->ir, prog, shader->base.Type); + do_set_program_inouts(shader->base.ir, prog, shader->base.Stage); prog->SamplersUsed = shader->base.active_samplers; _mesa_update_shader_textures_used(shProg, prog); @@ -259,27 +248,27 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) _mesa_reference_program(ctx, &prog, NULL); - if (ctx->Shader.Flags & GLSL_DUMP) { - printf("\n"); - printf("GLSL IR for linked %s program %d:\n", - _mesa_progshader_enum_to_string(shader->base.Type), shProg->Name); - _mesa_print_ir(shader->base.ir, NULL); - printf("\n"); + if (ctx->_Shader->Flags & GLSL_DUMP) { + fprintf(stderr, "\n"); + fprintf(stderr, "GLSL IR for linked %s program %d:\n", + _mesa_shader_stage_to_string(shader->base.Stage), + shProg->Name); + _mesa_print_ir(stderr, shader->base.ir, NULL); + fprintf(stderr, "\n"); } } - if (ctx->Shader.Flags & GLSL_DUMP) { + if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) { for (unsigned i = 0; i < shProg->NumShaders; i++) { const struct gl_shader *sh = shProg->Shaders[i]; if (!sh) continue; - printf("GLSL %s shader %d source for linked program %d:\n", - _mesa_progshader_enum_to_string(sh->Type), - i, - shProg->Name); - printf("%s", sh->Source); - printf("\n"); + fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n", + _mesa_shader_stage_to_string(sh->Stage), + i, shProg->Name); + fprintf(stderr, "%s", sh->Source); + fprintf(stderr, "\n"); } } @@ -311,6 +300,8 @@ brw_type_for_base_type(const struct glsl_type *type) * way to trip up if we don't. */ return BRW_REGISTER_TYPE_UD; + case GLSL_TYPE_IMAGE: + return BRW_REGISTER_TYPE_UD; case GLSL_TYPE_VOID: case GLSL_TYPE_ERROR: case GLSL_TYPE_INTERFACE: @@ -414,6 +405,8 @@ brw_instruction_name(enum opcode op) switch (op) { case FS_OPCODE_FB_WRITE: return "fb_write"; + case FS_OPCODE_BLORP_FB_WRITE: + return "blorp_fb_write"; case SHADER_OPCODE_RCP: return "rcp"; @@ -448,8 +441,10 @@ brw_instruction_name(enum opcode op) return "txs"; case FS_OPCODE_TXB: return "txb"; - case SHADER_OPCODE_TXF_MS: - return "txf_ms"; + case SHADER_OPCODE_TXF_CMS: + return "txf_cms"; + case SHADER_OPCODE_TXF_UMS: + return "txf_ums"; case SHADER_OPCODE_TXF_MCS: return "txf_mcs"; case SHADER_OPCODE_TG4: @@ -529,6 +524,8 @@ brw_instruction_name(enum opcode op) return "prepare_channel_masks"; case GS_OPCODE_SET_CHANNEL_MASKS: return "set_channel_masks"; + case GS_OPCODE_GET_INSTANCE_ID: + return "get_instance_id"; default: /* Yes, this leaks. It's in debug code, it should never occur, and if @@ -539,14 +536,30 @@ brw_instruction_name(enum opcode op) } } +backend_visitor::backend_visitor(struct brw_context *brw, + struct gl_shader_program *shader_prog, + struct gl_program *prog, + struct brw_stage_prog_data *stage_prog_data, + gl_shader_stage stage) + : brw(brw), + ctx(&brw->ctx), + shader(shader_prog ? + (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL), + shader_prog(shader_prog), + prog(prog), + stage_prog_data(stage_prog_data) +{ +} + bool -backend_instruction::is_tex() +backend_instruction::is_tex() const { return (opcode == SHADER_OPCODE_TEX || opcode == FS_OPCODE_TXB || opcode == SHADER_OPCODE_TXD || opcode == SHADER_OPCODE_TXF || - opcode == SHADER_OPCODE_TXF_MS || + opcode == SHADER_OPCODE_TXF_CMS || + opcode == SHADER_OPCODE_TXF_UMS || opcode == SHADER_OPCODE_TXF_MCS || opcode == SHADER_OPCODE_TXL || opcode == SHADER_OPCODE_TXS || @@ -556,7 +569,7 @@ backend_instruction::is_tex() } bool -backend_instruction::is_math() +backend_instruction::is_math() const { return (opcode == SHADER_OPCODE_RCP || opcode == SHADER_OPCODE_RSQ || @@ -571,7 +584,7 @@ backend_instruction::is_math() } bool -backend_instruction::is_control_flow() +backend_instruction::is_control_flow() const { switch (opcode) { case BRW_OPCODE_DO: @@ -588,7 +601,7 @@ backend_instruction::is_control_flow() } bool -backend_instruction::can_do_source_mods() +backend_instruction::can_do_source_mods() const { switch (opcode) { case BRW_OPCODE_ADDC: @@ -606,6 +619,73 @@ backend_instruction::can_do_source_mods() } } +bool +backend_instruction::can_do_saturate() const +{ + switch (opcode) { + case BRW_OPCODE_ADD: + case BRW_OPCODE_ASR: + case BRW_OPCODE_AVG: + case BRW_OPCODE_DP2: + case BRW_OPCODE_DP3: + case BRW_OPCODE_DP4: + case BRW_OPCODE_DPH: + case BRW_OPCODE_F16TO32: + case BRW_OPCODE_F32TO16: + case BRW_OPCODE_LINE: + case BRW_OPCODE_LRP: + case BRW_OPCODE_MAC: + case BRW_OPCODE_MACH: + case BRW_OPCODE_MAD: + case BRW_OPCODE_MATH: + case BRW_OPCODE_MOV: + case BRW_OPCODE_MUL: + case BRW_OPCODE_PLN: + case BRW_OPCODE_RNDD: + case BRW_OPCODE_RNDE: + case BRW_OPCODE_RNDU: + case BRW_OPCODE_RNDZ: + case BRW_OPCODE_SEL: + case BRW_OPCODE_SHL: + case BRW_OPCODE_SHR: + case FS_OPCODE_LINTERP: + case SHADER_OPCODE_COS: + case SHADER_OPCODE_EXP2: + case SHADER_OPCODE_LOG2: + case SHADER_OPCODE_POW: + case SHADER_OPCODE_RCP: + case SHADER_OPCODE_RSQ: + case SHADER_OPCODE_SIN: + case SHADER_OPCODE_SQRT: + return true; + default: + return false; + } +} + +bool +backend_instruction::reads_accumulator_implicitly() const +{ + switch (opcode) { + case BRW_OPCODE_MAC: + case BRW_OPCODE_MACH: + case BRW_OPCODE_SADA2: + return true; + default: + return false; + } +} + +bool +backend_instruction::writes_accumulator_implicitly(int gen) const +{ + return writes_accumulator || + (gen < 6 && + ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) || + (opcode >= FS_OPCODE_DDX && opcode <= FS_OPCODE_LINTERP && + opcode != FS_OPCODE_CINTERP))); +} + bool backend_instruction::has_side_effects() const { @@ -623,7 +703,7 @@ backend_visitor::dump_instructions() int ip = 0; foreach_list(node, &this->instructions) { backend_instruction *inst = (backend_instruction *)node; - printf("%d: ", ip++); + fprintf(stderr, "%d: ", ip++); dump_instruction(inst); } } @@ -679,5 +759,58 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table assert(next_binding_table_offset <= BRW_MAX_SURFACES); - /* prog_data->base.binding_table.size will be set by mark_surface_used. */ + /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */ +} + +void annotate(struct brw_context *brw, + struct annotation_info *annotation, cfg_t *cfg, + backend_instruction *inst, unsigned offset) +{ + if (annotation->ann_size <= annotation->ann_count) { + annotation->ann_size = MAX2(1024, annotation->ann_size * 2); + annotation->ann = reralloc(annotation->mem_ctx, annotation->ann, + struct annotation, annotation->ann_size); + if (!annotation->ann) + return; + } + + struct annotation *ann = &annotation->ann[annotation->ann_count++]; + ann->offset = offset; + ann->ir = inst->ir; + ann->annotation = inst->annotation; + + if (cfg->blocks[annotation->cur_block]->start == inst) { + ann->block_start = cfg->blocks[annotation->cur_block]; + } + + /* There is no hardware DO instruction on Gen6+, so since DO always + * starts a basic block, we need to set the .block_start of the next + * instruction's annotation with a pointer to the bblock started by + * the DO. + * + * There's also only complication from emitting an annotation without + * a corresponding hardware instruction to disassemble. + */ + if (brw->gen >= 6 && inst->opcode == BRW_OPCODE_DO) { + annotation->ann_count--; + } + + if (cfg->blocks[annotation->cur_block]->end == inst) { + ann->block_end = cfg->blocks[annotation->cur_block]; + annotation->cur_block++; + } +} + +void +annotation_finalize(struct annotation_info *annotation, + unsigned next_inst_offset) +{ + if (!annotation->ann_count) + return; + + if (annotation->ann_count == annotation->ann_size) { + annotation->ann = reralloc(annotation->mem_ctx, annotation->ann, + struct annotation, annotation->ann_size + 1); + } + annotation->ann[annotation->ann_count].offset = next_inst_offset; }