X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_shader.h;h=82374a46c1887ca5faeee2ae91ff2bb32b52e27a;hb=b6bb3b9bcd8fb03c8d307cafa34bc9ed8a4e2f28;hp=ccccf4d6938af19d0e824acdf57757ef3012a6f9;hpb=640c472fd075814972b1276c5b0ed3a769aacda5;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index ccccf4d6938..82374a46c18 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -21,112 +21,48 @@ * IN THE SOFTWARE. */ +#pragma once + #include #include "brw_reg.h" #include "brw_defines.h" -#include "main/compiler.h" -#include "glsl/ir.h" -#include "program/prog_parameter.h" +#include "brw_context.h" #ifdef __cplusplus #include "brw_ir_allocator.h" #endif -#pragma once - #define MAX_SAMPLER_MESSAGE_SIZE 11 #define MAX_VGRF_SIZE 16 -struct brw_compiler { - const struct brw_device_info *devinfo; - - struct { - struct ra_regs *regs; - - /** - * Array of the ra classes for the unaligned contiguous register - * block sizes used. - */ - int *classes; - - /** - * Mapping for register-allocated objects in *regs to the first - * GRF for that object. - */ - uint8_t *ra_reg_to_grf; - } vec4_reg_set; - - struct { - struct ra_regs *regs; - - /** - * Array of the ra classes for the unaligned contiguous register - * block sizes used, indexed by register size. - */ - int classes[16]; - - /** - * Mapping from classes to ra_reg ranges. Each of the per-size - * classes corresponds to a range of ra_reg nodes. This array stores - * those ranges in the form of first ra_reg in each class and the - * total number of ra_reg elements in the last array element. This - * way the range of the i'th class is given by: - * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] ) - */ - int class_to_ra_reg_range[17]; - - /** - * Mapping for register-allocated objects in *regs to the first - * GRF for that object. - */ - uint8_t *ra_reg_to_grf; - - /** - * ra class for the aligned pairs we use for PLN, which doesn't - * appear in *classes. - */ - int aligned_pairs_class; - } fs_reg_sets[2]; - - void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); - void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); - - bool scalar_vs; - struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES]; -}; +#ifdef __cplusplus +struct backend_reg : private brw_reg +{ + backend_reg() {} + backend_reg(const struct brw_reg ®) : brw_reg(reg) {} -enum PACKED register_file { - BAD_FILE, - GRF, - MRF, - IMM, - HW_REG, /* a struct brw_reg */ - ATTR, - UNIFORM, /* prog_data->params[reg] */ -}; + const brw_reg &as_brw_reg() const + { + assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); + assert(reg_offset == 0); + return static_cast(*this); + } + + brw_reg &as_brw_reg() + { + assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM); + assert(reg_offset == 0); + return static_cast(*this); + } + + bool equals(const backend_reg &r) const; -struct backend_reg -{ -#ifdef __cplusplus bool is_zero() const; bool is_one() const; bool is_negative_one() const; bool is_null() const; bool is_accumulator() const; bool in_range(const backend_reg &r, unsigned n) const; -#endif - - enum register_file file; /**< Register file: GRF, MRF, IMM. */ - enum brw_reg_type type; /**< Register type: BRW_REGISTER_TYPE_* */ - - /** - * Register number. - * - * For GRF, it's a virtual register number until register allocation. - * - * For MRF, it's the hardware register. - */ - uint16_t reg; /** * Offset within the virtual register. @@ -139,11 +75,26 @@ struct backend_reg */ uint16_t reg_offset; - struct brw_reg fixed_hw_reg; - - bool negate; - bool abs; + using brw_reg::type; + using brw_reg::file; + using brw_reg::negate; + using brw_reg::abs; + using brw_reg::address_mode; + using brw_reg::subnr; + using brw_reg::nr; + + using brw_reg::swizzle; + using brw_reg::writemask; + using brw_reg::indirect_offset; + using brw_reg::vstride; + using brw_reg::width; + using brw_reg::hstride; + + using brw_reg::f; + using brw_reg::d; + using brw_reg::ud; }; +#endif struct cfg_t; struct bblock_t; @@ -172,6 +123,12 @@ struct backend_instruction : public exec_node { * optimize these out unless you know what you are doing. */ bool has_side_effects() const; + + /** + * True if the instruction might be affected by side effects of other + * instructions. + */ + bool is_volatile() const; #else struct backend_instruction { struct exec_node link; @@ -218,16 +175,14 @@ enum instruction_scheduler_mode { SCHEDULE_POST, }; -class backend_shader { +struct backend_shader { protected: backend_shader(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, - struct gl_shader_program *shader_prog, - struct gl_program *prog, - struct brw_stage_prog_data *stage_prog_data, - gl_shader_stage stage); + const nir_shader *shader, + struct brw_stage_prog_data *stage_prog_data); public: @@ -235,9 +190,7 @@ public: void *log_data; /* Passed to compiler->*_log functions */ const struct brw_device_info * const devinfo; - struct brw_shader * const shader; - struct gl_shader_program * const shader_prog; - struct gl_program * const prog; + const nir_shader *nir; struct brw_stage_prog_data * const stage_prog_data; /** ralloc context for temporary data used during compile */ @@ -266,19 +219,18 @@ public: void calculate_cfg(); void invalidate_cfg(); - void assign_common_binding_table_offsets(uint32_t next_binding_table_offset); - virtual void invalidate_live_intervals() = 0; - - virtual void setup_vec4_uniform_value(unsigned param_offset, - const gl_constant_value *values, - unsigned n) = 0; - void setup_image_uniform_values(unsigned param_offset, - const gl_uniform_storage *storage); }; uint32_t brw_texture_offset(int *offsets, unsigned num_components); +void brw_setup_image_uniform_values(gl_shader_stage stage, + struct brw_stage_prog_data *stage_prog_data, + unsigned param_start_index, + const gl_uniform_storage *storage); + +#else +struct backend_shader; #endif /* __cplusplus */ enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type); @@ -289,16 +241,41 @@ bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg); bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg); bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg); +bool opt_predicated_break(struct backend_shader *s); + #ifdef __cplusplus extern "C" { #endif -struct brw_compiler * -brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo); +/** + * Scratch data used when compiling a GLSL geometry shader. + */ +struct brw_gs_compile +{ + struct brw_gs_prog_key key; + struct brw_vue_map input_vue_map; + + unsigned control_data_bits_per_vertex; + unsigned control_data_header_size_bits; +}; + +void +brw_assign_common_binding_table_offsets(gl_shader_stage stage, + const struct brw_device_info *devinfo, + const struct gl_shader_program *shader_prog, + const struct gl_program *prog, + struct brw_stage_prog_data *stage_prog_data, + uint32_t next_binding_table_offset); bool brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); +bool brw_tcs_precompile(struct gl_context *ctx, + struct gl_shader_program *shader_prog, + struct gl_program *prog); +bool brw_tes_precompile(struct gl_context *ctx, + struct gl_shader_program *shader_prog, + struct gl_program *prog); bool brw_gs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); @@ -309,8 +286,12 @@ bool brw_cs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); +GLboolean brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog); +struct gl_shader *brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type); + int type_size_scalar(const struct glsl_type *type); int type_size_vec4(const struct glsl_type *type); +int type_size_vec4_times_4(const struct glsl_type *type); #ifdef __cplusplus }