X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_shader.h;h=925072f1349def7ede3ffea82c602d6cfd38bb18;hb=5c0436dbf87fef76ba67456f215d9285c38f1816;hp=7bff186dc49fc512ab49b798b40edd5782efb047;hpb=e8a6f2ad65b03eac7c030b2cd4955a162739870b;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 7bff186dc49..925072f1349 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -26,6 +26,7 @@ #include "brw_defines.h" #include "main/compiler.h" #include "glsl/ir.h" +#include "program/prog_parameter.h" #ifdef __cplusplus #include "brw_ir_allocator.h" @@ -36,6 +37,64 @@ #define MAX_SAMPLER_MESSAGE_SIZE 11 #define MAX_VGRF_SIZE 16 +struct brw_compiler { + const struct brw_device_info *devinfo; + + struct { + struct ra_regs *regs; + + /** + * Array of the ra classes for the unaligned contiguous register + * block sizes used. + */ + int *classes; + + /** + * Mapping for register-allocated objects in *regs to the first + * GRF for that object. + */ + uint8_t *ra_reg_to_grf; + } vec4_reg_set; + + struct { + struct ra_regs *regs; + + /** + * Array of the ra classes for the unaligned contiguous register + * block sizes used, indexed by register size. + */ + int classes[16]; + + /** + * Mapping from classes to ra_reg ranges. Each of the per-size + * classes corresponds to a range of ra_reg nodes. This array stores + * those ranges in the form of first ra_reg in each class and the + * total number of ra_reg elements in the last array element. This + * way the range of the i'th class is given by: + * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] ) + */ + int class_to_ra_reg_range[17]; + + /** + * Mapping for register-allocated objects in *regs to the first + * GRF for that object. + */ + uint8_t *ra_reg_to_grf; + + /** + * ra class for the aligned pairs we use for PLN, which doesn't + * appear in *classes. + */ + int aligned_pairs_class; + } fs_reg_sets[2]; + + void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); + void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3); + + bool scalar_vs; + struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES]; +}; + enum PACKED register_file { BAD_FILE, GRF, @@ -54,6 +113,7 @@ struct backend_reg bool is_negative_one() const; bool is_null() const; bool is_accumulator() const; + bool in_range(const backend_reg &r, unsigned n) const; #endif enum register_file file; /**< Register file: GRF, MRF, IMM. */ @@ -77,7 +137,7 @@ struct backend_reg * * For uniforms, this is in units of 1 float. */ - int reg_offset; + uint16_t reg_offset; struct brw_reg fixed_hw_reg; @@ -94,11 +154,12 @@ struct backend_instruction : public exec_node { bool is_tex() const; bool is_math() const; bool is_control_flow() const; + bool is_commutative() const; bool can_do_source_mods() const; bool can_do_saturate() const; bool can_do_cmod() const; bool reads_accumulator_implicitly() const; - bool writes_accumulator_implicitly(struct brw_context *brw) const; + bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const; void remove(bblock_t *block); void insert_after(bblock_t *block, backend_instruction *inst); @@ -138,12 +199,14 @@ struct backend_instruction { bool no_dd_check:1; bool saturate:1; bool shadow_compare:1; - bool header_present:1; /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional * mod and predication. */ unsigned flag_subreg:1; + + /** The number of hardware registers used for a message header. */ + uint8_t header_size; }; #ifdef __cplusplus @@ -155,19 +218,23 @@ enum instruction_scheduler_mode { SCHEDULE_POST, }; -class backend_visitor : public ir_visitor { +class backend_shader { protected: - backend_visitor(struct brw_context *brw, - struct gl_shader_program *shader_prog, - struct gl_program *prog, - struct brw_stage_prog_data *stage_prog_data, - gl_shader_stage stage); + backend_shader(const struct brw_compiler *compiler, + void *log_data, + void *mem_ctx, + struct gl_shader_program *shader_prog, + struct gl_program *prog, + struct brw_stage_prog_data *stage_prog_data, + gl_shader_stage stage); public: - struct brw_context * const brw; - struct gl_context * const ctx; + const struct brw_compiler *compiler; + void *log_data; /* Passed to compiler->*_log functions */ + + const struct brw_device_info * const devinfo; struct brw_shader * const shader; struct gl_shader_program * const shader_prog; struct gl_program * const prog; @@ -185,6 +252,9 @@ public: cfg_t *cfg; gl_shader_stage stage; + bool debug_enabled; + const char *stage_name; + const char *stage_abbrev; brw::simple_allocator alloc; @@ -199,10 +269,12 @@ public: void assign_common_binding_table_offsets(uint32_t next_binding_table_offset); virtual void invalidate_live_intervals() = 0; + + virtual void setup_vector_uniform_values(const gl_constant_value *values, + unsigned n) = 0; }; -uint32_t brw_texture_offset(struct gl_context *ctx, int *offsets, - unsigned num_components); +uint32_t brw_texture_offset(int *offsets, unsigned num_components); #endif /* __cplusplus */ @@ -218,6 +290,9 @@ bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg); extern "C" { #endif +struct brw_compiler * +brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo); + bool brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); @@ -227,6 +302,9 @@ bool brw_gs_precompile(struct gl_context *ctx, bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); +bool brw_cs_precompile(struct gl_context *ctx, + struct gl_shader_program *shader_prog, + struct gl_program *prog); #ifdef __cplusplus }