X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_state_upload.c;h=338f3876b31bdc6c1c77cf7ec9ffc60bee411a71;hb=b2ddb93ff3b8c88682634ccdef247967e31fab84;hp=4c12e68c0e2dc09f2020680e0ee75e6f067602a9;hpb=719f2b1d8570aa58b970bd28941221ee6c34af9b;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 4c12e68c0e2..338f3876b31 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -35,7 +35,6 @@ #include "brw_state.h" #include "intel_batchbuffer.h" #include "intel_buffers.h" -#include "intel_chipset.h" /* This is used to initialize brw->state.atoms[]. We could use this * list directly except for a single atom, brw_constant_buffer, which @@ -61,12 +60,15 @@ static const struct brw_tracked_state *gen4_atoms[] = &brw_curbe_offsets, &brw_recalculate_urb_fence, - &brw_cc_vp, &brw_cc_unit, + &brw_vs_constants, /* Before vs_surfaces and constant_buffer */ + &brw_wm_constants, /* Before wm_surfaces and constant_buffer */ + &brw_vs_surfaces, /* must do before unit */ &brw_wm_constant_surface, /* must do before wm surfaces/bind bo */ &brw_wm_surfaces, /* must do before samplers and unit */ + &brw_wm_binding_table, &brw_wm_samplers, &brw_wm_unit, @@ -106,63 +108,63 @@ const struct brw_tracked_state *gen6_atoms[] = { &brw_check_fallback, -#if 0 &brw_wm_input_sizes, &brw_vs_prog, &brw_gs_prog, - &brw_clip_prog, - &brw_sf_prog, &brw_wm_prog, - /* Once all the programs are done, we know how large urb entry - * sizes need to be and can decide if we need to change the urb - * layout. - */ - &brw_curbe_offsets, - &brw_recalculate_urb_fence, + &gen6_clip_vp, + &gen6_sf_vp, - &brw_cc_vp, - &brw_cc_unit, + /* Command packets: */ + &brw_invarient_state, + + &gen6_viewport_state, /* must do after *_vp stages */ + + &gen6_urb, + &gen6_blend_state, /* must do before cc unit */ + &gen6_color_calc_state, /* must do before cc unit */ + &gen6_depth_stencil_state, /* must do before cc unit */ + &gen6_cc_state_pointers, + + &brw_vs_constants, /* Before vs_surfaces and constant_buffer */ + &brw_wm_constants, /* Before wm_surfaces and constant_buffer */ + &gen6_wm_constants, /* Before wm_surfaces and constant_buffer */ &brw_vs_surfaces, /* must do before unit */ &brw_wm_constant_surface, /* must do before wm surfaces/bind bo */ &brw_wm_surfaces, /* must do before samplers and unit */ + &brw_wm_binding_table, + &brw_wm_samplers, + &gen6_sampler_state, - &brw_wm_unit, - &brw_sf_vp, - &brw_sf_unit, - &brw_vs_unit, /* always required, enabled or not */ - &brw_clip_unit, - &brw_gs_unit, + &gen6_vs_state, + &gen6_gs_state, + &gen6_clip_state, + &gen6_sf_state, + &gen6_wm_state, + + &gen6_scissor_state, + &gen6_scissor_state_pointers, - /* Command packets: - */ - &brw_invarient_state, &brw_state_base_address, - &brw_binding_table_pointers, - &brw_blend_constant_color, -#endif + &gen6_binding_table_pointers, &brw_depthbuffer, -#if 0 &brw_polygon_stipple, &brw_polygon_stipple_offset, &brw_line_stipple, &brw_aa_line_parameters, - &brw_psp_urb_cbs, - &brw_drawing_rect, + &brw_indices, &brw_index_buffer, &brw_vertices, - - &brw_constant_buffer -#endif }; void brw_init_state( struct brw_context *brw ) @@ -213,7 +215,7 @@ brw_clear_validated_bos(struct brw_context *brw) /* Clear the last round of validated bos */ for (i = 0; i < brw->state.validated_bo_count; i++) { - dri_bo_unreference(brw->state.validated_bos[i]); + drm_intel_bo_unreference(brw->state.validated_bos[i]); brw->state.validated_bos[i] = NULL; } brw->state.validated_bo_count = 0; @@ -231,7 +233,6 @@ static struct dirty_bit_map mesa_bits[] = { DEFINE_BIT(_NEW_MODELVIEW), DEFINE_BIT(_NEW_PROJECTION), DEFINE_BIT(_NEW_TEXTURE_MATRIX), - DEFINE_BIT(_NEW_COLOR_MATRIX), DEFINE_BIT(_NEW_ACCUM), DEFINE_BIT(_NEW_COLOR), DEFINE_BIT(_NEW_DEPTH), @@ -271,6 +272,8 @@ static struct dirty_bit_map brw_bits[] = { DEFINE_BIT(BRW_NEW_CONTEXT), DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS), DEFINE_BIT(BRW_NEW_PSP), + DEFINE_BIT(BRW_NEW_WM_SURFACES), + DEFINE_BIT(BRW_NEW_BINDING_TABLE), DEFINE_BIT(BRW_NEW_INDICES), DEFINE_BIT(BRW_NEW_INDEX_BUFFER), DEFINE_BIT(BRW_NEW_VERTICES), @@ -280,6 +283,7 @@ static struct dirty_bit_map brw_bits[] = { }; static struct dirty_bit_map cache_bits[] = { + DEFINE_BIT(CACHE_NEW_BLEND_STATE), DEFINE_BIT(CACHE_NEW_CC_VP), DEFINE_BIT(CACHE_NEW_CC_UNIT), DEFINE_BIT(CACHE_NEW_WM_PROG), @@ -296,8 +300,6 @@ static struct dirty_bit_map cache_bits[] = { DEFINE_BIT(CACHE_NEW_CLIP_VP), DEFINE_BIT(CACHE_NEW_CLIP_UNIT), DEFINE_BIT(CACHE_NEW_CLIP_PROG), - DEFINE_BIT(CACHE_NEW_SURFACE), - DEFINE_BIT(CACHE_NEW_SURF_BIND), {0, 0, 0} }; @@ -335,7 +337,7 @@ brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) */ void brw_validate_state( struct brw_context *brw ) { - GLcontext *ctx = &brw->intel.ctx; + struct gl_context *ctx = &brw->intel.ctx; struct intel_context *intel = &brw->intel; struct brw_state_flags *state = &brw->state.dirty; GLuint i; @@ -349,7 +351,7 @@ void brw_validate_state( struct brw_context *brw ) brw_add_validated_bo(brw, intel->batch->buf); - if (IS_GEN6(intel->intelScreen->deviceID)) { + if (intel->gen >= 6) { atoms = gen6_atoms; num_atoms = ARRAY_SIZE(gen6_atoms); } else { @@ -423,7 +425,7 @@ void brw_upload_state(struct brw_context *brw) const struct brw_tracked_state **atoms; int num_atoms; - if (IS_GEN6(intel->intelScreen->deviceID)) { + if (intel->gen >= 6) { atoms = gen6_atoms; num_atoms = ARRAY_SIZE(gen6_atoms); } else { @@ -433,7 +435,7 @@ void brw_upload_state(struct brw_context *brw) brw_clear_validated_bos(brw); - if (INTEL_DEBUG) { + if (unlikely(INTEL_DEBUG)) { /* Debug version which enforces various sanity checks on the * state flags which are generated and checked to help ensure * state atoms are ordered correctly in the list. @@ -485,7 +487,7 @@ void brw_upload_state(struct brw_context *brw) } } - if (INTEL_DEBUG & DEBUG_STATE) { + if (unlikely(INTEL_DEBUG & DEBUG_STATE)) { brw_update_dirty_count(mesa_bits, state->mesa); brw_update_dirty_count(brw_bits, state->brw); brw_update_dirty_count(cache_bits, state->cache);