X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_tcs.c;h=78ad257e3b987a501df7d3ce8ee64c5eaecf63ab;hb=5edc3381628d1db4468f31b1c66bb518146e35b5;hp=037a2da76818ebf7ce4545d616be8a813d9fe33f;hpb=8498cb4a45e8ed53a2ee2b35d3c2cbb9963e1756;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c index 037a2da7681..78ad257e3b9 100644 --- a/src/mesa/drivers/dri/i965/brw_tcs.c +++ b/src/mesa/drivers/dri/i965/brw_tcs.c @@ -33,10 +33,91 @@ #include "brw_shader.h" #include "brw_state.h" #include "program/prog_parameter.h" +#include "nir_builder.h" + +static nir_shader * +create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler, + const nir_shader_compiler_options *options, + const struct brw_tcs_prog_key *key) +{ + nir_builder b; + nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL, + options); + nir_shader *nir = b.shader; + nir_variable *var; + nir_intrinsic_instr *load; + nir_intrinsic_instr *store; + nir_ssa_def *zero = nir_imm_int(&b, 0); + nir_ssa_def *invoc_id = + nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0); + + nir->info->inputs_read = key->outputs_written & + ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); + nir->info->outputs_written = key->outputs_written; + nir->info->tess.tcs_vertices_out = key->input_vertices; + nir->info->name = ralloc_strdup(nir, "passthrough"); + nir->num_uniforms = 8 * sizeof(uint32_t); + + var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0"); + var->data.location = 0; + var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1"); + var->data.location = 1; + + /* Write the patch URB header. */ + for (int i = 0; i <= 1; i++) { + load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform); + load->num_components = 4; + load->src[0] = nir_src_for_ssa(zero); + nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); + nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t)); + nir_builder_instr_insert(&b, &load->instr); + + store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output); + store->num_components = 4; + store->src[0] = nir_src_for_ssa(&load->dest.ssa); + store->src[1] = nir_src_for_ssa(zero); + nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i); + nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); + nir_builder_instr_insert(&b, &store->instr); + } + + /* Copy inputs to outputs. */ + uint64_t varyings = nir->info->inputs_read; + + while (varyings != 0) { + const int varying = ffsll(varyings) - 1; + + load = nir_intrinsic_instr_create(nir, + nir_intrinsic_load_per_vertex_input); + load->num_components = 4; + load->src[0] = nir_src_for_ssa(invoc_id); + load->src[1] = nir_src_for_ssa(zero); + nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); + nir_intrinsic_set_base(load, varying); + nir_builder_instr_insert(&b, &load->instr); + + store = nir_intrinsic_instr_create(nir, + nir_intrinsic_store_per_vertex_output); + store->num_components = 4; + store->src[0] = nir_src_for_ssa(&load->dest.ssa); + store->src[1] = nir_src_for_ssa(invoc_id); + store->src[2] = nir_src_for_ssa(zero); + nir_intrinsic_set_base(store, varying); + nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW); + nir_builder_instr_insert(&b, &store->instr); + + varyings &= ~BITFIELD64_BIT(varying); + } + + nir_validate_shader(nir); + + nir = brw_preprocess_nir(compiler, nir); + + return nir; +} static void -brw_tcs_debug_recompile(struct brw_context *brw, - struct gl_shader_program *shader_prog, +brw_tcs_debug_recompile(struct brw_context *brw, struct gl_program *prog, const struct brw_tcs_prog_key *key) { struct brw_cache_item *c = NULL; @@ -44,7 +125,7 @@ brw_tcs_debug_recompile(struct brw_context *brw, bool found = false; perf_debug("Recompiling tessellation control shader for program %d\n", - shader_prog->Name); + prog->Id); for (unsigned int i = 0; i < brw->cache.size; i++) { for (c = brw->cache.items[i]; c; c = c->next) { @@ -67,8 +148,14 @@ brw_tcs_debug_recompile(struct brw_context *brw, found |= key_debug(brw, "input vertices", old_key->input_vertices, key->input_vertices); + found |= key_debug(brw, "outputs written", old_key->outputs_written, + key->outputs_written); + found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written, + key->patch_outputs_written); found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode, key->tes_primitive_mode); + found |= key_debug(brw, "quads and equal_spacing workaround", + old_key->quads_workaround, key->quads_workaround); found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex); if (!found) { @@ -77,18 +164,31 @@ brw_tcs_debug_recompile(struct brw_context *brw, } static bool -brw_codegen_tcs_prog(struct brw_context *brw, - struct gl_shader_program *shader_prog, - struct brw_tess_ctrl_program *tcp, - struct brw_tcs_prog_key *key) +brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp, + struct brw_program *tep, struct brw_tcs_prog_key *key) { - const struct brw_compiler *compiler = brw->intelScreen->compiler; + struct gl_context *ctx = &brw->ctx; + const struct brw_compiler *compiler = brw->screen->compiler; + const struct gen_device_info *devinfo = compiler->devinfo; struct brw_stage_state *stage_state = &brw->tcs.base; - nir_shader *nir = tcp->program.Base.nir; + nir_shader *nir; struct brw_tcs_prog_data prog_data; bool start_busy = false; double start_time = 0; + void *mem_ctx = ralloc_context(NULL); + if (tcp) { + nir = tcp->program.nir; + } else { + /* Create a dummy nir_shader. We won't actually use NIR code to + * generate assembly (it's easier to generate assembly directly), + * but the whole compiler assumes one of these exists. + */ + const nir_shader_compiler_options *options = + ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions; + nir = create_passthrough_tcs(mem_ctx, compiler, options, key); + } + memset(&prog_data, 0, sizeof(prog_data)); /* Allocate the references to the uniforms that will end up in the @@ -99,45 +199,70 @@ brw_codegen_tcs_prog(struct brw_context *brw, * padding around uniform values below vec4 size, so the worst case is that * every uniform is a float which gets padded to the size of a vec4. */ - struct gl_shader *tcs = shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]; - int param_count = nir->num_uniforms; - if (!compiler->scalar_stage[MESA_SHADER_TESS_CTRL]) - param_count *= 4; + int param_count = nir->num_uniforms / 4; prog_data.base.base.param = rzalloc_array(NULL, const gl_constant_value *, param_count); prog_data.base.base.pull_param = rzalloc_array(NULL, const gl_constant_value *, param_count); - prog_data.base.base.image_param = - rzalloc_array(NULL, struct brw_image_param, tcs->NumImages); prog_data.base.base.nr_params = param_count; - prog_data.base.base.nr_image_params = tcs->NumImages; - brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program.Base, - &prog_data.base.base, false); - - if (unlikely(INTEL_DEBUG & DEBUG_TCS)) - brw_dump_ir("tessellation control", shader_prog, tcs, NULL); + if (tcp) { + brw_assign_common_binding_table_offsets(devinfo, &tcp->program, + &prog_data.base.base, 0); + + prog_data.base.base.image_param = + rzalloc_array(NULL, struct brw_image_param, + tcp->program.info.num_images); + prog_data.base.base.nr_image_params = tcp->program.info.num_images; + + brw_nir_setup_glsl_uniforms(nir, &tcp->program, &prog_data.base.base, + compiler->scalar_stage[MESA_SHADER_TESS_CTRL]); + } else { + /* Upload the Patch URB Header as the first two uniforms. + * Do the annoying scrambling so the shader doesn't have to. + */ + const float **param = (const float **) prog_data.base.base.param; + static float zero = 0.0f; + for (int i = 0; i < 8; i++) + param[i] = &zero; + + if (key->tes_primitive_mode == GL_QUADS) { + for (int i = 0; i < 4; i++) + param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i]; + + param[3] = &ctx->TessCtrlProgram.patch_default_inner_level[0]; + param[2] = &ctx->TessCtrlProgram.patch_default_inner_level[1]; + } else if (key->tes_primitive_mode == GL_TRIANGLES) { + for (int i = 0; i < 3; i++) + param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i]; + + param[4] = &ctx->TessCtrlProgram.patch_default_inner_level[0]; + } else { + assert(key->tes_primitive_mode == GL_ISOLINES); + param[7] = &ctx->TessCtrlProgram.patch_default_outer_level[1]; + param[6] = &ctx->TessCtrlProgram.patch_default_outer_level[0]; + } + } int st_index = -1; - if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME)) - st_index = brw_get_shader_time_index(brw, shader_prog, NULL, ST_TCS); + if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep)) + st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true); if (unlikely(brw->perf_debug)) { start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo); start_time = get_time(); } - void *mem_ctx = ralloc_context(NULL); unsigned program_size; char *error_str; const unsigned *program = brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index, &program_size, &error_str); if (program == NULL) { - if (shader_prog) { - shader_prog->LinkStatus = false; - ralloc_strcat(&shader_prog->InfoLog, error_str); + if (tep) { + tep->program.sh.data->LinkStatus = false; + ralloc_strcat(&tep->program.sh.data->InfoLog, error_str); } _mesa_problem(NULL, "Failed to compile tessellation control shader: " @@ -148,83 +273,101 @@ brw_codegen_tcs_prog(struct brw_context *brw, } if (unlikely(brw->perf_debug)) { - struct brw_shader *btcs = (struct brw_shader *) tcs; - if (btcs->compiled_once) { - brw_tcs_debug_recompile(brw, shader_prog, key); + if (tcp) { + if (tcp->compiled_once) { + brw_tcs_debug_recompile(brw, &tcp->program, key); + } + tcp->compiled_once = true; } + if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) { perf_debug("TCS compile took %.03f ms and stalled the GPU\n", (get_time() - start_time) * 1000); } - btcs->compiled_once = true; } /* Scratch space is used for register spilling */ - if (prog_data.base.base.total_scratch) { - brw_get_scratch_bo(brw, &stage_state->scratch_bo, - prog_data.base.base.total_scratch * - brw->max_hs_threads); - } + brw_alloc_stage_scratch(brw, stage_state, + prog_data.base.base.total_scratch, + devinfo->max_tcs_threads); brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG, key, sizeof(*key), program, program_size, &prog_data, sizeof(prog_data), - &stage_state->prog_offset, &brw->tcs.prog_data); + &stage_state->prog_offset, &brw->tcs.base.prog_data); ralloc_free(mem_ctx); return true; } +void +brw_tcs_populate_key(struct brw_context *brw, + struct brw_tcs_prog_key *key) +{ + struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; + struct brw_program *tep = (struct brw_program *) brw->tess_eval_program; + struct gl_program *tes_prog = &tep->program; + + uint64_t per_vertex_slots = tes_prog->info.inputs_read; + uint32_t per_patch_slots = tes_prog->info.patch_inputs_read; + + memset(key, 0, sizeof(*key)); + + if (tcp) { + struct gl_program *prog = &tcp->program; + per_vertex_slots |= prog->info.outputs_written; + per_patch_slots |= prog->info.patch_outputs_written; + } + + if (brw->gen < 8 || !tcp) + key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices; + key->outputs_written = per_vertex_slots; + key->patch_outputs_written = per_patch_slots; + + /* We need to specialize our code generation for tessellation levels + * based on the domain the DS is expecting to tessellate. + */ + key->tes_primitive_mode = tep->program.info.tess.primitive_mode; + key->quads_workaround = brw->gen < 9 && + tep->program.info.tess.primitive_mode == GL_QUADS && + tep->program.info.tess.spacing == TESS_SPACING_EQUAL; + + if (tcp) { + key->program_string_id = tcp->id; + + /* _NEW_TEXTURE */ + brw_populate_sampler_prog_key_data(&brw->ctx, &tcp->program, &key->tex); + } +} void brw_upload_tcs_prog(struct brw_context *brw) { - struct gl_context *ctx = &brw->ctx; - struct gl_shader_program **current = ctx->_Shader->CurrentProgram; struct brw_stage_state *stage_state = &brw->tcs.base; struct brw_tcs_prog_key key; - /* BRW_NEW_TESS_CTRL_PROGRAM */ - struct brw_tess_ctrl_program *tcp = - (struct brw_tess_ctrl_program *) brw->tess_ctrl_program; - /* BRW_NEW_TESS_EVAL_PROGRAM */ - struct brw_tess_eval_program *tep = - (struct brw_tess_eval_program *) brw->tess_eval_program; - assert(tcp && tep); + /* BRW_NEW_TESS_PROGRAMS */ + struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; + MAYBE_UNUSED struct brw_program *tep = + (struct brw_program *) brw->tess_eval_program; + assert(tep); if (!brw_state_dirty(brw, _NEW_TEXTURE, BRW_NEW_PATCH_PRIMITIVE | - BRW_NEW_TESS_CTRL_PROGRAM | - BRW_NEW_TESS_EVAL_PROGRAM)) + BRW_NEW_TESS_PROGRAMS)) return; - struct gl_program *prog = &tcp->program.Base; - - memset(&key, 0, sizeof(key)); - - key.program_string_id = tcp->id; - - key.input_vertices = ctx->TessCtrlProgram.patch_vertices; - - /* _NEW_TEXTURE */ - brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count, - &key.tex); - - /* We need to specialize our code generation for tessellation levels - * based on the domain the DS is expecting to tessellate. - */ - key.tes_primitive_mode = tep->program.PrimitiveMode; + brw_tcs_populate_key(brw, &key); if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, &key, sizeof(key), - &stage_state->prog_offset, &brw->tcs.prog_data)) { - bool success = brw_codegen_tcs_prog(brw, current[MESA_SHADER_TESS_CTRL], - tcp, &key); + &stage_state->prog_offset, + &brw->tcs.base.prog_data)) { + bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key); assert(success); (void)success; } - brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base; } @@ -236,11 +379,12 @@ brw_tcs_precompile(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct brw_tcs_prog_key key; uint32_t old_prog_offset = brw->tcs.base.prog_offset; - struct brw_tcs_prog_data *old_prog_data = brw->tcs.prog_data; + struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data; bool success; - struct gl_tess_ctrl_program *tcp = (struct gl_tess_ctrl_program *)prog; - struct brw_tess_ctrl_program *btcp = brw_tess_ctrl_program(tcp); + struct brw_program *btcp = brw_program(prog); + const struct gl_linked_shader *tes = + shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]; memset(&key, 0, sizeof(key)); @@ -248,14 +392,30 @@ brw_tcs_precompile(struct gl_context *ctx, brw_setup_tex_for_precompile(brw, &key.tex, prog); /* Guess that the input and output patches have the same dimensionality. */ - key.input_vertices = shader_prog->TessCtrl.VerticesOut; + if (brw->gen < 8) { + key.input_vertices = shader_prog-> + _LinkedShaders[MESA_SHADER_TESS_CTRL]->info.TessCtrl.VerticesOut; + } + + struct brw_program *btep; + if (tes) { + btep = brw_program(tes->Program); + key.tes_primitive_mode = tes->info.TessEval.PrimitiveMode; + key.quads_workaround = brw->gen < 9 && + tes->info.TessEval.PrimitiveMode == GL_QUADS && + tes->info.TessEval.Spacing == TESS_SPACING_EQUAL; + } else { + btep = NULL; + key.tes_primitive_mode = GL_TRIANGLES; + } - key.tes_primitive_mode = GL_TRIANGLES; + key.outputs_written = prog->nir->info->outputs_written; + key.patch_outputs_written = prog->nir->info->patch_outputs_written; - success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key); + success = brw_codegen_tcs_prog(brw, btcp, btep, &key); brw->tcs.base.prog_offset = old_prog_offset; - brw->tcs.prog_data = old_prog_data; + brw->tcs.base.prog_data = old_prog_data; return success; }