X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_vec4.cpp;h=0fac949521058f71695629608360ee644819fe31;hb=65dd4a255a16a0b5cf843ff1d4657fe346caf116;hp=4210ee00a5481308a6d407c663dd1cc94a2d0305;hpb=2c85132e511bbef9a0965c69848981b1bffb5bad;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 4210ee00a54..0fac9495210 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -22,6 +22,7 @@ */ #include "brw_vec4.h" +#include "brw_fs.h" #include "brw_cfg.h" #include "brw_vs.h" #include "brw_dead_control_flow.h" @@ -112,6 +113,27 @@ src_reg::src_reg(int32_t i) this->fixed_hw_reg.dw1.d = i; } +src_reg::src_reg(uint8_t vf[4]) +{ + init(); + + this->file = IMM; + this->type = BRW_REGISTER_TYPE_VF; + memcpy(&this->fixed_hw_reg.dw1.ud, vf, sizeof(unsigned)); +} + +src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3) +{ + init(); + + this->file = IMM; + this->type = BRW_REGISTER_TYPE_VF; + this->fixed_hw_reg.dw1.ud = (vf0 << 0) | + (vf1 << 8) | + (vf2 << 16) | + (vf3 << 24); +} + src_reg::src_reg(struct brw_reg reg) { init(); @@ -314,6 +336,72 @@ src_reg::equals(const src_reg &r) const sizeof(fixed_hw_reg)) == 0); } +bool +vec4_visitor::opt_vector_float() +{ + bool progress = false; + + int last_reg = -1, last_reg_offset = -1; + enum register_file last_reg_file = BAD_FILE; + + int remaining_channels; + uint8_t imm[4]; + int inst_count; + vec4_instruction *imm_inst[4]; + + foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { + if (last_reg != inst->dst.reg || + last_reg_offset != inst->dst.reg_offset || + last_reg_file != inst->dst.file) { + last_reg = inst->dst.reg; + last_reg_offset = inst->dst.reg_offset; + last_reg_file = inst->dst.file; + remaining_channels = WRITEMASK_XYZW; + + inst_count = 0; + } + + if (inst->opcode != BRW_OPCODE_MOV || + inst->dst.writemask == WRITEMASK_XYZW || + inst->src[0].file != IMM) + continue; + + int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.dw1.f); + if (vf == -1) + continue; + + if ((inst->dst.writemask & WRITEMASK_X) != 0) + imm[0] = vf; + if ((inst->dst.writemask & WRITEMASK_Y) != 0) + imm[1] = vf; + if ((inst->dst.writemask & WRITEMASK_Z) != 0) + imm[2] = vf; + if ((inst->dst.writemask & WRITEMASK_W) != 0) + imm[3] = vf; + + imm_inst[inst_count++] = inst; + + remaining_channels &= ~inst->dst.writemask; + if (remaining_channels == 0) { + vec4_instruction *mov = MOV(inst->dst, imm); + mov->dst.type = BRW_REGISTER_TYPE_F; + mov->dst.writemask = WRITEMASK_XYZW; + inst->insert_after(block, mov); + last_reg = -1; + + for (int i = 0; i < inst_count; i++) { + imm_inst[i]->remove(block); + } + progress = true; + } + } + + if (progress) + invalidate_live_intervals(); + + return progress; +} + /* Replaces unused channels of a swizzle with channels that are used. * * For instance, this pass transforms @@ -332,7 +420,7 @@ vec4_visitor::opt_reduce_swizzle() { bool progress = false; - foreach_in_list_safe(vec4_instruction, inst, &instructions) { + foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { if (inst->dst.file == BAD_FILE || inst->dst.file == HW_REG) continue; @@ -340,6 +428,12 @@ vec4_visitor::opt_reduce_swizzle() /* Determine which channels of the sources are read. */ switch (inst->opcode) { + case VEC4_OPCODE_PACK_BYTES: + swizzle[0] = 0; + swizzle[1] = 1; + swizzle[2] = 2; + swizzle[3] = 3; + break; case BRW_OPCODE_DP4: case BRW_OPCODE_DPH: /* FINISHME: DPH reads only three channels of src0, * but all four of src1. @@ -405,157 +499,6 @@ vec4_visitor::opt_reduce_swizzle() } } - if (progress) - invalidate_live_intervals(false); - - return progress; -} - -static bool -try_eliminate_instruction(vec4_instruction *inst, int new_writemask, - const struct brw_context *brw) -{ - if (inst->has_side_effects()) - return false; - - if (new_writemask == 0) { - /* Don't dead code eliminate instructions that write to the - * accumulator as a side-effect. Instead just set the destination - * to the null register to free it. - */ - if (inst->writes_accumulator || inst->writes_flag()) { - inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type)); - } else { - inst->remove(); - } - - return true; - } else if (inst->dst.writemask != new_writemask) { - switch (inst->opcode) { - case SHADER_OPCODE_TXF_CMS: - case SHADER_OPCODE_GEN4_SCRATCH_READ: - case VS_OPCODE_PULL_CONSTANT_LOAD: - case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7: - break; - default: - /* Do not set a writemask on Gen6 for math instructions, those are - * executed using align1 mode that does not support a destination mask. - */ - if (!(brw->gen == 6 && inst->is_math()) && !inst->is_tex()) { - inst->dst.writemask = new_writemask; - return true; - } - } - } - - return false; -} - -/** - * Must be called after calculate_live_intervals() to remove unused - * writes to registers -- register allocation will fail otherwise - * because something deffed but not used won't be considered to - * interfere with other regs. - */ -bool -vec4_visitor::dead_code_eliminate() -{ - bool progress = false; - int pc = -1; - - calculate_live_intervals(); - - foreach_in_list_safe(vec4_instruction, inst, &instructions) { - pc++; - - bool inst_writes_flag = false; - if (inst->dst.file != GRF) { - if (inst->dst.is_null() && inst->writes_flag()) { - inst_writes_flag = true; - } else { - continue; - } - } - - if (inst->dst.file == GRF) { - int write_mask = inst->dst.writemask; - - for (int c = 0; c < 4; c++) { - if (write_mask & (1 << c)) { - assert(this->virtual_grf_end[inst->dst.reg * 4 + c] >= pc); - if (this->virtual_grf_end[inst->dst.reg * 4 + c] == pc) { - write_mask &= ~(1 << c); - } - } - } - - progress = try_eliminate_instruction(inst, write_mask, brw) || - progress; - } - - if (inst->predicate || inst->prev == NULL) - continue; - - int dead_channels; - if (inst_writes_flag) { -/* Arbitrarily chosen, other than not being an xyzw writemask. */ -#define FLAG_WRITEMASK (1 << 5) - dead_channels = inst->reads_flag() ? 0 : FLAG_WRITEMASK; - } else { - dead_channels = inst->dst.writemask; - - for (int i = 0; i < 3; i++) { - if (inst->src[i].file != GRF || - inst->src[i].reg != inst->dst.reg) - continue; - - for (int j = 0; j < 4; j++) { - int swiz = BRW_GET_SWZ(inst->src[i].swizzle, j); - dead_channels &= ~(1 << swiz); - } - } - } - - for (exec_node *node = inst->prev, *prev = node->prev; - prev != NULL && dead_channels != 0; - node = prev, prev = prev->prev) { - vec4_instruction *scan_inst = (vec4_instruction *)node; - - if (scan_inst->is_control_flow()) - break; - - if (inst_writes_flag) { - if (scan_inst->dst.is_null() && scan_inst->writes_flag()) { - scan_inst->remove(); - progress = true; - continue; - } else if (scan_inst->reads_flag()) { - break; - } - } - - if (inst->dst.file == scan_inst->dst.file && - inst->dst.reg == scan_inst->dst.reg && - inst->dst.reg_offset == scan_inst->dst.reg_offset) { - int new_writemask = scan_inst->dst.writemask & ~dead_channels; - - progress = try_eliminate_instruction(scan_inst, new_writemask, brw) || - progress; - } - - for (int i = 0; i < 3; i++) { - if (scan_inst->src[i].file != inst->dst.file || - scan_inst->src[i].reg != inst->dst.reg) - continue; - - for (int j = 0; j < 4; j++) { - int swiz = BRW_GET_SWZ(scan_inst->src[i].swizzle, j); - dead_channels &= ~(1 << swiz); - } - } - } - } - if (progress) invalidate_live_intervals(); @@ -572,7 +515,7 @@ vec4_visitor::split_uniform_registers() * vector. The goal is to make elimination of unused uniform * components easier later. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -605,7 +548,7 @@ vec4_visitor::pack_uniform_registers() * expect unused vector elements when we've moved array access out * to pull constants, and from some GLSL code generators like wine. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM) continue; @@ -658,7 +601,7 @@ vec4_visitor::pack_uniform_registers() this->uniforms = new_uniform_count; /* Now, update the instructions for our repacked uniforms. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { int src = inst->src[i].reg; @@ -693,8 +636,31 @@ vec4_visitor::opt_algebraic() { bool progress = false; - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { switch (inst->opcode) { + case BRW_OPCODE_MOV: + if (inst->src[0].file != IMM) + break; + + if (inst->saturate) { + if (inst->dst.type != inst->src[0].type) + assert(!"unimplemented: saturate mixed types"); + + if (brw_saturate_immediate(inst->dst.type, + &inst->src[0].fixed_hw_reg)) { + inst->saturate = false; + progress = true; + } + } + break; + + case VEC4_OPCODE_UNPACK_UNIFORM: + if (inst->src[0].file != UNIFORM) { + inst->opcode = BRW_OPCODE_MOV; + progress = true; + } + break; + case BRW_OPCODE_ADD: if (inst->src[1].is_zero()) { inst->opcode = BRW_OPCODE_MOV; @@ -727,6 +693,17 @@ vec4_visitor::opt_algebraic() progress = true; } break; + case SHADER_OPCODE_RCP: { + vec4_instruction *prev = (vec4_instruction *)inst->prev; + if (prev->opcode == SHADER_OPCODE_SQRT) { + if (inst->src[0].equals(src_reg(prev->dst))) { + inst->opcode = SHADER_OPCODE_RSQ; + inst->src[0] = prev->src[0]; + progress = true; + } + } + break; + } default: break; } @@ -801,7 +778,7 @@ vec4_visitor::move_push_constants_to_pull_constants() /* Now actually rewrite usage of the things we've moved to pull * constants. */ - foreach_in_list_safe(vec4_instruction, inst, &instructions) { + foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM || pull_constant_loc[inst->src[i].reg] == -1) @@ -811,7 +788,7 @@ vec4_visitor::move_push_constants_to_pull_constants() dst_reg temp = dst_reg(this, glsl_type::vec4_type); - emit_pull_constant_load(inst, temp, inst->src[i], + emit_pull_constant_load(block, inst, temp, inst->src[i], pull_constant_loc[uniform]); inst->src[i].file = temp.file; @@ -825,6 +802,48 @@ vec4_visitor::move_push_constants_to_pull_constants() pack_uniform_registers(); } +/* Conditions for which we want to avoid setting the dependency control bits */ +bool +vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst) +{ +#define IS_DWORD(reg) \ + (reg.type == BRW_REGISTER_TYPE_UD || \ + reg.type == BRW_REGISTER_TYPE_D) + + /* From the destination hazard section of the spec: + * > Instructions other than send, may use this control as long as operations + * > that have different pipeline latencies are not mixed. + */ + if (brw->gen >= 8) { + if (inst->opcode == BRW_OPCODE_MUL && + IS_DWORD(inst->src[0]) && + IS_DWORD(inst->src[1])) + return true; + } +#undef IS_DWORD + + /* + * mlen: + * In the presence of send messages, totally interrupt dependency + * control. They're long enough that the chance of dependency + * control around them just doesn't matter. + * + * predicate: + * From the Ivy Bridge PRM, volume 4 part 3.7, page 80: + * When a sequence of NoDDChk and NoDDClr are used, the last instruction that + * completes the scoreboard clear must have a non-zero execution mask. This + * means, if any kind of predication can change the execution mask or channel + * enable of the last instruction, the optimization must be avoided. This is + * to avoid instructions being shot down the pipeline when no writes are + * required. + * + * math: + * Dependency control does not work well over math instructions. + * NB: Discovered empirically + */ + return (inst->mlen || inst->predicate || inst->is_math()); +} + /** * Sets the dependency control fields on instructions after register * allocation and before the generator is run. @@ -848,8 +867,6 @@ vec4_visitor::opt_set_dependency_control() vec4_instruction *last_mrf_write[BRW_MAX_GRF]; uint8_t mrf_channels_written[BRW_MAX_GRF]; - calculate_cfg(); - assert(prog_data->total_grf || !"Must be called after register allocation"); @@ -872,28 +889,7 @@ vec4_visitor::opt_set_dependency_control() assert(inst->src[i].file != MRF); } - /* In the presence of send messages, totally interrupt dependency - * control. They're long enough that the chance of dependency - * control around them just doesn't matter. - */ - if (inst->mlen) { - memset(last_grf_write, 0, sizeof(last_grf_write)); - memset(last_mrf_write, 0, sizeof(last_mrf_write)); - continue; - } - - /* It looks like setting dependency control on a predicated - * instruction hangs the GPU. - */ - if (inst->predicate) { - memset(last_grf_write, 0, sizeof(last_grf_write)); - memset(last_mrf_write, 0, sizeof(last_mrf_write)); - continue; - } - - /* Dependency control does not work well over math instructions. - */ - if (inst->is_math()) { + if (is_dep_ctrl_unsafe(inst)) { memset(last_grf_write, 0, sizeof(last_grf_write)); memset(last_mrf_write, 0, sizeof(last_mrf_write)); continue; @@ -972,6 +968,12 @@ vec4_instruction::reswizzle(int dst_writemask, int swizzle) if (src[i].file == BAD_FILE || src[i].file == IMM) continue; + /* Destination write mask doesn't correspond to source swizzle for the + * pack_bytes instruction. + */ + if (opcode == VEC4_OPCODE_PACK_BYTES) + continue; + for (int c = 0; c < 4; c++) { new_swizzle[c] = BRW_GET_SWZ(src[i].swizzle, BRW_GET_SWZ(swizzle, c)); } @@ -1057,10 +1059,11 @@ vec4_visitor::opt_register_coalesce() * everything writing to the temporary to write into the destination * instead. */ - vec4_instruction *scan_inst; - for (scan_inst = (vec4_instruction *)inst->prev; - scan_inst->prev != NULL; - scan_inst = (vec4_instruction *)scan_inst->prev) { + vec4_instruction *_scan_inst = (vec4_instruction *)inst->prev; + foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, + inst, block) { + _scan_inst = scan_inst; + if (scan_inst->dst.file == GRF && scan_inst->dst.reg == inst->src[0].reg && scan_inst->dst.reg_offset == inst->src[0].reg_offset) { @@ -1102,16 +1105,6 @@ vec4_visitor::opt_register_coalesce() break; } - /* We don't handle flow control here. Most computation of values - * that could be coalesced happens just before their use. - */ - if (scan_inst->opcode == BRW_OPCODE_DO || - scan_inst->opcode == BRW_OPCODE_WHILE || - scan_inst->opcode == BRW_OPCODE_ELSE || - scan_inst->opcode == BRW_OPCODE_ENDIF) { - break; - } - /* You can't read from an MRF, so if someone else reads our MRF's * source GRF that we wanted to rewrite, that stops us. If it's a * GRF we're trying to coalesce to, we don't actually handle @@ -1164,7 +1157,7 @@ vec4_visitor::opt_register_coalesce() * computing the value. Now go rewrite the instruction stream * between the two. */ - + vec4_instruction *scan_inst = _scan_inst; while (scan_inst != inst) { if (scan_inst->dst.file == GRF && scan_inst->dst.reg == inst->src[0].reg && @@ -1184,7 +1177,7 @@ vec4_visitor::opt_register_coalesce() } if (progress) - invalidate_live_intervals(false); + invalidate_live_intervals(); return progress; } @@ -1218,7 +1211,7 @@ vec4_visitor::split_virtual_grfs() /* Check that the instructions are compatible with the registers we're trying * to split. */ - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* If there's a SEND message loading from a GRF on gen7+, it needs to be * contiguous. */ @@ -1247,7 +1240,7 @@ vec4_visitor::split_virtual_grfs() this->virtual_grf_sizes[i] = 1; } - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF && split_grf[inst->dst.reg] && inst->dst.reg_offset != 0) { inst->dst.reg = (new_virtual_grf[inst->dst.reg] + @@ -1263,7 +1256,7 @@ vec4_visitor::split_virtual_grfs() } } } - invalidate_live_intervals(false); + invalidate_live_intervals(); } void @@ -1371,6 +1364,13 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) case BRW_REGISTER_TYPE_UD: fprintf(file, "%uU", inst->src[i].fixed_hw_reg.dw1.ud); break; + case BRW_REGISTER_TYPE_VF: + fprintf(file, "[%-gF, %-gF, %-gF, %-gF]", + brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 0) & 0xff), + brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 8) & 0xff), + brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 16) & 0xff), + brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 24) & 0xff)); + break; default: fprintf(file, "???"); break; @@ -1472,7 +1472,7 @@ void vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, bool interleaved) { - foreach_in_list(vec4_instruction, inst, &instructions) { + foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* We have to support ATTR as a destination for GL_FIXED fixup. */ if (inst->dst.file == ATTR) { int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; @@ -1612,6 +1612,12 @@ vec4_vs_visitor::setup_payload(void) this->first_non_payload_grf = reg; } +void +vec4_visitor::assign_binding_table_offsets() +{ + assign_common_binding_table_offsets(0); +} + src_reg vec4_visitor::get_timestamp() { @@ -1620,6 +1626,8 @@ vec4_visitor::get_timestamp() src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TIMESTAMP, 0, + 0, + 0, BRW_REGISTER_TYPE_UD, BRW_VERTICAL_STRIDE_0, BRW_WIDTH_4, @@ -1711,7 +1719,7 @@ vec4_visitor::run() if (INTEL_DEBUG & DEBUG_SHADER_TIME) emit_shader_time_begin(); - assign_common_binding_table_offsets(0); + assign_binding_table_offsets(); emit_prolog(); @@ -1730,6 +1738,8 @@ vec4_visitor::run() emit_thread_end(); + calculate_cfg(); + /* Before any optimization, push array accesses out to scratch * space where we need them to be. This pass may allocate new * virtual GRFs, so we want to do it early. It also makes sure @@ -1754,7 +1764,7 @@ vec4_visitor::run() const char *stage_name = stage == MESA_SHADER_GEOMETRY ? "gs" : "vs"; -#define OPT(pass, args...) do { \ +#define OPT(pass, args...) ({ \ pass_num++; \ bool this_progress = pass(args); \ \ @@ -1767,7 +1777,8 @@ vec4_visitor::run() } \ \ progress = progress || this_progress; \ - } while (false) + this_progress; \ + }) if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER)) { @@ -1780,20 +1791,29 @@ vec4_visitor::run() bool progress; int iteration = 0; + int pass_num = 0; do { progress = false; + pass_num = 0; iteration++; - int pass_num = 0; OPT(opt_reduce_swizzle); OPT(dead_code_eliminate); OPT(dead_control_flow_eliminate, this); OPT(opt_copy_propagation); - OPT(opt_algebraic); OPT(opt_cse); + OPT(opt_algebraic); OPT(opt_register_coalesce); } while (progress); + pass_num = 0; + + if (OPT(opt_vector_float)) { + OPT(opt_cse); + OPT(opt_copy_propagation, false); + OPT(opt_copy_propagation, true); + OPT(dead_code_eliminate); + } if (failed) return false; @@ -1829,8 +1849,6 @@ vec4_visitor::run() */ assert(sanity_param_count == prog->Parameters->NumParameters); - calculate_cfg(); - return !failed; } @@ -1853,6 +1871,7 @@ brw_vs_emit(struct brw_context *brw, { bool start_busy = false; double start_time = 0; + const unsigned *assembly = NULL; if (unlikely(brw->perf_debug)) { start_busy = (brw->batch.last_bo && @@ -1865,25 +1884,56 @@ brw_vs_emit(struct brw_context *brw, shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX]; if (unlikely(INTEL_DEBUG & DEBUG_VS)) - brw_dump_ir(brw, "vertex", prog, &shader->base, &c->vp->program.Base); + brw_dump_ir("vertex", prog, &shader->base, &c->vp->program.Base); + + if (prog && brw->gen >= 8 && brw->scalar_vs) { + fs_visitor v(brw, mem_ctx, &c->key, prog_data, prog, &c->vp->program, 8); + if (!v.run_vs()) { + if (prog) { + prog->LinkStatus = false; + ralloc_strcat(&prog->InfoLog, v.fail_msg); + } - vec4_vs_visitor v(brw, c, prog_data, prog, mem_ctx); - if (!v.run()) { - if (prog) { - prog->LinkStatus = false; - ralloc_strcat(&prog->InfoLog, v.fail_msg); + _mesa_problem(NULL, "Failed to compile vertex shader: %s\n", + v.fail_msg); + + return NULL; } - _mesa_problem(NULL, "Failed to compile vertex shader: %s\n", - v.fail_msg); + fs_generator g(brw, mem_ctx, (void *) &c->key, &prog_data->base.base, + &c->vp->program.Base, v.runtime_check_aads_emit, "VS"); + if (INTEL_DEBUG & DEBUG_VS) { + char *name = ralloc_asprintf(mem_ctx, "%s vertex shader %d", + prog->Label ? prog->Label : "unnamed", + prog->Name); + g.enable_debug(name); + } + g.generate_code(v.cfg, 8); + assembly = g.get_assembly(final_assembly_size); - return NULL; + if (assembly) + prog_data->base.simd8 = true; + c->base.last_scratch = v.last_scratch; } - const unsigned *assembly = NULL; - vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base, - mem_ctx, INTEL_DEBUG & DEBUG_VS); - assembly = g.generate_assembly(v.cfg, final_assembly_size); + if (!assembly) { + vec4_vs_visitor v(brw, c, prog_data, prog, mem_ctx); + if (!v.run()) { + if (prog) { + prog->LinkStatus = false; + ralloc_strcat(&prog->InfoLog, v.fail_msg); + } + + _mesa_problem(NULL, "Failed to compile vertex shader: %s\n", + v.fail_msg); + + return NULL; + } + + vec4_generator g(brw, prog, &c->vp->program.Base, &prog_data->base, + mem_ctx, INTEL_DEBUG & DEBUG_VS, "vertex", "VS"); + assembly = g.generate_assembly(v.cfg, final_assembly_size); + } if (unlikely(brw->perf_debug) && shader) { if (shader->compiled_once) { @@ -1901,16 +1951,17 @@ brw_vs_emit(struct brw_context *brw, void -brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx, - struct brw_vec4_prog_key *key, - GLuint id, struct gl_program *prog) +brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx, + struct brw_vue_prog_key *key, + GLuint id, struct gl_program *prog) { + struct brw_context *brw = brw_context(ctx); key->program_string_id = id; - key->clamp_vertex_color = ctx->API == API_OPENGL_COMPAT; + const bool has_shader_channel_select = brw->is_haswell || brw->gen >= 8; unsigned sampler_count = _mesa_fls(prog->SamplersUsed); for (unsigned i = 0; i < sampler_count; i++) { - if (prog->ShadowSamplers & (1 << i)) { + if (!has_shader_channel_select && (prog->ShadowSamplers & (1 << i))) { /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */ key->tex.swizzles[i] = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_ONE);