X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_vec4.h;h=0dc04eaa252f0ae45148d8a5a7913ef8a76db9b6;hb=63c313de84afa9ee65f5d98e1c843ace3a5c9f21;hp=06a16a49b6f9fac24ff5fd5bab9322553678cb8a;hpb=8b9ecfff360711cffc41a0a062de5ad810f9cf2b;p=mesa.git

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 06a16a49b6f..0dc04eaa252 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -24,41 +24,29 @@
 #ifndef BRW_VEC4_H
 #define BRW_VEC4_H
 
-#include <stdint.h>
 #include "brw_shader.h"
-#include "main/compiler.h"
-#include "program/hash_table.h"
 #include "brw_program.h"
 
 #ifdef __cplusplus
 #include "brw_ir_vec4.h"
-
-extern "C" {
-#endif
-
-#include "brw_context.h"
-#include "brw_eu.h"
-#include "intel_asm_annotation.h"
-
-#ifdef __cplusplus
-}; /* extern "C" */
 #endif
 
 #include "glsl/ir.h"
+#include "glsl/nir/nir.h"
 
 
-struct brw_vec4_compile {
-   GLuint last_scratch; /**< measured in 32-byte (register size) units */
-};
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void
-brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
-                                      struct brw_vue_prog_key *key,
-                                      GLuint id, struct gl_program *prog);
+const unsigned *
+brw_vec4_generate_assembly(const struct brw_compiler *compiler,
+                           void *log_data,
+                           void *mem_ctx,
+                           const nir_shader *nir,
+                           struct brw_vue_prog_data *prog_data,
+                           const struct cfg_t *cfg,
+                           unsigned *out_assembly_size);
 
 #ifdef __cplusplus
 } /* extern "C" */
@@ -73,22 +61,18 @@ class vec4_live_variables;
  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  * fixed-function) into VS IR.
  */
-class vec4_visitor : public backend_shader, public ir_visitor
+class vec4_visitor : public backend_shader
 {
 public:
-   vec4_visitor(struct brw_context *brw,
-                struct brw_vec4_compile *c,
-                struct gl_program *prog,
-                const struct brw_vue_prog_key *key,
+   vec4_visitor(const struct brw_compiler *compiler,
+                void *log_data,
+                const struct brw_sampler_prog_key_data *key,
                 struct brw_vue_prog_data *prog_data,
-		struct gl_shader_program *shader_prog,
-                gl_shader_stage stage,
+                const nir_shader *shader,
 		void *mem_ctx,
                 bool no_spills,
-                shader_time_shader_type st_base,
-                shader_time_shader_type st_written,
-                shader_time_shader_type st_reset);
-   ~vec4_visitor();
+                int shader_time_index);
+   virtual ~vec4_visitor();
 
    dst_reg dst_null_f()
    {
@@ -105,11 +89,8 @@ public:
       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
    }
 
-   struct brw_vec4_compile * const c;
-   const struct brw_vue_prog_key * const key;
+   const struct brw_sampler_prog_key_data * const key_tex;
    struct brw_vue_prog_data * const prog_data;
-   unsigned int sanity_param_count;
-
    char *fail_msg;
    bool failed;
 
@@ -127,64 +108,22 @@ public:
    brw::vec4_live_variables *live_intervals;
    dst_reg userplane[MAX_CLIP_PLANES];
 
-   dst_reg *variable_storage(ir_variable *var);
-
-   void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
-
    bool need_all_constants_in_pull_buffer;
 
-   /**
-    * \name Visit methods
-    *
-    * As typical for the visitor pattern, there must be one \c visit method for
-    * each concrete subclass of \c ir_instruction.  Virtual base classes within
-    * the hierarchy should not have \c visit methods.
-    */
-   /*@{*/
-   virtual void visit(ir_variable *);
-   virtual void visit(ir_loop *);
-   virtual void visit(ir_loop_jump *);
-   virtual void visit(ir_function_signature *);
-   virtual void visit(ir_function *);
-   virtual void visit(ir_expression *);
-   virtual void visit(ir_swizzle *);
-   virtual void visit(ir_dereference_variable  *);
-   virtual void visit(ir_dereference_array *);
-   virtual void visit(ir_dereference_record *);
-   virtual void visit(ir_assignment *);
-   virtual void visit(ir_constant *);
-   virtual void visit(ir_call *);
-   virtual void visit(ir_return *);
-   virtual void visit(ir_discard *);
-   virtual void visit(ir_texture *);
-   virtual void visit(ir_if *);
-   virtual void visit(ir_emit_vertex *);
-   virtual void visit(ir_end_primitive *);
-   /*@}*/
-
-   src_reg result;
-
    /* Regs for vertex results.  Generated at ir_variable visiting time
     * for the ir->location's used.
     */
    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
-   int *uniform_size;
-   int *uniform_vector_size;
-   int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
    int uniforms;
 
    src_reg shader_start_time;
 
-   struct hash_table *variable_ht;
-
-   bool run(void);
+   bool run();
    void fail(const char *msg, ...);
 
-   void setup_uniform_clipplane_values();
-   void setup_uniform_values(ir_variable *ir);
-   void setup_builtin_uniform_values(ir_variable *ir);
    int setup_uniforms(int payload_reg);
+
    bool reg_allocate_trivial();
    bool reg_allocate();
    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
@@ -204,6 +143,7 @@ public:
    int var_range_start(unsigned v, unsigned n) const;
    int var_range_end(unsigned v, unsigned n) const;
    bool virtual_grf_interferes(int a, int b);
+   bool opt_cmod_propagation();
    bool opt_copy_propagation(bool do_constant_prop = true);
    bool opt_cse_local(bblock_t *block);
    bool opt_cse();
@@ -213,6 +153,7 @@ public:
    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
    void opt_set_dependency_control();
    void opt_schedule_instructions();
+   void convert_to_hw_regs();
 
    vec4_instruction *emit(vec4_instruction *inst);
 
@@ -278,51 +219,25 @@ public:
 
    int implied_mrf_writes(vec4_instruction *inst);
 
-   bool try_rewrite_rhs_to_dst(ir_assignment *ir,
-			       dst_reg dst,
-			       src_reg src,
-			       vec4_instruction *pre_rhs_inst,
-			       vec4_instruction *last_rhs_inst);
-
-   /** Walks an exec_list of ir_instruction and sends it through this visitor. */
-   void visit_instructions(const exec_list *list);
+   vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
+                                 src_reg src0, src_reg src1);
 
-   void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
-                    src_reg src0, src_reg src1, src_reg one);
-
-   void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
-   void emit_if_gen6(ir_if *ir);
-
-   void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
-                    src_reg src0, src_reg src1);
-
-   void emit_lrp(const dst_reg &dst,
-                 const src_reg &x, const src_reg &y, const src_reg &a);
-
-   /** Copy any live channel from \p src to the first channel of \p dst. */
-   void emit_uniformize(const dst_reg &dst, const src_reg &src);
-
-   void emit_block_move(dst_reg *dst, src_reg *src,
-                        const struct glsl_type *type, brw_predicate predicate);
-
-   void emit_constant_values(dst_reg *dst, ir_constant *value);
+   vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
+                              const src_reg &y, const src_reg &a);
 
    /**
-    * Emit the correct dot-product instruction for the type of arguments
+    * Copy any live channel from \p src to the first channel of the
+    * result.
     */
-   void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
-
-   void emit_scalar(ir_instruction *ir, enum prog_opcode op,
-		    dst_reg dst, src_reg src0);
+   src_reg emit_uniformize(const src_reg &src);
 
-   void emit_scalar(ir_instruction *ir, enum prog_opcode op,
-		    dst_reg dst, src_reg src0, src_reg src1);
+   src_reg fix_3src_operand(const src_reg &src);
+   src_reg resolve_source_modifiers(const src_reg &src);
 
-   src_reg fix_3src_operand(src_reg src);
+   vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
+                               const src_reg &src1 = src_reg());
 
-   void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
-                  const src_reg &src1 = src_reg());
-   src_reg fix_math_operand(src_reg src);
+   src_reg fix_math_operand(const src_reg &src);
 
    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
@@ -331,21 +246,32 @@ public:
    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 
-   uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
-   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
+   void emit_texture(ir_texture_opcode op,
+                     dst_reg dest,
+                     const glsl_type *dest_type,
+                     src_reg coordinate,
+                     int coord_components,
+                     src_reg shadow_comparitor,
+                     src_reg lod, src_reg lod2,
+                     src_reg sample_index,
+                     uint32_t constant_offset,
+                     src_reg offset_value,
+                     src_reg mcs,
+                     bool is_cube_array,
+                     uint32_t sampler, src_reg sampler_reg);
+
+   src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate,
+                          src_reg sampler);
    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
-   void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 
    void emit_ndc_computation();
    void emit_psiz_and_flags(dst_reg reg);
-   void emit_clip_distances(dst_reg reg, int offset);
    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
-   void emit_urb_slot(dst_reg reg, int varying);
+   virtual void emit_urb_slot(dst_reg reg, int varying);
 
    void emit_shader_time_begin();
    void emit_shader_time_end();
-   void emit_shader_time_write(enum shader_time_shader_type type,
-                               src_reg value);
+   void emit_shader_time_write(int shader_time_subindex, src_reg value);
 
    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
                             dst_reg dst, src_reg offset, src_reg src0,
@@ -356,8 +282,6 @@ public:
 
    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 			      src_reg *reladdr, int reg_offset);
-   src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
-				    src_reg *reladdr, int reg_offset);
    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 			  dst_reg dst,
 			  src_reg orig_src,
@@ -367,7 +291,8 @@ public:
    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 				dst_reg dst,
 				src_reg orig_src,
-				int base_offset);
+				int base_offset,
+                                src_reg indirect);
    void emit_pull_constant_load_reg(dst_reg dst,
                                     src_reg surf_index,
                                     src_reg offset,
@@ -376,19 +301,49 @@ public:
    src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
                                 vec4_instruction *inst, src_reg src);
 
-   bool try_emit_mad(ir_expression *ir);
-   bool try_emit_b2f_of_compare(ir_expression *ir);
    void resolve_ud_negate(src_reg *reg);
-   void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 
    src_reg get_timestamp();
 
-   bool process_move_condition(ir_rvalue *ir);
-
    void dump_instruction(backend_instruction *inst);
    void dump_instruction(backend_instruction *inst, FILE *file);
 
-   void visit_atomic_counter_intrinsic(ir_call *ir);
+   bool is_high_sampler(src_reg sampler);
+
+   virtual void emit_nir_code();
+   virtual void nir_setup_uniforms();
+   virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
+   virtual void nir_setup_system_values();
+   virtual void nir_emit_impl(nir_function_impl *impl);
+   virtual void nir_emit_cf_list(exec_list *list);
+   virtual void nir_emit_if(nir_if *if_stmt);
+   virtual void nir_emit_loop(nir_loop *loop);
+   virtual void nir_emit_block(nir_block *block);
+   virtual void nir_emit_instr(nir_instr *instr);
+   virtual void nir_emit_load_const(nir_load_const_instr *instr);
+   virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr);
+   virtual void nir_emit_alu(nir_alu_instr *instr);
+   virtual void nir_emit_jump(nir_jump_instr *instr);
+   virtual void nir_emit_texture(nir_tex_instr *instr);
+   virtual void nir_emit_undef(nir_ssa_undef_instr *instr);
+   virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr);
+
+   dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type);
+   dst_reg get_nir_dest(nir_dest dest, nir_alu_type type);
+   dst_reg get_nir_dest(nir_dest dest);
+   src_reg get_nir_src(nir_src src, enum brw_reg_type type,
+                       unsigned num_components = 4);
+   src_reg get_nir_src(nir_src src, nir_alu_type type,
+                       unsigned num_components = 4);
+   src_reg get_nir_src(nir_src src,
+                       unsigned num_components = 4);
+
+   virtual dst_reg *make_reg_for_system_value(int location,
+                                              const glsl_type *type) = 0;
+
+   dst_reg *nir_locals;
+   dst_reg *nir_ssa_values;
+   dst_reg *nir_system_values;
 
 protected:
    void emit_vertex();
@@ -396,15 +351,13 @@ protected:
                                     bool interleaved);
    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
                                    int reg_node_count);
-   virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
-   virtual void assign_binding_table_offsets();
    virtual void setup_payload() = 0;
    virtual void emit_prolog() = 0;
-   virtual void emit_program_code() = 0;
    virtual void emit_thread_end() = 0;
    virtual void emit_urb_write_header(int mrf) = 0;
    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
-   virtual int compute_array_stride(ir_dereference_array *ir);
+   virtual void gs_emit_vertex(int stream_id);
+   virtual void gs_end_primitive();
 
 private:
    /**
@@ -412,116 +365,9 @@ private:
     */
    const bool no_spills;
 
-   const shader_time_shader_type st_base;
-   const shader_time_shader_type st_written;
-   const shader_time_shader_type st_reset;
-};
+   int shader_time_index;
 
-
-/**
- * The vertex shader code generator.
- *
- * Translates VS IR to actual i965 assembly code.
- */
-class vec4_generator
-{
-public:
-   vec4_generator(struct brw_context *brw,
-                  struct gl_shader_program *shader_prog,
-                  struct gl_program *prog,
-                  struct brw_vue_prog_data *prog_data,
-                  void *mem_ctx,
-                  bool debug_flag,
-                  const char *stage_name,
-                  const char *stage_abbrev);
-   ~vec4_generator();
-
-   const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
-
-private:
-   void generate_code(const cfg_t *cfg);
-
-   void generate_math1_gen4(vec4_instruction *inst,
-			    struct brw_reg dst,
-			    struct brw_reg src);
-   void generate_math2_gen4(vec4_instruction *inst,
-			    struct brw_reg dst,
-			    struct brw_reg src0,
-			    struct brw_reg src1);
-   void generate_math_gen6(vec4_instruction *inst,
-                           struct brw_reg dst,
-                           struct brw_reg src0,
-                           struct brw_reg src1);
-
-   void generate_tex(vec4_instruction *inst,
-                     struct brw_reg dst,
-                     struct brw_reg src,
-                     struct brw_reg sampler_index);
-
-   void generate_vs_urb_write(vec4_instruction *inst);
-   void generate_gs_urb_write(vec4_instruction *inst);
-   void generate_gs_urb_write_allocate(vec4_instruction *inst);
-   void generate_gs_thread_end(vec4_instruction *inst);
-   void generate_gs_set_write_offset(struct brw_reg dst,
-                                     struct brw_reg src0,
-                                     struct brw_reg src1);
-   void generate_gs_set_vertex_count(struct brw_reg dst,
-                                     struct brw_reg src);
-   void generate_gs_svb_write(vec4_instruction *inst,
-                              struct brw_reg dst,
-                              struct brw_reg src0,
-                              struct brw_reg src1);
-   void generate_gs_svb_set_destination_index(vec4_instruction *inst,
-                                              struct brw_reg dst,
-                                              struct brw_reg src);
-   void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
-   void generate_gs_prepare_channel_masks(struct brw_reg dst);
-   void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
-   void generate_gs_get_instance_id(struct brw_reg dst);
-   void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
-                                           struct brw_reg src0,
-                                           struct brw_reg src1,
-                                           struct brw_reg src2);
-   void generate_gs_ff_sync(vec4_instruction *inst,
-                            struct brw_reg dst,
-                            struct brw_reg src0,
-                            struct brw_reg src1);
-   void generate_gs_set_primitive_id(struct brw_reg dst);
-   void generate_oword_dual_block_offsets(struct brw_reg m1,
-					  struct brw_reg index);
-   void generate_scratch_write(vec4_instruction *inst,
-			       struct brw_reg dst,
-			       struct brw_reg src,
-			       struct brw_reg index);
-   void generate_scratch_read(vec4_instruction *inst,
-			      struct brw_reg dst,
-			      struct brw_reg index);
-   void generate_pull_constant_load(vec4_instruction *inst,
-				    struct brw_reg dst,
-				    struct brw_reg index,
-				    struct brw_reg offset);
-   void generate_pull_constant_load_gen7(vec4_instruction *inst,
-                                         struct brw_reg dst,
-                                         struct brw_reg surf_index,
-                                         struct brw_reg offset);
-   void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
-                                         struct brw_reg dst);
-   void generate_unpack_flags(struct brw_reg dst);
-
-   struct brw_context *brw;
-   const struct brw_device_info *devinfo;
-
-   struct brw_codegen *p;
-
-   struct gl_shader_program *shader_prog;
-   const struct gl_program *prog;
-
-   struct brw_vue_prog_data *prog_data;
-
-   void *mem_ctx;
-   const char *stage_name;
-   const char *stage_abbrev;
-   const bool debug_flag;
+   unsigned last_scratch; /**< measured in 32-byte (register size) units */
 };
 
 } /* namespace brw */