X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_vec4.h;h=150e20a0387dc0287efcdf46021c1eceb341a9cb;hb=179fc4aae8f782453f0488e8dd508f9a01117376;hp=5e5ef036a66ef3b1be90c7c5babd27d0e8aadb4f;hpb=a6367dfc157ecc71a686955323526ac4de3652f6;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 5e5ef036a66..f94f7128a07 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -31,252 +31,42 @@ #include "brw_program.h" #ifdef __cplusplus +#include "brw_ir_vec4.h" + extern "C" { #endif #include "brw_context.h" #include "brw_eu.h" +#include "intel_asm_annotation.h" #ifdef __cplusplus }; /* extern "C" */ -#include "gen8_generator.h" #endif #include "glsl/ir.h" - - -struct brw_vec4_compile { - GLuint last_scratch; /**< measured in 32-byte (register size) units */ -}; - - -struct brw_vec4_prog_key { - GLuint program_string_id; - - /** - * True if at least one clip flag is enabled, regardless of whether the - * shader uses clip planes or gl_ClipDistance. - */ - GLuint userclip_active:1; - - /** - * How many user clipping planes are being uploaded to the vertex shader as - * push constants. - */ - GLuint nr_userclip_plane_consts:4; - - GLuint clamp_vertex_color:1; - - struct brw_sampler_prog_key_data tex; -}; +#include "glsl/nir/nir.h" #ifdef __cplusplus extern "C" { #endif -void -brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx, - struct brw_vec4_prog_key *key, - GLuint id, struct gl_program *prog); +const unsigned * +brw_vec4_generate_assembly(const struct brw_compiler *compiler, + void *log_data, + void *mem_ctx, + const nir_shader *nir, + struct brw_vue_prog_data *prog_data, + const struct cfg_t *cfg, + unsigned *out_assembly_size); #ifdef __cplusplus } /* extern "C" */ namespace brw { -class dst_reg; - -unsigned -swizzle_for_size(int size); - -class reg -{ -public: - /** Register file: GRF, MRF, IMM. */ - enum register_file file; - /** virtual register number. 0 = fixed hw reg */ - int reg; - /** Offset within the virtual register. */ - int reg_offset; - /** Register type. BRW_REGISTER_TYPE_* */ - int type; - struct brw_reg fixed_hw_reg; - - /** Value for file == BRW_IMMMEDIATE_FILE */ - union { - int32_t i; - uint32_t u; - float f; - } imm; -}; - -class src_reg : public reg -{ -public: - DECLARE_RALLOC_CXX_OPERATORS(src_reg) - - void init(); - - src_reg(register_file file, int reg, const glsl_type *type); - src_reg(); - src_reg(float f); - src_reg(uint32_t u); - src_reg(int32_t i); - src_reg(struct brw_reg reg); - - bool equals(src_reg *r); - bool is_zero() const; - bool is_one() const; - - src_reg(class vec4_visitor *v, const struct glsl_type *type); - - explicit src_reg(dst_reg reg); - - GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */ - bool negate; - bool abs; - - src_reg *reladdr; -}; - -static inline src_reg -retype(src_reg reg, unsigned type) -{ - reg.fixed_hw_reg.type = reg.type = type; - return reg; -} - -static inline src_reg -offset(src_reg reg, unsigned delta) -{ - assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM)); - reg.reg_offset += delta; - return reg; -} - -/** - * Reswizzle a given source register. - * \sa brw_swizzle(). - */ -static inline src_reg -swizzle(src_reg reg, unsigned swizzle) -{ - assert(reg.file != HW_REG); - reg.swizzle = BRW_SWIZZLE4( - BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)), - BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)), - BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)), - BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3))); - return reg; -} - -static inline src_reg -negate(src_reg reg) -{ - assert(reg.file != HW_REG && reg.file != IMM); - reg.negate = !reg.negate; - return reg; -} - -class dst_reg : public reg -{ -public: - DECLARE_RALLOC_CXX_OPERATORS(dst_reg) - - void init(); - - dst_reg(); - dst_reg(register_file file, int reg); - dst_reg(register_file file, int reg, const glsl_type *type, int writemask); - dst_reg(struct brw_reg reg); - dst_reg(class vec4_visitor *v, const struct glsl_type *type); - - explicit dst_reg(src_reg reg); - - int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ - - src_reg *reladdr; -}; - -static inline dst_reg -retype(dst_reg reg, unsigned type) -{ - reg.fixed_hw_reg.type = reg.type = type; - return reg; -} - -static inline dst_reg -offset(dst_reg reg, unsigned delta) -{ - assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM)); - reg.reg_offset += delta; - return reg; -} - -static inline dst_reg -writemask(dst_reg reg, unsigned mask) -{ - assert(reg.file != HW_REG && reg.file != IMM); - assert((reg.writemask & mask) != 0); - reg.writemask &= mask; - return reg; -} - -class vec4_instruction : public backend_instruction { -public: - DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction) - - vec4_instruction(vec4_visitor *v, enum opcode opcode, - dst_reg dst = dst_reg(), - src_reg src0 = src_reg(), - src_reg src1 = src_reg(), - src_reg src2 = src_reg()); - - struct brw_reg get_dst(void); - struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i); - - dst_reg dst; - src_reg src[3]; - - bool saturate; - bool force_writemask_all; - bool no_dd_clear, no_dd_check; - - int conditional_mod; /**< BRW_CONDITIONAL_* */ - - int sampler; - uint32_t texture_offset; /**< Texture Offset bitfield */ - int target; /**< MRT target. */ - bool shadow_compare; - - enum brw_urb_write_flags urb_write_flags; - bool header_present; - int mlen; /**< SEND message length */ - int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */ - - uint32_t offset; /* spill/unspill offset */ - /** @{ - * Annotation for the generated IR. One of the two can be set. - */ - const void *ir; - const char *annotation; - /** @} */ - - bool is_send_from_grf(); - bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask); - void reswizzle_dst(int dst_writemask, int swizzle); - - bool reads_flag() - { - return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2; - } - - bool writes_flag() - { - return conditional_mod && opcode != BRW_OPCODE_SEL; - } -}; +class vec4_live_variables; /** * The vertex shader front-end. @@ -284,23 +74,18 @@ public: * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and * fixed-function) into VS IR. */ -class vec4_visitor : public backend_visitor +class vec4_visitor : public backend_shader { public: - vec4_visitor(struct brw_context *brw, - struct brw_vec4_compile *c, - struct gl_program *prog, - const struct brw_vec4_prog_key *key, - struct brw_vec4_prog_data *prog_data, - struct gl_shader_program *shader_prog, - gl_shader_stage stage, + vec4_visitor(const struct brw_compiler *compiler, + void *log_data, + const struct brw_sampler_prog_key_data *key, + struct brw_vue_prog_data *prog_data, + const nir_shader *shader, void *mem_ctx, - bool debug_flag, bool no_spills, - shader_time_shader_type st_base, - shader_time_shader_type st_written, - shader_time_shader_type st_reset); - ~vec4_visitor(); + int shader_time_index); + virtual ~vec4_visitor(); dst_reg dst_null_f() { @@ -317,11 +102,8 @@ public: return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); } - struct brw_vec4_compile * const c; - const struct brw_vec4_prog_key * const key; - struct brw_vec4_prog_data * const prog_data; - unsigned int sanity_param_count; - + const struct brw_sampler_prog_key_data * const key_tex; + struct brw_vue_prog_data * const prog_data; char *fail_msg; bool failed; @@ -332,84 +114,31 @@ public: const void *base_ir; const char *current_annotation; - int *virtual_grf_sizes; - int virtual_grf_count; - int virtual_grf_array_size; int first_non_payload_grf; unsigned int max_grf; int *virtual_grf_start; int *virtual_grf_end; + brw::vec4_live_variables *live_intervals; dst_reg userplane[MAX_CLIP_PLANES]; - /** - * This is the size to be used for an array with an element per - * reg_offset - */ - int virtual_grf_reg_count; - /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */ - int *virtual_grf_reg_map; - - bool live_intervals_valid; - - dst_reg *variable_storage(ir_variable *var); - - void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr); - bool need_all_constants_in_pull_buffer; - /** - * \name Visit methods - * - * As typical for the visitor pattern, there must be one \c visit method for - * each concrete subclass of \c ir_instruction. Virtual base classes within - * the hierarchy should not have \c visit methods. - */ - /*@{*/ - virtual void visit(ir_variable *); - virtual void visit(ir_loop *); - virtual void visit(ir_loop_jump *); - virtual void visit(ir_function_signature *); - virtual void visit(ir_function *); - virtual void visit(ir_expression *); - virtual void visit(ir_swizzle *); - virtual void visit(ir_dereference_variable *); - virtual void visit(ir_dereference_array *); - virtual void visit(ir_dereference_record *); - virtual void visit(ir_assignment *); - virtual void visit(ir_constant *); - virtual void visit(ir_call *); - virtual void visit(ir_return *); - virtual void visit(ir_discard *); - virtual void visit(ir_texture *); - virtual void visit(ir_if *); - virtual void visit(ir_emit_vertex *); - virtual void visit(ir_end_primitive *); - /*@}*/ - - src_reg result; - /* Regs for vertex results. Generated at ir_variable visiting time * for the ir->location's used. */ dst_reg output_reg[BRW_VARYING_SLOT_COUNT]; const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT]; int *uniform_size; - int *uniform_vector_size; - int uniform_array_size; /*< Size of uniform_[vector_]size arrays */ + int uniform_array_size; /*< Size of the uniform_size array */ int uniforms; src_reg shader_start_time; - struct hash_table *variable_ht; - - bool run(void); + bool run(); void fail(const char *msg, ...); - int virtual_grf_alloc(int size); - void setup_uniform_clipplane_values(); - void setup_uniform_values(ir_variable *ir); - void setup_builtin_uniform_values(ir_variable *ir); int setup_uniforms(int payload_reg); + bool reg_allocate_trivial(); bool reg_allocate(); void evaluate_spill_costs(float *spill_costs, bool *no_spill); @@ -423,146 +152,142 @@ public: void calculate_live_intervals(); void invalidate_live_intervals(); void split_virtual_grfs(); + bool opt_vector_float(); + bool opt_reduce_swizzle(); bool dead_code_eliminate(); + int var_range_start(unsigned v, unsigned n) const; + int var_range_end(unsigned v, unsigned n) const; bool virtual_grf_interferes(int a, int b); - bool opt_copy_propagation(); + bool opt_cmod_propagation(); + bool opt_copy_propagation(bool do_constant_prop = true); + bool opt_cse_local(bblock_t *block); + bool opt_cse(); bool opt_algebraic(); bool opt_register_coalesce(); + bool eliminate_find_live_channel(); + bool is_dep_ctrl_unsafe(const vec4_instruction *inst); void opt_set_dependency_control(); void opt_schedule_instructions(); - - bool can_do_source_mods(vec4_instruction *inst); + void convert_to_hw_regs(); vec4_instruction *emit(vec4_instruction *inst); vec4_instruction *emit(enum opcode opcode); - - vec4_instruction *emit(enum opcode opcode, dst_reg dst); - - vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0); - - vec4_instruction *emit(enum opcode opcode, dst_reg dst, - src_reg src0, src_reg src1); - - vec4_instruction *emit(enum opcode opcode, dst_reg dst, - src_reg src0, src_reg src1, src_reg src2); - - vec4_instruction *emit_before(vec4_instruction *inst, + vec4_instruction *emit(enum opcode opcode, const dst_reg &dst); + vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + const src_reg &src0); + vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + const src_reg &src0, const src_reg &src1); + vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, + const src_reg &src0, const src_reg &src1, + const src_reg &src2); + + vec4_instruction *emit_before(bblock_t *block, + vec4_instruction *inst, vec4_instruction *new_inst); - vec4_instruction *MOV(dst_reg dst, src_reg src0); - vec4_instruction *NOT(dst_reg dst, src_reg src0); - vec4_instruction *RNDD(dst_reg dst, src_reg src0); - vec4_instruction *RNDE(dst_reg dst, src_reg src0); - vec4_instruction *RNDZ(dst_reg dst, src_reg src0); - vec4_instruction *FRC(dst_reg dst, src_reg src0); - vec4_instruction *F32TO16(dst_reg dst, src_reg src0); - vec4_instruction *F16TO32(dst_reg dst, src_reg src0); - vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1); +#define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &); +#define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &); +#define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &); + EMIT1(MOV) + EMIT1(NOT) + EMIT1(RNDD) + EMIT1(RNDE) + EMIT1(RNDZ) + EMIT1(FRC) + EMIT1(F32TO16) + EMIT1(F16TO32) + EMIT2(ADD) + EMIT2(MUL) + EMIT2(MACH) + EMIT2(MAC) + EMIT2(AND) + EMIT2(OR) + EMIT2(XOR) + EMIT2(DP3) + EMIT2(DP4) + EMIT2(DPH) + EMIT2(SHL) + EMIT2(SHR) + EMIT2(ASR) vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1, - uint32_t condition); - vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition); - vec4_instruction *IF(uint32_t predicate); - vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index); - vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index); - vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index); - vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x); - vec4_instruction *BFREV(dst_reg dst, src_reg value); - vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value); - vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset); - vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base); - vec4_instruction *FBH(dst_reg dst, src_reg value); - vec4_instruction *FBL(dst_reg dst, src_reg value); - vec4_instruction *CBIT(dst_reg dst, src_reg value); - vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a); - vec4_instruction *ADDC(dst_reg dst, src_reg src0, src_reg src1); - vec4_instruction *SUBB(dst_reg dst, src_reg src0, src_reg src1); + enum brw_conditional_mod condition); + vec4_instruction *IF(src_reg src0, src_reg src1, + enum brw_conditional_mod condition); + vec4_instruction *IF(enum brw_predicate predicate); + EMIT1(SCRATCH_READ) + EMIT2(SCRATCH_WRITE) + EMIT3(LRP) + EMIT1(BFREV) + EMIT3(BFE) + EMIT2(BFI1) + EMIT3(BFI2) + EMIT1(FBH) + EMIT1(FBL) + EMIT1(CBIT) + EMIT3(MAD) + EMIT2(ADDC) + EMIT2(SUBB) +#undef EMIT1 +#undef EMIT2 +#undef EMIT3 int implied_mrf_writes(vec4_instruction *inst); - bool try_rewrite_rhs_to_dst(ir_assignment *ir, - dst_reg dst, - src_reg src, - vec4_instruction *pre_rhs_inst, - vec4_instruction *last_rhs_inst); - - bool try_copy_propagation(vec4_instruction *inst, int arg, - src_reg *values[4]); - - /** Walks an exec_list of ir_instruction and sends it through this visitor. */ - void visit_instructions(const exec_list *list); - - void emit_vp_sop(uint32_t condmod, dst_reg dst, - src_reg src0, src_reg src1, src_reg one); + vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst, + src_reg src0, src_reg src1); - void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate); - void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1); - void emit_if_gen6(ir_if *ir); - - void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1); - - void emit_lrp(const dst_reg &dst, - const src_reg &x, const src_reg &y, const src_reg &a); - - void emit_block_move(dst_reg *dst, src_reg *src, - const struct glsl_type *type, uint32_t predicate); - - void emit_constant_values(dst_reg *dst, ir_constant *value); + vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x, + const src_reg &y, const src_reg &a); /** - * Emit the correct dot-product instruction for the type of arguments + * Copy any live channel from \p src to the first channel of the + * result. */ - void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements); + src_reg emit_uniformize(const src_reg &src); - void emit_scalar(ir_instruction *ir, enum prog_opcode op, - dst_reg dst, src_reg src0); + src_reg fix_3src_operand(const src_reg &src); + src_reg resolve_source_modifiers(const src_reg &src); - void emit_scalar(ir_instruction *ir, enum prog_opcode op, - dst_reg dst, src_reg src0, src_reg src1); + vec4_instruction *emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0, + const src_reg &src1 = src_reg()); - void emit_scs(ir_instruction *ir, enum prog_opcode op, - dst_reg dst, const src_reg &src); - - src_reg fix_3src_operand(src_reg src); - - void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src); - void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src); - void emit_math(enum opcode opcode, dst_reg dst, src_reg src); - void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1); - void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1); - void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1); - src_reg fix_math_operand(src_reg src); + src_reg fix_math_operand(const src_reg &src); void emit_pack_half_2x16(dst_reg dst, src_reg src0); void emit_unpack_half_2x16(dst_reg dst, src_reg src0); - - uint32_t gather_channel(ir_texture *ir, int sampler); - src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler); + void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0); + void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0); + void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0); + void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0); + + void emit_texture(ir_texture_opcode op, + dst_reg dest, + const glsl_type *dest_type, + src_reg coordinate, + int coord_components, + src_reg shadow_comparitor, + src_reg lod, src_reg lod2, + src_reg sample_index, + uint32_t constant_offset, + src_reg offset_value, + src_reg mcs, + bool is_cube_array, + uint32_t surface, src_reg surface_reg, + uint32_t sampler, src_reg sampler_reg); + + src_reg emit_mcs_fetch(const glsl_type *coordinate_type, src_reg coordinate, + src_reg sampler); void emit_gen6_gather_wa(uint8_t wa, dst_reg dst); - void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler); void emit_ndc_computation(); - void emit_psiz_and_flags(struct brw_reg reg); - void emit_clip_distances(dst_reg reg, int offset); - void emit_generic_urb_slot(dst_reg reg, int varying); - void emit_urb_slot(int mrf, int varying); + void emit_psiz_and_flags(dst_reg reg); + vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying); + virtual void emit_urb_slot(dst_reg reg, int varying); void emit_shader_time_begin(); void emit_shader_time_end(); - void emit_shader_time_write(enum shader_time_shader_type type, - src_reg value); + void emit_shader_time_write(int shader_time_subindex, src_reg value); void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, dst_reg dst, src_reg offset, src_reg src0, @@ -571,32 +296,73 @@ public: void emit_untyped_surface_read(unsigned surf_index, dst_reg dst, src_reg offset); - src_reg get_scratch_offset(vec4_instruction *inst, + src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset); - src_reg get_pull_constant_offset(vec4_instruction *inst, + src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst, src_reg *reladdr, int reg_offset); - void emit_scratch_read(vec4_instruction *inst, + void emit_scratch_read(bblock_t *block, vec4_instruction *inst, dst_reg dst, src_reg orig_src, int base_offset); - void emit_scratch_write(vec4_instruction *inst, + void emit_scratch_write(bblock_t *block, vec4_instruction *inst, int base_offset); - void emit_pull_constant_load(vec4_instruction *inst, + void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst, dst_reg dst, src_reg orig_src, int base_offset); + void emit_pull_constant_load_reg(dst_reg dst, + src_reg surf_index, + src_reg offset, + bblock_t *before_block, + vec4_instruction *before_inst); + src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block, + vec4_instruction *inst, src_reg src); - bool try_emit_sat(ir_expression *ir); - bool try_emit_mad(ir_expression *ir, int mul_arg); void resolve_ud_negate(src_reg *reg); src_reg get_timestamp(); - bool process_move_condition(ir_rvalue *ir); - void dump_instruction(backend_instruction *inst); - - void visit_atomic_counter_intrinsic(ir_call *ir); + void dump_instruction(backend_instruction *inst, FILE *file); + + bool is_high_sampler(src_reg sampler); + + virtual void emit_nir_code(); + virtual void nir_setup_inputs(); + virtual void nir_setup_uniforms(); + virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr); + virtual void nir_setup_system_values(); + virtual void nir_emit_impl(nir_function_impl *impl); + virtual void nir_emit_cf_list(exec_list *list); + virtual void nir_emit_if(nir_if *if_stmt); + virtual void nir_emit_loop(nir_loop *loop); + virtual void nir_emit_block(nir_block *block); + virtual void nir_emit_instr(nir_instr *instr); + virtual void nir_emit_load_const(nir_load_const_instr *instr); + virtual void nir_emit_intrinsic(nir_intrinsic_instr *instr); + virtual void nir_emit_alu(nir_alu_instr *instr); + virtual void nir_emit_jump(nir_jump_instr *instr); + virtual void nir_emit_texture(nir_tex_instr *instr); + virtual void nir_emit_undef(nir_ssa_undef_instr *instr); + virtual void nir_emit_ssbo_atomic(int op, nir_intrinsic_instr *instr); + + dst_reg get_nir_dest(nir_dest dest, enum brw_reg_type type); + dst_reg get_nir_dest(nir_dest dest, nir_alu_type type); + dst_reg get_nir_dest(nir_dest dest); + src_reg get_nir_src(nir_src src, enum brw_reg_type type, + unsigned num_components = 4); + src_reg get_nir_src(nir_src src, nir_alu_type type, + unsigned num_components = 4); + src_reg get_nir_src(nir_src src, + unsigned num_components = 4); + + virtual dst_reg *make_reg_for_system_value(int location, + const glsl_type *type) = 0; + + dst_reg *nir_locals; + dst_reg *nir_ssa_values; + src_reg *nir_inputs; + dst_reg *nir_system_values; protected: void emit_vertex(); @@ -604,16 +370,13 @@ protected: bool interleaved); void setup_payload_interference(struct ra_graph *g, int first_payload_node, int reg_node_count); - virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0; virtual void setup_payload() = 0; virtual void emit_prolog() = 0; - virtual void emit_program_code() = 0; virtual void emit_thread_end() = 0; virtual void emit_urb_write_header(int mrf) = 0; virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0; - virtual int compute_array_stride(ir_dereference_array *ir); - - const bool debug_flag; + virtual void gs_emit_vertex(int stream_id); + virtual void gs_end_primitive(); private: /** @@ -621,173 +384,11 @@ private: */ const bool no_spills; - const shader_time_shader_type st_base; - const shader_time_shader_type st_written; - const shader_time_shader_type st_reset; -}; - + int shader_time_index; -/** - * The vertex shader code generator. - * - * Translates VS IR to actual i965 assembly code. - */ -class vec4_generator -{ -public: - vec4_generator(struct brw_context *brw, - struct gl_shader_program *shader_prog, - struct gl_program *prog, - struct brw_vec4_prog_data *prog_data, - void *mem_ctx, - bool debug_flag); - ~vec4_generator(); - - const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size); - -private: - void generate_code(exec_list *instructions); - void generate_vec4_instruction(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg *src); - - void generate_math1_gen4(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src); - void generate_math1_gen6(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src); - void generate_math2_gen4(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_math2_gen6(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_math2_gen7(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - - void generate_tex(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src); - - void generate_vs_urb_write(vec4_instruction *inst); - void generate_gs_urb_write(vec4_instruction *inst); - void generate_gs_thread_end(vec4_instruction *inst); - void generate_gs_set_write_offset(struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_gs_set_vertex_count(struct brw_reg dst, - struct brw_reg src); - void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src); - void generate_gs_prepare_channel_masks(struct brw_reg dst); - void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src); - void generate_gs_get_instance_id(struct brw_reg dst); - void generate_oword_dual_block_offsets(struct brw_reg m1, - struct brw_reg index); - void generate_scratch_write(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg index); - void generate_scratch_read(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index); - void generate_pull_constant_load(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset); - void generate_pull_constant_load_gen7(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg surf_index, - struct brw_reg offset); - void generate_unpack_flags(vec4_instruction *inst, - struct brw_reg dst); - - void generate_untyped_atomic(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg atomic_op, - struct brw_reg surf_index); - - void generate_untyped_surface_read(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg surf_index); - - struct brw_context *brw; - - struct brw_compile *p; - - struct gl_shader_program *shader_prog; - const struct gl_program *prog; - - struct brw_vec4_prog_data *prog_data; - - void *mem_ctx; - const bool debug_flag; + unsigned last_scratch; /**< measured in 32-byte (register size) units */ }; -/** - * The vertex shader code generator. - * - * Translates VS IR to actual i965 assembly code. - */ -class gen8_vec4_generator : public gen8_generator -{ -public: - gen8_vec4_generator(struct brw_context *brw, - struct gl_shader_program *shader_prog, - struct gl_program *prog, - struct brw_vec4_prog_data *prog_data, - void *mem_ctx, - bool debug_flag); - ~gen8_vec4_generator(); - - const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size); - -private: - void generate_code(exec_list *instructions); - void generate_vec4_instruction(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg *src); - - void generate_tex(vec4_instruction *inst, - struct brw_reg dst); - - void generate_urb_write(vec4_instruction *ir, bool copy_g0); - void generate_gs_thread_end(vec4_instruction *ir); - void generate_gs_set_write_offset(struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1); - void generate_gs_set_vertex_count(struct brw_reg dst, - struct brw_reg src); - void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src); - void generate_gs_prepare_channel_masks(struct brw_reg dst); - void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src); - - void generate_oword_dual_block_offsets(struct brw_reg m1, - struct brw_reg index); - void generate_scratch_write(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src, - struct brw_reg index); - void generate_scratch_read(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index); - void generate_pull_constant_load(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg index, - struct brw_reg offset); - - void mark_surface_used(unsigned surf_index); - - struct brw_vec4_prog_data *prog_data; - - const bool debug_flag; -}; - - } /* namespace brw */ #endif /* __cplusplus */