X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_vec4.h;h=4a5b57775c30abea3bb29aaacbf96267b7b49176;hb=a92e5f7cf63d496ad7830b5cea4bbab287c25b8e;hp=91f1b6442ccdebf7f16f939c30df5f8278decd70;hpb=b645913ff6c74228d8c05dd236a545ef2e734071;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 91f1b6442cc..4a5b57775c3 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_vec4.h @@ -39,6 +39,7 @@ extern "C" { #ifdef __cplusplus }; /* extern "C" */ +#include "gen8_generator.h" #endif #include "glsl/ir.h" @@ -64,12 +65,6 @@ struct brw_vec4_prog_key { */ GLuint nr_userclip_plane_consts:4; - /** - * True if the shader uses gl_ClipDistance, regardless of whether any clip - * flags are enabled. - */ - GLuint uses_clip_distance:1; - GLuint clamp_vertex_color:1; struct brw_sampler_prog_key_data tex; @@ -80,6 +75,10 @@ struct brw_vec4_prog_key { extern "C" { #endif +void +brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx, + struct brw_vec4_prog_key *key, + GLuint id, struct gl_program *prog); bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a, const struct brw_vec4_prog_data *b); void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data); @@ -232,7 +231,11 @@ public: struct gl_shader_program *shader_prog, struct brw_shader *shader, void *mem_ctx, - bool debug_flag); + bool debug_flag, + bool no_spills, + shader_time_shader_type st_base, + shader_time_shader_type st_written, + shader_time_shader_type st_reset); ~vec4_visitor(); dst_reg dst_null_f() @@ -250,7 +253,6 @@ public: return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD)); } - struct gl_program *prog; struct brw_vec4_compile *c; const struct brw_vec4_prog_key *key; struct brw_vec4_prog_data *prog_data; @@ -354,6 +356,7 @@ public: void split_uniform_registers(); void pack_uniform_registers(); void calculate_live_intervals(); + void invalidate_live_intervals(); void split_virtual_grfs(); bool dead_code_eliminate(); bool virtual_grf_interferes(int a, int b); @@ -478,6 +481,7 @@ public: void emit_unpack_half_2x16(dst_reg dst, src_reg src0); uint32_t gather_channel(ir_texture *ir, int sampler); + src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler); void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler); void emit_ndc_computation(); @@ -491,6 +495,13 @@ public: void emit_shader_time_write(enum shader_time_shader_type type, src_reg value); + void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index, + dst_reg dst, src_reg offset, src_reg src0, + src_reg src1); + + void emit_untyped_surface_read(unsigned surf_index, dst_reg dst, + src_reg offset); + src_reg get_scratch_offset(vec4_instruction *inst, src_reg *reladdr, int reg_offset); src_reg get_pull_constant_offset(vec4_instruction *inst, @@ -516,9 +527,12 @@ public: void dump_instruction(backend_instruction *inst); + void visit_atomic_counter_intrinsic(ir_call *ir); + protected: void emit_vertex(); - void lower_attributes_to_hw_regs(const int *attribute_map); + void lower_attributes_to_hw_regs(const int *attribute_map, + bool interleaved); void setup_payload_interference(struct ra_graph *g, int first_payload_node, int reg_node_count); virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0; @@ -531,6 +545,16 @@ protected: virtual int compute_array_stride(ir_dereference_array *ir); const bool debug_flag; + +private: + /** + * If true, then register allocation should fail instead of spilling. + */ + const bool no_spills; + + const shader_time_shader_type st_base; + const shader_time_shader_type st_written; + const shader_time_shader_type st_reset; }; @@ -612,6 +636,15 @@ private: void generate_unpack_flags(vec4_instruction *inst, struct brw_reg dst); + void generate_untyped_atomic(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg atomic_op, + struct brw_reg surf_index); + + void generate_untyped_surface_read(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg surf_index); + void mark_surface_used(unsigned surf_index); struct brw_context *brw; @@ -628,6 +661,66 @@ private: const bool debug_flag; }; +/** + * The vertex shader code generator. + * + * Translates VS IR to actual i965 assembly code. + */ +class gen8_vec4_generator : public gen8_generator +{ +public: + gen8_vec4_generator(struct brw_context *brw, + struct gl_shader_program *shader_prog, + struct gl_program *prog, + struct brw_vec4_prog_data *prog_data, + void *mem_ctx, + bool debug_flag); + ~gen8_vec4_generator(); + + const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size); + +private: + void generate_code(exec_list *instructions); + void generate_vec4_instruction(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg *src); + + void generate_tex(vec4_instruction *inst, + struct brw_reg dst); + + void generate_urb_write(vec4_instruction *ir, bool copy_g0); + void generate_gs_thread_end(vec4_instruction *ir); + void generate_gs_set_write_offset(struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1); + void generate_gs_set_vertex_count(struct brw_reg dst, + struct brw_reg src); + void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src); + void generate_gs_prepare_channel_masks(struct brw_reg dst); + void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src); + + void generate_oword_dual_block_offsets(struct brw_reg m1, + struct brw_reg index); + void generate_scratch_write(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src, + struct brw_reg index); + void generate_scratch_read(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg index); + void generate_pull_constant_load(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg index, + struct brw_reg offset); + + void mark_surface_used(unsigned surf_index); + + struct brw_vec4_prog_data *prog_data; + + const bool debug_flag; +}; + + } /* namespace brw */ #endif /* __cplusplus */