X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_vec4_generator.cpp;h=119bcaecf7a32233e518b06e59d36cf46b075f26;hb=f3ddd71f2878e42d2c9e927bd5f695a62b357c58;hp=11f45bd92ca00850ace53cb590332586f726c2f1;hpb=d58e03fe4f04c24c70c76e7ad86fd04b9130a711;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp index 11f45bd92ca..119bcaecf7a 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp @@ -21,6 +21,7 @@ */ #include "brw_vec4.h" +#include "brw_cfg.h" extern "C" { #include "brw_eu.h" @@ -50,6 +51,7 @@ vec4_instruction::get_dst(void) break; case HW_REG: + assert(dst.type == dst.fixed_hw_reg.type); brw_reg = dst.fixed_hw_reg; break; @@ -116,6 +118,7 @@ vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i) break; case HW_REG: + assert(src[i].type == src[i].fixed_hw_reg.type); brw_reg = src[i].fixed_hw_reg; break; @@ -142,8 +145,6 @@ vec4_generator::vec4_generator(struct brw_context *brw, : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data), mem_ctx(mem_ctx), debug_flag(debug_flag) { - shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL; - p = rzalloc(mem_ctx, struct brw_compile); brw_init_compile(brw, p, mem_ctx); } @@ -152,27 +153,18 @@ vec4_generator::~vec4_generator() { } -void -vec4_generator::mark_surface_used(unsigned surf_index) -{ - assert(surf_index < BRW_MAX_SURFACES); - - prog_data->base.binding_table.size_bytes = - MAX2(prog_data->base.binding_table.size_bytes, (surf_index + 1) * 4); -} - void vec4_generator::generate_math1_gen4(vec4_instruction *inst, struct brw_reg dst, struct brw_reg src) { - brw_math(p, - dst, - brw_math_function(inst->opcode), - inst->base_mrf, - src, - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); + gen4_math(p, + dst, + brw_math_function(inst->opcode), + inst->base_mrf, + src, + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); } static void @@ -185,55 +177,21 @@ check_gen6_math_src_arg(struct brw_reg src) } void -vec4_generator::generate_math1_gen6(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src) -{ - /* Can't do writemask because math can't be align16. */ - assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); - check_gen6_math_src_arg(src); - - brw_set_access_mode(p, BRW_ALIGN_1); - brw_math(p, - dst, - brw_math_function(inst->opcode), - inst->base_mrf, - src, - BRW_MATH_DATA_SCALAR, - BRW_MATH_PRECISION_FULL); - brw_set_access_mode(p, BRW_ALIGN_16); -} - -void -vec4_generator::generate_math2_gen7(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) -{ - brw_math2(p, - dst, - brw_math_function(inst->opcode), - src0, src1); -} - -void -vec4_generator::generate_math2_gen6(vec4_instruction *inst, - struct brw_reg dst, - struct brw_reg src0, - struct brw_reg src1) +vec4_generator::generate_math_gen6(vec4_instruction *inst, + struct brw_reg dst, + struct brw_reg src0, + struct brw_reg src1) { /* Can't do writemask because math can't be align16. */ assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); /* Source swizzles are ignored. */ check_gen6_math_src_arg(src0); - check_gen6_math_src_arg(src1); + if (src1.file == BRW_GENERAL_REGISTER_FILE) + check_gen6_math_src_arg(src1); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_math2(p, - dst, - brw_math_function(inst->opcode), - src0, src1); - brw_set_access_mode(p, BRW_ALIGN_16); + brw_set_default_access_mode(p, BRW_ALIGN_1); + gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1); + brw_set_default_access_mode(p, BRW_ALIGN_16); } void @@ -256,18 +214,18 @@ vec4_generator::generate_math2_gen4(vec4_instruction *inst, struct brw_reg &op1 = is_int_div ? src0 : src1; brw_push_insn_state(p); - brw_set_saturate(p, false); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_saturate(p, false); + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1); brw_pop_insn_state(p); - brw_math(p, - dst, - brw_math_function(inst->opcode), - inst->base_mrf, - op0, - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); + gen4_math(p, + dst, + brw_math_function(inst->opcode), + inst->base_mrf, + op0, + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); } void @@ -299,7 +257,7 @@ vec4_generator::generate_tex(vec4_instruction *inst, case SHADER_OPCODE_TXF: msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD; break; - case SHADER_OPCODE_TXF_MS: + case SHADER_OPCODE_TXF_CMS: if (brw->gen >= 7) msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS; else @@ -377,16 +335,33 @@ vec4_generator::generate_tex(vec4_instruction *inst, /* Explicitly set up the message header by copying g0 to the MRF. */ brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); - brw_set_access_mode(p, BRW_ALIGN_1); + brw_set_default_access_mode(p, BRW_ALIGN_1); if (inst->texture_offset) { /* Set the texel offset bits in DWord 2. */ brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(inst->texture_offset)); } + + if (inst->sampler >= 16) { + /* The "Sampler Index" field can only store values between 0 and 15. + * However, we can add an offset to the "Sampler State Pointer" + * field, effectively selecting a different set of 16 samplers. + * + * The "Sampler State Pointer" needs to be aligned to a 32-byte + * offset, and each sampler state is only 16-bytes, so we can't + * exclusively use the offset - we have to use both. + */ + assert(brw->is_haswell); /* field only exists on Haswell */ + brw_ADD(p, + get_element_ud(header, 3), + get_element_ud(brw_vec8_grf(0, 0), 3), + brw_imm_ud(16 * (inst->sampler / 16) * + sizeof(gen7_sampler_state))); + } brw_pop_insn_state(p); } } @@ -415,7 +390,7 @@ vec4_generator::generate_tex(vec4_instruction *inst, inst->base_mrf, src, surface_index, - inst->sampler, + inst->sampler % 16, msg_type, 1, /* response length */ inst->mlen, @@ -423,7 +398,7 @@ vec4_generator::generate_tex(vec4_instruction *inst, BRW_SAMPLER_SIMD_MODE_SIMD4X2, return_format); - mark_surface_used(surface_index); + brw_mark_surface_used(&prog_data->base, surface_index); } void @@ -494,11 +469,11 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst, * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all } */ brw_push_insn_state(p); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4), src1); - brw_set_access_mode(p, BRW_ALIGN_16); + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); } @@ -507,8 +482,8 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst, struct brw_reg src) { brw_push_insn_state(p); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); /* If we think of the src and dst registers as composed of 8 DWORDs each, * we want to pick up the contents of DWORDs 0 and 4 from src, truncate @@ -525,7 +500,7 @@ vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst, */ brw_MOV(p, suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4), stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0)); - brw_set_access_mode(p, BRW_ALIGN_16); + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); } @@ -536,10 +511,10 @@ vec4_generator::generate_gs_set_dword_2_immed(struct brw_reg dst, assert(src.file == BRW_IMMEDIATE_VALUE); brw_push_insn_state(p); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_MOV(p, suboffset(vec1(dst), 2), src); - brw_set_access_mode(p, BRW_ALIGN_16); + brw_set_default_access_mode(p, BRW_ALIGN_16); brw_pop_insn_state(p); } @@ -554,8 +529,8 @@ vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst) */ dst = suboffset(vec1(dst), 4); brw_push_insn_state(p); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_SHL(p, dst, dst, brw_imm_ud(4)); brw_pop_insn_state(p); } @@ -617,12 +592,29 @@ vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst, dst = retype(dst, BRW_REGISTER_TYPE_UB); src = retype(src, BRW_REGISTER_TYPE_UB); brw_push_insn_state(p); - brw_set_access_mode(p, BRW_ALIGN_1); - brw_set_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16)); brw_pop_insn_state(p); } +void +vec4_generator::generate_gs_get_instance_id(struct brw_reg dst) +{ + /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT + * and store into dst.0 & dst.4. So generate the instruction: + * + * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q } + */ + brw_push_insn_state(p); + brw_set_default_access_mode(p, BRW_ALIGN_1); + dst = retype(dst, BRW_REGISTER_TYPE_UD); + struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)); + brw_SHR(p, dst, stride(r0, 1, 4, 0), + brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT)); + brw_pop_insn_state(p); +} + void vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1, struct brw_reg index) @@ -645,8 +637,8 @@ vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1, struct brw_reg index_4 = suboffset(vec1(index), 4); brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); brw_MOV(p, m1_0, index_0); @@ -665,8 +657,8 @@ vec4_generator::generate_unpack_flags(vec4_instruction *inst, struct brw_reg dst) { brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_set_access_mode(p, BRW_ALIGN_1); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_set_default_access_mode(p, BRW_ALIGN_1); struct brw_reg flags = brw_flag_reg(0, 0); struct brw_reg dst_0 = suboffset(vec1(dst), 0); @@ -730,7 +722,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst, /* If the instruction is predicated, we'll predicate the send, not * the header setup. */ - brw_set_predicate_control(p, false); + brw_set_default_predicate_control(p, false); gen6_resolve_implied_move(p, &header, inst->base_mrf); @@ -750,7 +742,7 @@ vec4_generator::generate_scratch_write(vec4_instruction *inst, else msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE; - brw_set_predicate_control(p, inst->predicate); + brw_set_default_predicate_control(p, inst->predicate); /* Pre-gen6, we have to specify write commits to ensure ordering * between reads and writes within a thread. Afterwards, that's @@ -835,7 +827,7 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst, true, /* header_present */ 1 /* rlen */); - mark_surface_used(surf_index); + brw_mark_surface_used(&prog_data->base, surf_index); } void @@ -860,7 +852,7 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst, BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0); - mark_surface_used(surf_index.dw1.ud); + brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); } void @@ -878,7 +870,7 @@ vec4_generator::generate_untyped_atomic(vec4_instruction *inst, atomic_op.dw1.ud, surf_index.dw1.ud, inst->mlen, 1); - mark_surface_used(surf_index.dw1.ud); + brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); } void @@ -893,7 +885,7 @@ vec4_generator::generate_untyped_surface_read(vec4_instruction *inst, surf_index.dw1.ud, inst->mlen, 1); - mark_surface_used(surf_index.dw1.ud); + brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud); } /** @@ -946,9 +938,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, brw_MUL(p, dst, src[0], src[1]); break; case BRW_OPCODE_MACH: - brw_set_acc_write_control(p, 1); brw_MACH(p, dst, src[0], src[1]); - brw_set_acc_write_control(p, 0); break; case BRW_OPCODE_MAD: @@ -1052,15 +1042,14 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, break; case BRW_OPCODE_ADDC: assert(brw->gen >= 7); - brw_set_acc_write_control(p, 1); brw_ADDC(p, dst, src[0], src[1]); - brw_set_acc_write_control(p, 0); break; case BRW_OPCODE_SUBB: assert(brw->gen >= 7); - brw_set_acc_write_control(p, 1); brw_SUBB(p, dst, src[0], src[1]); - brw_set_acc_write_control(p, 0); + break; + case BRW_OPCODE_MAC: + brw_MAC(p, dst, src[0], src[1]); break; case BRW_OPCODE_BFE: @@ -1101,7 +1090,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case BRW_OPCODE_BREAK: brw_BREAK(p); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); break; case BRW_OPCODE_CONTINUE: /* FINISHME: We need to write the loop instruction support still. */ @@ -1109,7 +1098,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, gen6_CONT(p); else brw_CONT(p); - brw_set_predicate_control(p, BRW_PREDICATE_NONE); + brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); break; case BRW_OPCODE_WHILE: @@ -1123,10 +1112,12 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case SHADER_OPCODE_LOG2: case SHADER_OPCODE_SIN: case SHADER_OPCODE_COS: - if (brw->gen == 6) { - generate_math1_gen6(inst, dst, src[0]); + if (brw->gen >= 7) { + gen6_math(p, dst, brw_math_function(inst->opcode), src[0], + brw_null_reg()); + } else if (brw->gen == 6) { + generate_math_gen6(inst, dst, src[0], brw_null_reg()); } else { - /* Also works for Gen7. */ generate_math1_gen4(inst, dst, src[0]); } break; @@ -1135,9 +1126,9 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case SHADER_OPCODE_INT_QUOTIENT: case SHADER_OPCODE_INT_REMAINDER: if (brw->gen >= 7) { - generate_math2_gen7(inst, dst, src[0], src[1]); + gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]); } else if (brw->gen == 6) { - generate_math2_gen6(inst, dst, src[0], src[1]); + generate_math_gen6(inst, dst, src[0], src[1]); } else { generate_math2_gen4(inst, dst, src[0], src[1]); } @@ -1146,7 +1137,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, case SHADER_OPCODE_TEX: case SHADER_OPCODE_TXD: case SHADER_OPCODE_TXF: - case SHADER_OPCODE_TXF_MS: + case SHADER_OPCODE_TXF_CMS: case SHADER_OPCODE_TXF_MCS: case SHADER_OPCODE_TXL: case SHADER_OPCODE_TXS: @@ -1203,10 +1194,15 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, generate_gs_set_channel_masks(dst, src[0]); break; + case GS_OPCODE_GET_INSTANCE_ID: + generate_gs_get_instance_id(dst); + break; + case SHADER_OPCODE_SHADER_TIME_ADD: brw_shader_time_add(p, src[0], prog_data->base.binding_table.shader_time_start); - mark_surface_used(prog_data->base.binding_table.shader_time_start); + brw_mark_surface_used(&prog_data->base, + prog_data->base.binding_table.shader_time_start); break; case SHADER_OPCODE_UNTYPED_ATOMIC: @@ -1235,95 +1231,74 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction, void vec4_generator::generate_code(exec_list *instructions) { - int last_native_insn_offset = 0; - const char *last_annotation_string = NULL; - const void *last_annotation_ir = NULL; + struct annotation_info annotation; + memset(&annotation, 0, sizeof(annotation)); - if (unlikely(debug_flag)) { - if (shader) { - printf("Native code for vertex shader %d:\n", shader_prog->Name); - } else { - printf("Native code for vertex program %d:\n", prog->Id); - } - } + cfg_t *cfg = NULL; + if (unlikely(debug_flag)) + cfg = new(mem_ctx) cfg_t(instructions); foreach_list(node, instructions) { vec4_instruction *inst = (vec4_instruction *)node; struct brw_reg src[3], dst; - if (unlikely(debug_flag)) { - if (last_annotation_ir != inst->ir) { - last_annotation_ir = inst->ir; - if (last_annotation_ir) { - printf(" "); - if (shader) { - ((ir_instruction *) last_annotation_ir)->print(); - } else { - const prog_instruction *vpi; - vpi = (const prog_instruction *) inst->ir; - printf("%d: ", (int)(vpi - prog->Instructions)); - _mesa_fprint_instruction_opt(stdout, vpi, 0, - PROG_PRINT_DEBUG, NULL); - } - printf("\n"); - } - } - if (last_annotation_string != inst->annotation) { - last_annotation_string = inst->annotation; - if (last_annotation_string) - printf(" %s\n", last_annotation_string); - } - } + if (unlikely(debug_flag)) + annotate(brw, &annotation, cfg, inst, p->next_insn_offset); for (unsigned int i = 0; i < 3; i++) { src[i] = inst->get_src(this->prog_data, i); } dst = inst->get_dst(); - brw_set_conditionalmod(p, inst->conditional_mod); - brw_set_predicate_control(p, inst->predicate); - brw_set_predicate_inverse(p, inst->predicate_inverse); - brw_set_saturate(p, inst->saturate); - brw_set_mask_control(p, inst->force_writemask_all); + brw_set_default_predicate_control(p, inst->predicate); + brw_set_default_predicate_inverse(p, inst->predicate_inverse); + brw_set_default_saturate(p, inst->saturate); + brw_set_default_mask_control(p, inst->force_writemask_all); + brw_set_default_acc_write_control(p, inst->writes_accumulator); unsigned pre_emit_nr_insn = p->nr_insn; generate_vec4_instruction(inst, dst, src); - if (inst->no_dd_clear || inst->no_dd_check) { + if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) { assert(p->nr_insn == pre_emit_nr_insn + 1 || - !"no_dd_check or no_dd_clear set for IR emitting more " - "than 1 instruction"); + !"conditional_mod, no_dd_check, or no_dd_clear set for IR " + "emitting more than 1 instruction"); struct brw_instruction *last = &p->store[pre_emit_nr_insn]; + if (inst->conditional_mod) + last->header.destreg__conditionalmod = inst->conditional_mod; if (inst->no_dd_clear) last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; if (inst->no_dd_check) last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; } - - if (unlikely(debug_flag)) { - brw_dump_compile(p, stdout, - last_native_insn_offset, p->next_insn_offset); - } - - last_native_insn_offset = p->next_insn_offset; - } - - if (unlikely(debug_flag)) { - printf("\n"); } brw_set_uip_jip(p); + annotation_finalize(&annotation, p->next_insn_offset); - /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS - * emit issues, it doesn't get the jump distances into the output, - * which is often something we want to debug. So this is here in - * case you're doing that. - */ - if (0 && unlikely(debug_flag)) { - brw_dump_compile(p, stdout, 0, p->next_insn_offset); + int before_size = p->next_insn_offset; + brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann); + int after_size = p->next_insn_offset; + + if (unlikely(debug_flag)) { + if (shader_prog) { + fprintf(stderr, "Native code for %s vertex shader %d:\n", + shader_prog->Label ? shader_prog->Label : "unnamed", + shader_prog->Name); + } else { + fprintf(stderr, "Native code for vertex program %d:\n", prog->Id); + } + fprintf(stderr, "vec4 shader: %d instructions. Compacted %d to %d" + " bytes (%.0f%%)\n", + before_size / 16, before_size, after_size, + 100.0f * (before_size - after_size) / before_size); + + dump_assembly(p->store, annotation.ann_count, annotation.ann, + brw, prog, brw_disassemble); + ralloc_free(annotation.ann); } } @@ -1331,8 +1306,9 @@ const unsigned * vec4_generator::generate_assembly(exec_list *instructions, unsigned *assembly_size) { - brw_set_access_mode(p, BRW_ALIGN_16); + brw_set_default_access_mode(p, BRW_ALIGN_16); generate_code(instructions); + return brw_get_program(p, assembly_size); }