X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_wm_surface_state.c;h=5a3eccfe04288e05410721a9b78504ea6e6e6930;hb=2410deefff2d1551fabfefa4d0ef48e8d9b73bc2;hp=ba98cd42a5e74790c697b9c5dacb504924943f5b;hpb=6d7660cf4b7c0c73b4394f09dd149c6b0386115c;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ba98cd42a5e..5a3eccfe042 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -64,96 +64,114 @@ uint32_t tex_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_WB, [9] = SKL_MOCS_WB, + [10] = CNL_MOCS_WB, }; uint32_t rb_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_PTE, [9] = SKL_MOCS_PTE, + [10] = CNL_MOCS_PTE, }; +static void +get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, + GLenum target, struct isl_view *view, + uint32_t *tile_x, uint32_t *tile_y, + uint32_t *offset, struct isl_surf *surf) +{ + *surf = mt->surf; + + const enum isl_dim_layout dim_layout = + get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target); + + if (surf->dim_layout == dim_layout) + return; + + /* The layout of the specified texture target is not compatible with the + * actual layout of the miptree structure in memory -- You're entering + * dangerous territory, this can only possibly work if you only intended + * to access a single level and slice of the texture, and the hardware + * supports the tile offset feature in order to allow non-tile-aligned + * base offsets, since we'll have to point the hardware to the first + * texel of the level instead of relying on the usual base level/layer + * controls. + */ + assert(brw->has_surface_tile_offset); + assert(view->levels == 1 && view->array_len == 1); + assert(*tile_x == 0 && *tile_y == 0); + + *offset += intel_miptree_get_tile_offsets(mt, view->base_level, + view->base_array_layer, + tile_x, tile_y); + + /* Minify the logical dimensions of the texture. */ + const unsigned l = view->base_level - mt->first_level; + surf->logical_level0_px.width = minify(surf->logical_level0_px.width, l); + surf->logical_level0_px.height = surf->dim <= ISL_SURF_DIM_1D ? 1 : + minify(surf->logical_level0_px.height, l); + surf->logical_level0_px.depth = surf->dim <= ISL_SURF_DIM_2D ? 1 : + minify(surf->logical_level0_px.depth, l); + + /* Only the base level and layer can be addressed with the overridden + * layout. + */ + surf->logical_level0_px.array_len = 1; + surf->levels = 1; + surf->dim_layout = dim_layout; + + /* The requested slice of the texture is now at the base level and + * layer. + */ + view->base_level = 0; + view->base_array_layer = 0; +} + static void brw_emit_surface_state(struct brw_context *brw, - struct intel_mipmap_tree *mt, uint32_t flags, + struct intel_mipmap_tree *mt, GLenum target, struct isl_view view, + enum isl_aux_usage aux_usage, uint32_t mocs, uint32_t *surf_offset, int surf_index, unsigned read_domains, unsigned write_domains) { - uint32_t tile_x = mt->level[0].slice[0].x_offset; - uint32_t tile_y = mt->level[0].slice[0].y_offset; + uint32_t tile_x = mt->level[0].level_x; + uint32_t tile_y = mt->level[0].level_y; uint32_t offset = mt->offset; struct isl_surf surf; - intel_miptree_get_isl_surf(brw, mt, &surf); - - surf.dim = get_isl_surf_dim(target); - - const enum isl_dim_layout dim_layout = - get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target); - - if (surf.dim_layout != dim_layout) { - /* The layout of the specified texture target is not compatible with the - * actual layout of the miptree structure in memory -- You're entering - * dangerous territory, this can only possibly work if you only intended - * to access a single level and slice of the texture, and the hardware - * supports the tile offset feature in order to allow non-tile-aligned - * base offsets, since we'll have to point the hardware to the first - * texel of the level instead of relying on the usual base level/layer - * controls. - */ - assert(brw->has_surface_tile_offset); - assert(view.levels == 1 && view.array_len == 1); - assert(tile_x == 0 && tile_y == 0); - - offset += intel_miptree_get_tile_offsets(mt, view.base_level, - view.base_array_layer, - &tile_x, &tile_y); - - /* Minify the logical dimensions of the texture. */ - const unsigned l = view.base_level - mt->first_level; - surf.logical_level0_px.width = minify(surf.logical_level0_px.width, l); - surf.logical_level0_px.height = surf.dim <= ISL_SURF_DIM_1D ? 1 : - minify(surf.logical_level0_px.height, l); - surf.logical_level0_px.depth = surf.dim <= ISL_SURF_DIM_2D ? 1 : - minify(surf.logical_level0_px.depth, l); - - /* Only the base level and layer can be addressed with the overridden - * layout. - */ - surf.logical_level0_px.array_len = 1; - surf.levels = 1; - surf.dim_layout = dim_layout; - /* The requested slice of the texture is now at the base level and - * layer. - */ - view.base_level = 0; - view.base_array_layer = 0; - } + get_isl_surf(brw, mt, target, &view, &tile_x, &tile_y, &offset, &surf); union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } }; struct brw_bo *aux_bo; - struct isl_surf *aux_surf = NULL, aux_surf_s; + struct isl_surf *aux_surf = NULL; uint64_t aux_offset = 0; - enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE; - if ((mt->mcs_buf || intel_miptree_sample_with_hiz(brw, mt)) && - !(flags & INTEL_AUX_BUFFER_DISABLED)) { - intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage); - aux_surf = &aux_surf_s; - - if (mt->mcs_buf) { - aux_bo = mt->mcs_buf->bo; - aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset; - } else { - aux_bo = mt->hiz_buf->aux_base.bo; - aux_offset = mt->hiz_buf->aux_base.bo->offset64; - } + switch (aux_usage) { + case ISL_AUX_USAGE_MCS: + case ISL_AUX_USAGE_CCS_D: + case ISL_AUX_USAGE_CCS_E: + aux_surf = &mt->mcs_buf->surf; + aux_bo = mt->mcs_buf->bo; + aux_offset = mt->mcs_buf->offset; + break; + + case ISL_AUX_USAGE_HIZ: + aux_surf = &mt->hiz_buf->surf; + aux_bo = mt->hiz_buf->bo; + aux_offset = 0; + break; + + case ISL_AUX_USAGE_NONE: + break; + } + if (aux_usage != ISL_AUX_USAGE_NONE) { /* We only really need a clear color if we also have an auxiliary * surface. Without one, it does nothing. */ - clear_color = intel_miptree_get_isl_clear_color(brw, mt); + clear_color = mt->fast_clear_color; } void *state = brw_state_batch(brw, @@ -161,71 +179,72 @@ brw_emit_surface_state(struct brw_context *brw, brw->isl_dev.ss.align, surf_offset); - isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view, - .address = mt->bo->offset64 + offset, + isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view, + .address = brw_emit_reloc(&brw->batch, + *surf_offset + brw->isl_dev.ss.addr_offset, + mt->bo, offset, read_domains, write_domains), .aux_surf = aux_surf, .aux_usage = aux_usage, .aux_address = aux_offset, .mocs = mocs, .clear_color = clear_color, .x_offset_sa = tile_x, .y_offset_sa = tile_y); - - brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset, - mt->bo, offset, read_domains, write_domains); - if (aux_surf) { /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits * contain other control information. Since buffer addresses are always * on 4k boundaries (and thus have their lower 12 bits zero), we can use * an ordinary reloc to do the necessary address translation. + * + * FIXME: move to the point of assignment. */ assert((aux_offset & 0xfff) == 0); uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset; - brw_emit_reloc(&brw->batch, - *surf_offset + brw->isl_dev.ss.aux_addr_offset, - aux_bo, *aux_addr - aux_bo->offset64, - read_domains, write_domains); + *aux_addr = brw_emit_reloc(&brw->batch, + *surf_offset + + brw->isl_dev.ss.aux_addr_offset, + aux_bo, *aux_addr, + read_domains, write_domains); } } uint32_t brw_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - uint32_t flags, unsigned unit /* unused */, + uint32_t flags, unsigned unit, uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; - if (brw->gen < 9) { - assert(!(flags & INTEL_AUX_BUFFER_DISABLED)); + enum isl_aux_usage aux_usage = + intel_miptree_render_aux_usage(brw, mt, ctx->Color.sRGBEnabled, + ctx->Color.BlendEnabled & (1 << unit)); + + if (flags & INTEL_AUX_BUFFER_DISABLED) { + assert(brw->gen >= 9); + aux_usage = ISL_AUX_USAGE_NONE; } assert(brw_render_target_supported(brw, rb)); mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); - if (unlikely(!brw->format_supported_as_render_target[rb_format])) { + if (unlikely(!brw->mesa_format_supports_render[rb_format])) { _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", __func__, _mesa_get_format_name(rb_format)); } - const unsigned layer_multiplier = - (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || - irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? - MAX2(irb->mt->num_samples, 1) : 1; - struct isl_view view = { - .format = brw->render_target_format[rb_format], + .format = brw->mesa_to_isl_render_format[rb_format], .base_level = irb->mt_level - irb->mt->first_level, .levels = 1, - .base_array_layer = irb->mt_layer / layer_multiplier, + .base_array_layer = irb->mt_layer, .array_len = MAX2(irb->layer_count, 1), .swizzle = ISL_SWIZZLE_IDENTITY, .usage = ISL_SURF_USAGE_RENDER_TARGET_BIT, }; uint32_t offset; - brw_emit_surface_state(brw, mt, flags, mt->target, view, + brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, rb_mocs[brw->gen], &offset, surf_index, I915_GEM_DOMAIN_RENDER, @@ -264,12 +283,12 @@ translate_tex_target(GLenum target) } uint32_t -brw_get_surface_tiling_bits(uint32_t tiling) +brw_get_surface_tiling_bits(enum isl_tiling tiling) { switch (tiling) { - case I915_TILING_X: + case ISL_TILING_X: return BRW_SURFACE_TILED; - case I915_TILING_Y: + case ISL_TILING_Y0: return BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y; default: return 0; @@ -389,7 +408,9 @@ brw_get_texture_swizzle(const struct gl_context *ctx, case GL_RED: case GL_RG: case GL_RGB: - if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0) + if (_mesa_get_format_bits(img->TexFormat, GL_ALPHA_BITS) > 0 || + img->TexFormat == MESA_FORMAT_RGB_DXT1 || + img->TexFormat == MESA_FORMAT_SRGB_DXT1) swizzles[3] = SWIZZLE_ONE; break; } @@ -421,95 +442,21 @@ swizzle_to_scs(GLenum swizzle, bool need_green_to_blue) return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs; } -static unsigned -brw_find_matching_rb(const struct gl_framebuffer *fb, - const struct intel_mipmap_tree *mt) +static bool +brw_aux_surface_disabled(const struct brw_context *brw, + const struct intel_mipmap_tree *mt) { + const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { const struct intel_renderbuffer *irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); if (irb && irb->mt == mt) - return i; + return brw->draw_aux_buffer_disabled[i]; } - return fb->_NumColorDrawBuffers; -} - -static inline bool -brw_texture_view_sane(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - const struct isl_view *view) -{ - /* There are special cases only for lossless compression. */ - if (!intel_miptree_is_lossless_compressed(brw, mt)) - return true; - - if (isl_format_supports_ccs_e(&brw->screen->devinfo, view->format)) - return true; - - /* Logic elsewhere needs to take care to resolve the color buffer prior - * to sampling it as non-compressed. - */ - if (intel_miptree_has_color_unresolved(mt, view->base_level, view->levels, - view->base_array_layer, - view->array_len)) - return false; - - const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; - const unsigned rb_index = brw_find_matching_rb(fb, mt); - - if (rb_index == fb->_NumColorDrawBuffers) - return true; - - /* Underlying surface is compressed but it is sampled using a format that - * the sampling engine doesn't support as compressed. Compression must be - * disabled for both sampling engine and data port in case the same surface - * is used also as render target. - */ - return brw->draw_aux_buffer_disabled[rb_index]; -} - -static bool -brw_disable_aux_surface(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - const struct isl_view *view) -{ - /* Nothing to disable. */ - if (!mt->mcs_buf) - return false; - - const bool is_unresolved = intel_miptree_has_color_unresolved( - mt, view->base_level, view->levels, - view->base_array_layer, view->array_len); - - /* There are special cases only for lossless compression. */ - if (!intel_miptree_is_lossless_compressed(brw, mt)) - return !is_unresolved; - - const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; - const unsigned rb_index = brw_find_matching_rb(fb, mt); - - /* If we are drawing into this with compression enabled, then we must also - * enable compression when texturing from it regardless of - * fast_clear_state. If we don't then, after the first draw call with - * this setup, there will be data in the CCS which won't get picked up by - * subsequent texturing operations as required by ARB_texture_barrier. - * Since we don't want to re-emit the binding table or do a resolve - * operation every draw call, the easiest thing to do is just enable - * compression on the texturing side. This is completely safe to do - * since, if compressed texturing weren't allowed, we would have disabled - * compression of render targets in whatever_that_function_is_called(). - */ - if (rb_index < fb->_NumColorDrawBuffers) { - if (brw->draw_aux_buffer_disabled[rb_index]) { - assert(!is_unresolved); - } - - return brw->draw_aux_buffer_disabled[rb_index]; - } - - return !is_unresolved; + return false; } void @@ -539,9 +486,14 @@ brw_update_texture_surface(struct gl_context *ctx, /* If this is a view with restricted NumLayers, then our effective depth * is not just the miptree depth. */ - const unsigned view_num_layers = - (obj->Immutable && obj->Target != GL_TEXTURE_3D) ? obj->NumLayers : - mt->logical_depth0; + unsigned view_num_layers; + if (obj->Immutable && obj->Target != GL_TEXTURE_3D) { + view_num_layers = obj->NumLayers; + } else { + view_num_layers = mt->surf.dim == ISL_SURF_DIM_3D ? + mt->surf.logical_level0_px.depth : + mt->surf.logical_level0_px.array_len; + } /* Handling GL_ALPHA as a surface format override breaks 1.30+ style * texturing functions that return a float, as our code generation always @@ -555,8 +507,8 @@ brw_update_texture_surface(struct gl_context *ctx, brw_get_texture_swizzle(&brw->ctx, obj)); mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format; - unsigned format = translate_tex_format(brw, mesa_fmt, - sampler->sRGBDecode); + enum isl_format format = translate_tex_format(brw, mesa_fmt, + sampler->sRGBDecode); /* Implement gen6 and gen7 gather work-around */ bool need_green_to_blue = false; @@ -631,11 +583,13 @@ brw_update_texture_surface(struct gl_context *ctx, obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) view.usage |= ISL_SURF_USAGE_CUBE_BIT; - assert(brw_texture_view_sane(brw, mt, &view)); + enum isl_aux_usage aux_usage = + intel_miptree_texture_aux_usage(brw, mt, format); - const int flags = brw_disable_aux_surface(brw, mt, &view) ? - INTEL_AUX_BUFFER_DISABLED : 0; - brw_emit_surface_state(brw, mt, flags, mt->target, view, + if (brw_aux_surface_disabled(brw, mt)) + aux_usage = ISL_AUX_USAGE_NONE; + + brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, tex_mocs[brw->gen], surf_offset, surf_index, I915_GEM_DOMAIN_SAMPLER, 0); @@ -658,18 +612,16 @@ brw_emit_buffer_surface_state(struct brw_context *brw, out_offset); isl_buffer_fill_state(&brw->isl_dev, dw, - .address = (bo ? bo->offset64 : 0) + buffer_offset, + .address = !bo ? buffer_offset : + brw_emit_reloc(&brw->batch, + *out_offset + brw->isl_dev.ss.addr_offset, + bo, buffer_offset, + I915_GEM_DOMAIN_SAMPLER, + (rw ? I915_GEM_DOMAIN_SAMPLER : 0)), .size = buffer_size, .format = surface_format, .stride = pitch, .mocs = tex_mocs[brw->gen]); - - if (bo) { - brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset, - bo, buffer_offset, - I915_GEM_DOMAIN_SAMPLER, - (rw ? I915_GEM_DOMAIN_SAMPLER : 0)); - } } void @@ -684,12 +636,13 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, uint32_t size = tObj->BufferSize; struct brw_bo *bo = NULL; mesa_format format = tObj->_BufferObjectFormat; - uint32_t brw_format = brw_isl_format_for_mesa_format(format); + const enum isl_format isl_format = brw_isl_format_for_mesa_format(format); int texel_size = _mesa_get_format_bytes(format); if (intel_obj) { size = MIN2(size, intel_obj->Base.Size); - bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size); + bo = intel_bufferobj_buffer(brw, intel_obj, tObj->BufferOffset, size, + false); } /* The ARB_texture_buffer_specification says: @@ -710,14 +663,14 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, */ size = MIN2(size, ctx->Const.MaxTextureBufferSize * (unsigned) texel_size); - if (brw_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { + if (isl_format == ISL_FORMAT_UNSUPPORTED) { _mesa_problem(NULL, "bad format %s for texture buffer\n", _mesa_get_format_name(format)); } brw_emit_buffer_surface_state(brw, surf_offset, bo, tObj->BufferOffset, - brw_format, + isl_format, size, texel_size, false /* rw */); @@ -777,7 +730,8 @@ brw_update_sol_surface(struct brw_context *brw, uint32_t offset_bytes = 4 * offset_dwords; struct brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo, offset_bytes, - buffer_obj->Size - offset_bytes); + buffer_obj->Size - offset_bytes, + true); uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset); uint32_t pitch_minus_1 = 4*stride_dwords - 1; size_t size_dwords = buffer_obj->Size / 4; @@ -830,17 +784,15 @@ brw_update_sol_surface(struct brw_context *brw, BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | surface_format << BRW_SURFACE_FORMAT_SHIFT | BRW_SURFACE_RC_READ_WRITE; - surf[1] = bo->offset64 + offset_bytes; /* reloc */ + surf[1] = brw_emit_reloc(&brw->batch, + *out_offset + 4, bo, offset_bytes, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT | height << BRW_SURFACE_HEIGHT_SHIFT); surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT | pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); surf[4] = 0; surf[5] = 0; - - /* Emit relocation to surface contents. */ - brw_emit_reloc(&brw->batch, *out_offset + 4, bo, offset_bytes, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } /* Creates a new WM constant buffer reflecting the current fragment program's @@ -948,7 +900,9 @@ brw_emit_null_surface_state(struct brw_context *brw, 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT | 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT); } - surf[1] = bo ? bo->offset64 : 0; + surf[1] = !bo ? 0 : + brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT | (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); @@ -961,11 +915,6 @@ brw_emit_null_surface_state(struct brw_context *brw, pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); surf[4] = multisampling_state; surf[5] = 0; - - if (bo) { - brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - } } /** @@ -984,7 +933,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, struct intel_mipmap_tree *mt = irb->mt; uint32_t *surf; uint32_t tile_x, tile_y; - uint32_t format = 0; + enum isl_format format; uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); @@ -1004,14 +953,15 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, * miptree and render into that. */ intel_renderbuffer_move_to_temp(brw, irb, false); - mt = irb->mt; + assert(irb->align_wa_mt); + mt = irb->align_wa_mt; } } surf = brw_state_batch(brw, 6 * 4, 32, &offset); - format = brw->render_target_format[rb_format]; - if (unlikely(!brw->format_supported_as_render_target[rb_format])) { + format = brw->mesa_to_isl_render_format[rb_format]; + if (unlikely(!brw->mesa_format_supports_render[rb_format])) { _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", __func__, _mesa_get_format_name(rb_format)); } @@ -1021,16 +971,20 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, /* reloc */ assert(mt->offset % mt->cpp == 0); - surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + - mt->bo->offset64 + mt->offset); + surf[1] = brw_emit_reloc(&brw->batch, offset + 4, mt->bo, + mt->offset + + intel_renderbuffer_get_tile_offsets(irb, + &tile_x, + &tile_y), + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); - surf[3] = (brw_get_surface_tiling_bits(mt->tiling) | - (mt->pitch - 1) << BRW_SURFACE_PITCH_SHIFT); + surf[3] = (brw_get_surface_tiling_bits(mt->surf.tiling) | + (mt->surf.row_pitch - 1) << BRW_SURFACE_PITCH_SHIFT); - surf[4] = brw_get_surface_num_multisamples(mt->num_samples); + surf[4] = brw_get_surface_num_multisamples(mt->surf.samples); assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); /* Note that the low bits of these fields are missing, so @@ -1040,7 +994,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, assert(tile_y % 2 == 0); surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - (mt->valign == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); + (mt->surf.image_alignment_el.height == 4 ? + BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); if (brw->gen < 6) { /* _NEW_COLOR */ @@ -1064,9 +1019,6 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, } } - brw_emit_reloc(&brw->batch, offset + 4, mt->bo, surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - return offset; } @@ -1170,7 +1122,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) uint32_t *surf_offset = &brw->wm.base.surf_offset[surf_index]; if (irb) { - const unsigned format = brw->render_target_format[ + const enum isl_format format = brw->mesa_to_isl_render_format[ _mesa_get_render_format(ctx, intel_rb_format(irb))]; assert(isl_format_supports_sampling(&brw->screen->devinfo, format)); @@ -1190,29 +1142,22 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) irb->mt->target == GL_TEXTURE_1D_ARRAY ? GL_TEXTURE_2D_ARRAY : irb->mt->target; - /* intel_renderbuffer::mt_layer is expressed in sample units for - * the UMS and CMS multisample layouts, but - * intel_renderbuffer::layer_count is expressed in units of whole - * logical layers regardless of the multisample layout. - */ - const unsigned mt_layer_unit = - (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS || - irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? - MAX2(irb->mt->num_samples, 1) : 1; - const struct isl_view view = { .format = format, .base_level = irb->mt_level - irb->mt->first_level, .levels = 1, - .base_array_layer = irb->mt_layer / mt_layer_unit, + .base_array_layer = irb->mt_layer, .array_len = irb->layer_count, .swizzle = ISL_SWIZZLE_IDENTITY, .usage = ISL_SURF_USAGE_TEXTURE_BIT, }; - const int flags = brw->draw_aux_buffer_disabled[i] ? - INTEL_AUX_BUFFER_DISABLED : 0; - brw_emit_surface_state(brw, irb->mt, flags, target, view, + enum isl_aux_usage aux_usage = + intel_miptree_texture_aux_usage(brw, irb->mt, format); + if (brw->draw_aux_buffer_disabled[i]) + aux_usage = ISL_AUX_USAGE_NONE; + + brw_emit_surface_state(brw, irb->mt, target, view, aux_usage, tex_mocs[brw->gen], surf_offset, surf_index, I915_GEM_DOMAIN_SAMPLER, 0); @@ -1402,7 +1347,7 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, struct brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo, binding->Offset, - size); + size, false); brw_create_constant_surface(brw, bo, binding->Offset, size, &ubo_surf_offsets[i]); @@ -1427,13 +1372,15 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, struct brw_bo *bo = intel_bufferobj_buffer(brw, intel_bo, binding->Offset, - size); + size, true); brw_create_buffer_surface(brw, bo, binding->Offset, size, &ssbo_surf_offsets[i]); } } + stage_state->push_constants_dirty = true; + if (prog->info.num_ubos || prog->info.num_ssbos) brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } @@ -1499,8 +1446,10 @@ brw_upload_abo_surfaces(struct brw_context *brw, &ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding]; struct intel_buffer_object *intel_bo = intel_buffer_object(binding->BufferObject); - struct brw_bo *bo = intel_bufferobj_buffer( - brw, intel_bo, binding->Offset, intel_bo->Base.Size - binding->Offset); + struct brw_bo *bo = + intel_bufferobj_buffer(brw, intel_bo, binding->Offset, + intel_bo->Base.Size - binding->Offset, + true); brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo, binding->Offset, ISL_FORMAT_RAW, @@ -1585,7 +1534,7 @@ static uint32_t get_image_format(struct brw_context *brw, mesa_format format, GLenum access) { const struct gen_device_info *devinfo = &brw->screen->devinfo; - uint32_t hw_format = brw_isl_format_for_mesa_format(format); + enum isl_format hw_format = brw_isl_format_for_mesa_format(format); if (access == GL_WRITE_ONLY) { return hw_format; } else if (isl_has_matching_typed_storage_image_format(devinfo, hw_format)) { @@ -1632,71 +1581,16 @@ update_buffer_image_param(struct brw_context *brw, param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat); } -static void -update_texture_image_param(struct brw_context *brw, - struct gl_image_unit *u, - unsigned surface_idx, - struct brw_image_param *param) +static unsigned +get_image_num_layers(const struct intel_mipmap_tree *mt, GLenum target, + unsigned level) { - struct intel_mipmap_tree *mt = intel_texture_object(u->TexObj)->mt; - - update_default_image_param(brw, u, surface_idx, param); + if (target == GL_TEXTURE_CUBE_MAP) + return 6; - param->size[0] = minify(mt->logical_width0, u->Level); - param->size[1] = minify(mt->logical_height0, u->Level); - param->size[2] = (!u->Layered ? 1 : - u->TexObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : - u->TexObj->Target == GL_TEXTURE_3D ? - minify(mt->logical_depth0, u->Level) : - mt->logical_depth0); - - intel_miptree_get_image_offset(mt, u->Level, u->_Layer, - ¶m->offset[0], - ¶m->offset[1]); - - param->stride[0] = mt->cpp; - param->stride[1] = mt->pitch / mt->cpp; - param->stride[2] = - brw_miptree_get_horizontal_slice_pitch(brw, mt, u->Level); - param->stride[3] = - brw_miptree_get_vertical_slice_pitch(brw, mt, u->Level); - - if (mt->tiling == I915_TILING_X) { - /* An X tile is a rectangular block of 512x8 bytes. */ - param->tiling[0] = _mesa_logbase2(512 / mt->cpp); - param->tiling[1] = _mesa_logbase2(8); - - if (brw->has_swizzling) { - /* Right shifts required to swizzle bits 9 and 10 of the memory - * address with bit 6. - */ - param->swizzling[0] = 3; - param->swizzling[1] = 4; - } - } else if (mt->tiling == I915_TILING_Y) { - /* The layout of a Y-tiled surface in memory isn't really fundamentally - * different to the layout of an X-tiled surface, we simply pretend that - * the surface is broken up in a number of smaller 16Bx32 tiles, each - * one arranged in X-major order just like is the case for X-tiling. - */ - param->tiling[0] = _mesa_logbase2(16 / mt->cpp); - param->tiling[1] = _mesa_logbase2(32); - - if (brw->has_swizzling) { - /* Right shift required to swizzle bit 9 of the memory address with - * bit 6. - */ - param->swizzling[0] = 3; - } - } - - /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The - * address calculation algorithm (emit_address_calculation() in - * brw_fs_surface_builder.cpp) handles this as a sort of tiling with - * modulus equal to the LOD. - */ - param->tiling[2] = (u->TexObj->Target == GL_TEXTURE_3D ? u->Level : - 0); + return target == GL_TEXTURE_3D ? + minify(mt->surf.logical_level0_px.depth, level) : + mt->surf.logical_level0_px.array_len; } static void @@ -1727,6 +1621,18 @@ update_image_surface(struct brw_context *brw, } else { struct intel_texture_object *intel_obj = intel_texture_object(obj); struct intel_mipmap_tree *mt = intel_obj->mt; + const unsigned num_layers = u->Layered ? + get_image_num_layers(mt, obj->Target, u->Level) : 1; + + struct isl_view view = { + .format = format, + .base_level = obj->MinLevel + u->Level, + .levels = 1, + .base_array_layer = obj->MinLayer + u->_Layer, + .array_len = num_layers, + .swizzle = ISL_SWIZZLE_IDENTITY, + .usage = ISL_SURF_USAGE_STORAGE_BIT, + }; if (format == ISL_FORMAT_RAW) { brw_emit_buffer_surface_state( @@ -1735,34 +1641,21 @@ update_image_surface(struct brw_context *brw, access != GL_READ_ONLY); } else { - const unsigned num_layers = (!u->Layered ? 1 : - obj->Target == GL_TEXTURE_CUBE_MAP ? 6 : - mt->logical_depth0); - - struct isl_view view = { - .format = format, - .base_level = obj->MinLevel + u->Level, - .levels = 1, - .base_array_layer = obj->MinLayer + u->_Layer, - .array_len = num_layers, - .swizzle = ISL_SWIZZLE_IDENTITY, - .usage = ISL_SURF_USAGE_STORAGE_BIT, - }; - const int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; - const bool unresolved = intel_miptree_has_color_unresolved( - mt, view.base_level, view.levels, - view.base_array_layer, view.array_len); - const int flags = unresolved ? 0 : INTEL_AUX_BUFFER_DISABLED; - brw_emit_surface_state(brw, mt, flags, mt->target, view, - tex_mocs[brw->gen], + assert(!intel_miptree_has_color_unresolved(mt, + view.base_level, 1, + view.base_array_layer, + view.array_len)); + brw_emit_surface_state(brw, mt, mt->target, view, + ISL_AUX_USAGE_NONE, tex_mocs[brw->gen], surf_offset, surf_index, I915_GEM_DOMAIN_SAMPLER, access == GL_READ_ONLY ? 0 : I915_GEM_DOMAIN_SAMPLER); } - update_texture_image_param(brw, u, surface_idx, param); + isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view); + param->surface_idx = surface_idx; } } else {