X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen6_blorp.cpp;h=4222fa87d08edf25f86077426ed1a9b73fd8774e;hb=7a7b8a02bed5a113fd0f8e45acc0eafdd7227b55;hp=d5d65c635f2d78fe987880ae255606dd0541e4fc;hpb=c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index d5d65c635f2..4222fa87d08 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -45,63 +45,6 @@ * sizeof(float)) /** \} */ - -/** - * Compute masks to determine how much of draw_x and draw_y should be - * performed using the fine adjustment of "depth coordinate offset X/Y" - * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for - * details. - */ -void -gen6_blorp_compute_tile_masks(const brw_blorp_params *params, - uint32_t *tile_mask_x, uint32_t *tile_mask_y) -{ - uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y; - intel_region_get_tile_masks(params->depth.mt->region, - &depth_mask_x, &depth_mask_y); - intel_region_get_tile_masks(params->depth.mt->hiz_mt->region, - &hiz_mask_x, &hiz_mask_y); - - /* Each HiZ row represents 2 rows of pixels */ - hiz_mask_y = hiz_mask_y << 1 | 1; - - *tile_mask_x = depth_mask_x | hiz_mask_x; - *tile_mask_y = depth_mask_y | hiz_mask_y; -} - - -void -gen6_blorp_emit_batch_head(struct brw_context *brw, - const brw_blorp_params *params) -{ - struct gl_context *ctx = &brw->intel.ctx; - struct intel_context *intel = &brw->intel; - - /* To ensure that the batch contains only the resolve, flush the batch - * before beginning and after finishing emitting the resolve packets. - * - * Ideally, we would not need to flush for the resolve op. But, I suspect - * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in - * a single batch, and there is no safe way to ensure that other than by - * fencing the resolve with flushes. Ideally, we would just detect if - * a batch is in progress and do the right thing, but that would require - * the ability to *safely* access brw_context::state::dirty::brw - * outside of the brw_upload_state() codepath. - */ - intel_flush(ctx); - - /* CMD_PIPELINE_SELECT - * - * Select the 3D pipeline, as opposed to the media pipeline. - */ - { - BEGIN_BATCH(1); - OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16); - ADVANCE_BATCH(); - } -} - - /** * CMD_STATE_BASE_ADDRESS * @@ -118,15 +61,18 @@ void gen6_blorp_emit_state_base_address(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0; BEGIN_BATCH(10); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); - OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ + OUT_BATCH(mocs << 8 | /* GeneralStateMemoryObjectControlState */ + mocs << 4 | /* StatelessDataPortAccessMemoryObjectControlState */ + 1); /* GeneralStateBaseAddressModifyEnable */ + /* SurfaceStateBaseAddress */ - OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); /* DynamicStateBaseAddress */ - OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | + OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION), 0, 1); OUT_BATCH(1); /* IndirectObjectBaseAddress */ if (params->use_wm_prog) { @@ -152,7 +98,6 @@ void gen6_blorp_emit_vertices(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; uint32_t vertex_offset; /* Setup VBO for the rectangle primitive.. @@ -188,9 +133,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw, float *vertex_data; const float vertices[GEN6_BLORP_VBO_SIZE] = { - /* v0 */ 0, 0, 0, 0, params->x0, params->y1, 0, 1, - /* v1 */ 0, 0, 0, 0, params->x1, params->y1, 0, 1, - /* v2 */ 0, 0, 0, 0, params->x0, params->y0, 0, 1, + /* v0 */ 0, 0, 0, 0, (float) params->x0, (float) params->y1, 0, 1, + /* v1 */ 0, 0, 0, 0, (float) params->x1, (float) params->y1, 0, 1, + /* v2 */ 0, 0, 0, 0, (float) params->x0, (float) params->y0, 0, 1, }; vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER, @@ -207,17 +152,20 @@ gen6_blorp_emit_vertices(struct brw_context *brw, uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA | (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT; - if (intel->gen >= 7) + if (brw->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; + if (brw->gen == 7) + dw0 |= GEN7_MOCS_L3 << 16; + BEGIN_BATCH(batch_length); OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); OUT_BATCH(dw0); /* start address */ - OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, vertex_offset); /* end address */ - OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, + OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, vertex_offset + GEN6_BLORP_VBO_SIZE - 1); OUT_BATCH(0); ADVANCE_BATCH(); @@ -275,8 +223,6 @@ static void gen6_blorp_emit_urb_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT); @@ -303,10 +249,10 @@ gen6_blorp_emit_blend_state(struct brw_context *brw, blend->blend1.post_blend_clamp_enable = 1; blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; - blend->blend1.write_disable_r = false; - blend->blend1.write_disable_g = false; - blend->blend1.write_disable_b = false; - blend->blend1.write_disable_a = false; + blend->blend1.write_disable_r = params->color_write_disable[0]; + blend->blend1.write_disable_g = params->color_write_disable[1]; + blend->blend1.write_disable_b = params->color_write_disable[2]; + blend->blend1.write_disable_a = params->color_write_disable[3]; return cc_blend_state_offset; } @@ -354,7 +300,7 @@ gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, state->ds2.depth_write_enable = 1; if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) { state->ds2.depth_test_enable = 1; - state->ds2.depth_test_func = COMPAREFUNC_NEVER; + state->ds2.depth_test_func = BRW_COMPAREFUNCTION_NEVER; } return depthstencil_offset; @@ -375,8 +321,6 @@ gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, uint32_t depthstencil_offset, uint32_t cc_state_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */ @@ -424,6 +368,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, height /= 2; } struct intel_region *region = surface->mt->region; + uint32_t tile_x, tile_y; uint32_t *surf = (uint32_t *) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, @@ -435,7 +380,8 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT); /* reloc */ - surf[1] = region->bo->offset; /* No tile offsets needed */ + surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) + + region->bo->offset64); surf[2] = (0 << BRW_SURFACE_LOD_SHIFT | (width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -444,7 +390,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, uint32_t tiling = surface->map_stencil_as_y_tiled ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y : brw_get_surface_tiling_bits(region->tiling); - uint32_t pitch_bytes = region->pitch * region->cpp; + uint32_t pitch_bytes = region->pitch; if (surface->map_stencil_as_y_tiled) pitch_bytes *= 2; surf[3] = (tiling | @@ -453,16 +399,21 @@ gen6_blorp_emit_surface_state(struct brw_context *brw, surf[4] = brw_get_surface_num_multisamples(surface->num_samples); - surf[5] = (0 << BRW_SURFACE_X_OFFSET_SHIFT | - 0 << BRW_SURFACE_Y_OFFSET_SHIFT | + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. + */ + assert(tile_x % 4 == 0); + assert(tile_y % 2 == 0); + surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | + (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | (surface->mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); /* Emit relocation to surface contents */ - drm_intel_bo_emit_reloc(brw->intel.batch.bo, + drm_intel_bo_emit_reloc(brw->batch.bo, wm_surf_offset + 4, region->bo, - surf[1] - region->bo->offset, + surf[1] - region->bo->offset64, read_domains, write_domain); return wm_surf_offset; @@ -516,14 +467,14 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw, sampler->ss0.min_mag_neq = 1; - /* Set LOD bias: + /* Set LOD bias: */ sampler->ss0.lod_bias = 0; sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - /* Set BaseMipLevel, MaxLOD, MinLOD: + /* Set BaseMipLevel, MaxLOD, MinLOD: * * XXX: I don't think that using firstLevel, lastLevel works, * because we always setup the surface state as if firstLevel == @@ -556,8 +507,6 @@ gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw, const brw_blorp_params *params, uint32_t sampler_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 | VS_SAMPLER_STATE_CHANGE | @@ -579,10 +528,8 @@ void gen6_blorp_emit_vs_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - - if (intel->gen == 6) { - /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section + if (brw->gen == 6) { + /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, * 3DSTATE_VS, Dword 5.0 "VS Function Enable": * * [DevSNB] A pipeline flush must be programmed prior to a @@ -590,9 +537,18 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw, * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL * command with CS stall bit set and a post sync operation. */ - intel_emit_post_sync_nonzero_flush(intel); + intel_emit_post_sync_nonzero_flush(brw); } + /* Disable the push constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); OUT_BATCH(0); @@ -612,7 +568,14 @@ void gen6_blorp_emit_gs_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + /* Disable all the constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); @@ -644,8 +607,6 @@ void gen6_blorp_emit_clip_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); OUT_BATCH(0); @@ -677,15 +638,13 @@ static void gen6_blorp_emit_sf_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(20); OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */ 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); OUT_BATCH(0); /* dw2 */ - OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); + OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); for (int i = 0; i < 16; ++i) OUT_BATCH(0); ADVANCE_BATCH(); @@ -701,13 +660,12 @@ gen6_blorp_emit_wm_config(struct brw_context *brw, uint32_t prog_offset, brw_blorp_prog_data *prog_data) { - struct intel_context *intel = &brw->intel; uint32_t dw2, dw4, dw5, dw6; /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be - * nonzero to prevent the GPU from hanging. See the valid ranges in the - * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31 - * "Maximum Number Of Threads". + * nonzero to prevent the GPU from hanging. While the documentation doesn't + * mention this explicitly, it notes that the valid range for the field is + * [1,39] = [2,40] threads, which excludes zero. * * To be safe (and to minimize extraneous code) we go ahead and fully * configure the WM state whether or not there is a WM program. @@ -730,7 +688,6 @@ gen6_blorp_emit_wm_config(struct brw_context *brw, assert(0); break; } - dw4 |= GEN6_WM_STATISTICS_ENABLE; dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5; dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; @@ -744,7 +701,7 @@ gen6_blorp_emit_wm_config(struct brw_context *brw, dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */ } - if (params->num_samples > 1) { + if (params->dst.num_samples > 1) { dw6 |= GEN6_WM_MSRAST_ON_PATTERN; if (prog_data && prog_data->persample_msaa_dispatch) dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; @@ -774,8 +731,6 @@ gen6_blorp_emit_constant_ps(struct brw_context *brw, const brw_blorp_params *params, uint32_t wm_push_const_offset) { - struct intel_context *intel = &brw->intel; - /* Make sure the push constants fill an exact integer number of * registers. */ @@ -796,6 +751,19 @@ gen6_blorp_emit_constant_ps(struct brw_context *brw, ADVANCE_BATCH(); } +static void +gen6_blorp_emit_constant_ps_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + /* Disable the push constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} /** * 3DSTATE_BINDING_TABLE_POINTERS @@ -805,8 +773,6 @@ gen6_blorp_emit_binding_table_pointers(struct brw_context *brw, const brw_blorp_params *params, uint32_t wm_bind_bo_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | GEN6_BINDING_TABLE_MODIFY_PS | @@ -822,12 +788,16 @@ static void gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &brw->ctx; uint32_t draw_x = params->depth.x_offset; uint32_t draw_y = params->depth.y_offset; uint32_t tile_mask_x, tile_mask_y; - gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); + brw_get_depthstencil_tile_masks(params->depth.mt, + params->depth.level, + params->depth.layer, + NULL, + &tile_mask_x, &tile_mask_y); /* 3DSTATE_DEPTH_BUFFER */ { @@ -836,7 +806,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t offset = intel_region_get_aligned_offset(params->depth.mt->region, draw_x & ~tile_mask_x, - draw_y & ~tile_mask_y); + draw_y & ~tile_mask_y, false); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth @@ -853,17 +823,18 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, * tile_x and tile_y to 0. This is a temporary workaround until we come * up with a better solution. */ + WARN_ONCE((tile_x & 7) || (tile_y & 7), + "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n" + "Truncating offset, bad rendering may occur.\n"); tile_x &= ~7; tile_y &= ~7; - intel_emit_post_sync_nonzero_flush(intel); - intel_emit_depth_stall_flushes(intel); + intel_emit_post_sync_nonzero_flush(brw); + intel_emit_depth_stall_flushes(brw); BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); - uint32_t pitch_bytes = - params->depth.mt->region->pitch * params->depth.mt->region->cpp; - OUT_BATCH((pitch_bytes - 1) | + OUT_BATCH((params->depth.mt->region->pitch - 1) | params->depth_format << 18 | 1 << 21 | /* separate stencil enable */ 1 << 22 | /* hiz enable */ @@ -889,11 +860,11 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x & ~tile_mask_x, - (draw_y & ~tile_mask_y) / 2); + (draw_y & ~tile_mask_y) / 2, false); BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); + OUT_BATCH(hiz_region->pitch - 1); OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, hiz_offset); @@ -915,7 +886,8 @@ static void gen6_blorp_emit_depth_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + intel_emit_post_sync_nonzero_flush(brw); + intel_emit_depth_stall_flushes(brw); BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); @@ -927,6 +899,18 @@ gen6_blorp_emit_depth_disable(struct brw_context *brw, OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); } @@ -940,8 +924,6 @@ static void gen6_blorp_emit_clear_params(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | GEN5_DEPTH_CLEAR_VALID | @@ -956,7 +938,8 @@ void gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + if (brw->gen == 6) + intel_emit_post_sync_nonzero_flush(brw); BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); @@ -972,7 +955,6 @@ void gen6_blorp_emit_viewport_state(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; struct brw_cc_viewport *ccv; uint32_t cc_vp_offset; @@ -998,8 +980,6 @@ static void gen6_blorp_emit_primitive(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(6); OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) | _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT | @@ -1010,8 +990,10 @@ gen6_blorp_emit_primitive(struct brw_context *brw, OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); -} + /* Only used on Sandybridge; harmless to set elsewhere. */ + brw->batch.need_workaround_flush = true; +} /** * \brief Execute a blit or render pass operation. @@ -1023,11 +1005,9 @@ gen6_blorp_emit_primitive(struct brw_context *brw, * This function alters no GL state. */ void -gen6_blorp_exec(struct intel_context *intel, +gen6_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) { - struct gl_context *ctx = &intel->ctx; - struct brw_context *brw = brw_context(ctx); brw_blorp_prog_data *prog_data = NULL; uint32_t cc_blend_state_offset = 0; uint32_t cc_state_offset = 0; @@ -1036,9 +1016,14 @@ gen6_blorp_exec(struct intel_context *intel, uint32_t wm_bind_bo_offset = 0; uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); - gen6_blorp_emit_batch_head(brw, params); - gen6_emit_3dstate_multisample(brw, params->num_samples); - gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); + + /* Emit workaround flushes when we switch from drawing to blorping. */ + brw->batch.need_workaround_flush = true; + + gen6_emit_3dstate_multisample(brw, params->dst.num_samples); + gen6_emit_3dstate_sample_mask(brw, + params->dst.num_samples > 1 ? + (1 << params->dst.num_samples) - 1 : 1); gen6_blorp_emit_state_base_address(brw, params); gen6_blorp_emit_vertices(brw, params); gen6_blorp_emit_urb_config(brw, params); @@ -1051,16 +1036,19 @@ gen6_blorp_exec(struct intel_context *intel, depthstencil_offset, cc_state_offset); if (params->use_wm_prog) { uint32_t wm_surf_offset_renderbuffer; - uint32_t wm_surf_offset_texture; + uint32_t wm_surf_offset_texture = 0; uint32_t sampler_offset; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); + intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = gen6_blorp_emit_surface_state(brw, params, ¶ms->dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - wm_surf_offset_texture = - gen6_blorp_emit_surface_state(brw, params, ¶ms->src, - I915_GEM_DOMAIN_SAMPLER, 0); + if (params->src.mt) { + wm_surf_offset_texture = + gen6_blorp_emit_surface_state(brw, params, ¶ms->src, + I915_GEM_DOMAIN_SAMPLER, 0); + } wm_bind_bo_offset = gen6_blorp_emit_binding_table(brw, params, wm_surf_offset_renderbuffer, @@ -1074,6 +1062,8 @@ gen6_blorp_exec(struct intel_context *intel, gen6_blorp_emit_sf_config(brw, params); if (params->use_wm_prog) gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset); + else + gen6_blorp_emit_constant_ps_disable(brw, params); gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data); if (params->use_wm_prog) gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset); @@ -1086,14 +1076,5 @@ gen6_blorp_exec(struct intel_context *intel, gen6_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen6_blorp_emit_primitive(brw, params); - - /* See comments above at first invocation of intel_flush() in - * gen6_blorp_emit_batch_head(). - */ - intel_flush(ctx); - - /* Be safe. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; }