X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen6_blorp.cpp;h=b134ab46809f29328e1f215d71551726637b0729;hb=8f37ea414fca66d03f6f4460d6b7730411abb2a2;hp=604d380e70223470deb7488ac98d0953b128f9b5;hpb=c56918246162d9059ce914f36e8df6db0f578909;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index 604d380e702..b134ab46809 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -31,23 +31,48 @@ #include "brw_defines.h" #include "brw_state.h" +#include "brw_blorp.h" #include "gen6_blorp.h" /** - * \name Constants for HiZ VBO + * \name Constants for BLORP VBO * \{ - * - * \see brw_context::hiz::vertex_bo */ -#define GEN6_HIZ_NUM_VERTICES 3 -#define GEN6_HIZ_NUM_VUE_ELEMS 8 -#define GEN6_HIZ_VBO_SIZE (GEN6_HIZ_NUM_VERTICES \ - * GEN6_HIZ_NUM_VUE_ELEMS \ - * sizeof(float)) +#define GEN6_BLORP_NUM_VERTICES 3 +#define GEN6_BLORP_NUM_VUE_ELEMS 8 +#define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \ + * GEN6_BLORP_NUM_VUE_ELEMS \ + * sizeof(float)) /** \} */ + +/** + * Compute masks to determine how much of draw_x and draw_y should be + * performed using the fine adjustment of "depth coordinate offset X/Y" + * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for + * details. + */ +void +gen6_blorp_compute_tile_masks(const brw_blorp_params *params, + uint32_t *tile_mask_x, uint32_t *tile_mask_y) +{ + uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y; + intel_region_get_tile_masks(params->depth.mt->region, + &depth_mask_x, &depth_mask_y); + intel_region_get_tile_masks(params->depth.mt->hiz_mt->region, + &hiz_mask_x, &hiz_mask_y); + + /* Each HiZ row represents 2 rows of pixels */ + hiz_mask_y = hiz_mask_y << 1 | 1; + + *tile_mask_x = depth_mask_x | hiz_mask_x; + *tile_mask_y = depth_mask_y | hiz_mask_y; +} + + void -gen6_hiz_emit_batch_head(struct brw_context *brw) +gen6_blorp_emit_batch_head(struct brw_context *brw, + const brw_blorp_params *params) { struct gl_context *ctx = &brw->intel.ctx; struct intel_context *intel = &brw->intel; @@ -74,65 +99,58 @@ gen6_hiz_emit_batch_head(struct brw_context *brw) OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16); ADVANCE_BATCH(); } +} - /* 3DSTATE_MULTISAMPLE */ - { - int length = intel->gen == 7 ? 4 : 3; - - BEGIN_BATCH(length); - OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (length - 2)); - OUT_BATCH(MS_PIXEL_LOCATION_CENTER | - MS_NUMSAMPLES_1); - OUT_BATCH(0); - if (length >= 4) - OUT_BATCH(0); - ADVANCE_BATCH(); - - } - /* 3DSTATE_SAMPLE_MASK */ - { - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2)); - OUT_BATCH(1); - ADVANCE_BATCH(); - } +/** + * CMD_STATE_BASE_ADDRESS + * + * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS: + * The following commands must be reissued following any change to the + * base addresses: + * 3DSTATE_CC_POINTERS + * 3DSTATE_BINDING_TABLE_POINTERS + * 3DSTATE_SAMPLER_STATE_POINTERS + * 3DSTATE_VIEWPORT_STATE_POINTERS + * MEDIA_STATE_POINTERS + */ +void +gen6_blorp_emit_state_base_address(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; - /* CMD_STATE_BASE_ADDRESS - * - * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS: - * The following commands must be reissued following any change to the - * base addresses: - * 3DSTATE_CC_POINTERS - * 3DSTATE_BINDING_TABLE_POINTERS - * 3DSTATE_SAMPLER_STATE_POINTERS - * 3DSTATE_VIEWPORT_STATE_POINTERS - * MEDIA_STATE_POINTERS - */ - { - BEGIN_BATCH(10); - OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); - OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ - /* SurfaceStateBaseAddress */ - OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); - /* DynamicStateBaseAddress */ - OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | - I915_GEM_DOMAIN_INSTRUCTION), 0, 1); - OUT_BATCH(1); /* IndirectObjectBaseAddress */ + BEGIN_BATCH(10); + OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); + OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ + /* SurfaceStateBaseAddress */ + OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); + /* DynamicStateBaseAddress */ + OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | + I915_GEM_DOMAIN_INSTRUCTION), 0, 1); + OUT_BATCH(1); /* IndirectObjectBaseAddress */ + if (params->use_wm_prog) { + OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + 1); /* Instruction base address: shader kernels */ + } else { OUT_BATCH(1); /* InstructionBaseAddress */ - OUT_BATCH(1); /* GeneralStateUpperBound */ - OUT_BATCH(1); /* DynamicStateUpperBound */ - OUT_BATCH(1); /* IndirectObjectUpperBound*/ - OUT_BATCH(1); /* InstructionAccessUpperBound */ - ADVANCE_BATCH(); } + OUT_BATCH(1); /* GeneralStateUpperBound */ + /* Dynamic state upper bound. Although the documentation says that + * programming it to zero will cause it to be ignored, that is a lie. + * If this isn't programmed to a real bound, the sampler border color + * pointer is rejected, causing border color to mysteriously fail. + */ + OUT_BATCH(0xfffff001); + OUT_BATCH(1); /* IndirectObjectUpperBound*/ + OUT_BATCH(1); /* InstructionAccessUpperBound */ + ADVANCE_BATCH(); } + void -gen6_hiz_emit_vertices(struct brw_context *brw, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int layer) +gen6_blorp_emit_vertices(struct brw_context *brw, + const brw_blorp_params *params) { struct intel_context *intel = &brw->intel; uint32_t vertex_offset; @@ -167,20 +185,18 @@ gen6_hiz_emit_vertices(struct brw_context *brw, * "Vertex URB Entry (VUE) Formats". */ { - const int width = mt->level[level].width; - const int height = mt->level[level].height; float *vertex_data; - const float vertices[GEN6_HIZ_VBO_SIZE] = { - /* v0 */ 0, 0, 0, 0, 0, height, 0, 1, - /* v1 */ 0, 0, 0, 0, width, height, 0, 1, - /* v2 */ 0, 0, 0, 0, 0, 0, 0, 1, + const float vertices[GEN6_BLORP_VBO_SIZE] = { + /* v0 */ 0, 0, 0, 0, params->x0, params->y1, 0, 1, + /* v1 */ 0, 0, 0, 0, params->x1, params->y1, 0, 1, + /* v2 */ 0, 0, 0, 0, params->x0, params->y0, 0, 1, }; - vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_NO_TYPE, - GEN6_HIZ_VBO_SIZE, 32, + vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER, + GEN6_BLORP_VBO_SIZE, 32, &vertex_offset); - memcpy(vertex_data, vertices, GEN6_HIZ_VBO_SIZE); + memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE); } /* 3DSTATE_VERTEX_BUFFERS */ @@ -189,7 +205,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw, const int batch_length = 1 + 4 * num_buffers; uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA | - (GEN6_HIZ_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT; + (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT; if (intel->gen >= 7) dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; @@ -202,7 +218,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw, vertex_offset); /* end address */ OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, - vertex_offset + GEN6_HIZ_VBO_SIZE - 1); + vertex_offset + GEN6_BLORP_VBO_SIZE - 1); OUT_BATCH(0); ADVANCE_BATCH(); } @@ -210,7 +226,7 @@ gen6_hiz_emit_vertices(struct brw_context *brw, /* 3DSTATE_VERTEX_ELEMENTS * * Fetch dwords 0 - 7 from each VUE. See the comments above where - * hiz->vertex_bo is filled with data. + * the vertex_bo is filled with data. */ { const int num_elements = 2; @@ -238,255 +254,592 @@ gen6_hiz_emit_vertices(struct brw_context *brw, } } -/** - * \brief Execute a HiZ op on a miptree slice. - * - * To execute the HiZ op, this function manually constructs and emits a batch - * to "draw" the HiZ op's rectangle primitive. The batchbuffer is flushed - * before constructing and after emitting the batch. + +/* 3DSTATE_URB * - * This function alters no GL state. + * Assign the entire URB to the VS. Even though the VS disabled, URB space + * is still needed because the clipper loads the VUE's from the URB. From + * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE, + * Dword 1.15:0 "VS Number of URB Entries": + * This field is always used (even if VS Function Enable is DISABLED). * - * For an overview of HiZ ops, see the following sections of the Sandy Bridge - * PRM, Volume 1, Part 2: - * - 7.5.3.1 Depth Buffer Clear - * - 7.5.3.2 Depth Buffer Resolve - * - 7.5.3.3 Hierarchical Depth Buffer Resolve + * The warning below appears in the PRM (Section 3DSTATE_URB), but we can + * safely ignore it because this batch contains only one draw call. + * Because of URB corruption caused by allocating a previous GS unit + * URB entry to the VS unit, software is required to send a “GS NULL + * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0) + * plus a dummy DRAW call before any case where VS will be taking over + * GS URB space. */ static void -gen6_hiz_exec(struct intel_context *intel, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int layer, - enum gen6_hiz_op op) +gen6_blorp_emit_urb_config(struct brw_context *brw, + const brw_blorp_params *params) { - struct gl_context *ctx = &intel->ctx; - struct brw_context *brw = brw_context(ctx); - uint32_t draw_x, draw_y; - uint32_t tile_mask_x, tile_mask_y; + struct intel_context *intel = &brw->intel; - assert(op != GEN6_HIZ_OP_DEPTH_CLEAR); /* Not implemented yet. */ - assert(mt->hiz_mt != NULL); - intel_miptree_check_level_layer(mt, level, layer); + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); + OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT); + OUT_BATCH(0); + ADVANCE_BATCH(); +} - { - /* Construct a dummy renderbuffer just to extract tile offsets. */ - struct intel_renderbuffer rb; - rb.mt = mt; - rb.mt_level = level; - rb.mt_layer = layer; - intel_renderbuffer_set_draw_offset(&rb); - draw_x = rb.draw_x; - draw_y = rb.draw_y; - } - /* Compute masks to determine how much of draw_x and draw_y should be - * performed using the fine adjustment of "depth coordinate offset X/Y" - * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for - * details. - */ - { - uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y; - intel_region_get_tile_masks(mt->region, &depth_mask_x, &depth_mask_y); - intel_region_get_tile_masks(mt->hiz_mt->region, - &hiz_mask_x, &hiz_mask_y); +/* BLEND_STATE */ +uint32_t +gen6_blorp_emit_blend_state(struct brw_context *brw, + const brw_blorp_params *params) +{ + uint32_t cc_blend_state_offset; - /* Each HiZ row represents 2 rows of pixels */ - hiz_mask_y = hiz_mask_y << 1 | 1; + struct gen6_blend_state *blend = (struct gen6_blend_state *) + brw_state_batch(brw, AUB_TRACE_BLEND_STATE, + sizeof(struct gen6_blend_state), 64, + &cc_blend_state_offset); - tile_mask_x = depth_mask_x | hiz_mask_x; - tile_mask_y = depth_mask_y | hiz_mask_y; - } + memset(blend, 0, sizeof(*blend)); - gen6_hiz_emit_batch_head(brw); - gen6_hiz_emit_vertices(brw, mt, level, layer); + blend->blend1.pre_blend_clamp_enable = 1; + blend->blend1.post_blend_clamp_enable = 1; + blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; - /* 3DSTATE_URB - * - * Assign the entire URB to the VS. Even though the VS disabled, URB space - * is still needed because the clipper loads the VUE's from the URB. From - * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE, - * Dword 1.15:0 "VS Number of URB Entries": - * This field is always used (even if VS Function Enable is DISABLED). - * - * The warning below appears in the PRM (Section 3DSTATE_URB), but we can - * safely ignore it because this batch contains only one draw call. - * Because of URB corruption caused by allocating a previous GS unit - * URB entry to the VS unit, software is required to send a “GS NULL - * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0) - * plus a dummy DRAW call before any case where VS will be taking over - * GS URB space. + blend->blend1.write_disable_r = false; + blend->blend1.write_disable_g = false; + blend->blend1.write_disable_b = false; + blend->blend1.write_disable_a = false; + + return cc_blend_state_offset; +} + + +/* CC_STATE */ +uint32_t +gen6_blorp_emit_cc_state(struct brw_context *brw, + const brw_blorp_params *params) +{ + uint32_t cc_state_offset; + + struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *) + brw_state_batch(brw, AUB_TRACE_CC_STATE, + sizeof(gen6_color_calc_state), 64, + &cc_state_offset); + memset(cc, 0, sizeof(*cc)); + + return cc_state_offset; +} + + +/** + * \param out_offset is relative to + * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. + */ +uint32_t +gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, + const brw_blorp_params *params) +{ + uint32_t depthstencil_offset; + + struct gen6_depth_stencil_state *state; + state = (struct gen6_depth_stencil_state *) + brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, + sizeof(*state), 64, + &depthstencil_offset); + memset(state, 0, sizeof(*state)); + + /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2: + * - 7.5.3.1 Depth Buffer Clear + * - 7.5.3.2 Depth Buffer Resolve + * - 7.5.3.3 Hierarchical Depth Buffer Resolve */ - { - BEGIN_BATCH(3); - OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); - OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT); - OUT_BATCH(0); - ADVANCE_BATCH(); + state->ds2.depth_write_enable = 1; + if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) { + state->ds2.depth_test_enable = 1; + state->ds2.depth_test_func = COMPAREFUNC_NEVER; } - /* 3DSTATE_CC_STATE_POINTERS - * - * The pointer offsets are relative to - * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. - * - * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE. - */ - { - uint32_t depthstencil_offset; - gen6_hiz_emit_depth_stencil_state(brw, op, &depthstencil_offset); - - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); - OUT_BATCH(1); /* BLEND_STATE offset */ - OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */ - OUT_BATCH(1); /* COLOR_CALC_STATE offset */ - ADVANCE_BATCH(); + return depthstencil_offset; +} + + +/* 3DSTATE_CC_STATE_POINTERS + * + * The pointer offsets are relative to + * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. + * + * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE. + */ +static void +gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t cc_blend_state_offset, + uint32_t depthstencil_offset, + uint32_t cc_state_offset) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); + OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */ + OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */ + OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */ + ADVANCE_BATCH(); +} + + +/* WM push constants */ +uint32_t +gen6_blorp_emit_wm_constants(struct brw_context *brw, + const brw_blorp_params *params) +{ + uint32_t wm_push_const_offset; + + void *constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS, + sizeof(params->wm_push_consts), + 32, &wm_push_const_offset); + memcpy(constants, ¶ms->wm_push_consts, + sizeof(params->wm_push_consts)); + + return wm_push_const_offset; +} + + +/* SURFACE_STATE for renderbuffer or texture surface (see + * brw_update_renderbuffer_surface and brw_update_texture_surface) + */ +static uint32_t +gen6_blorp_emit_surface_state(struct brw_context *brw, + const brw_blorp_params *params, + const brw_blorp_surface_info *surface, + uint32_t read_domains, uint32_t write_domain) +{ + uint32_t wm_surf_offset; + uint32_t width, height; + surface->get_miplevel_dims(&width, &height); + if (surface->num_samples > 0) { /* TODO: seems clumsy */ + width /= 2; + height /= 2; + } + if (surface->map_stencil_as_y_tiled) { + width *= 2; + height /= 2; } + struct intel_region *region = surface->mt->region; + + uint32_t *surf = (uint32_t *) + brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, + &wm_surf_offset); + + surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | + BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | + BRW_SURFACE_CUBEFACE_ENABLES | + surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT); + + /* reloc */ + surf[1] = region->bo->offset; /* No tile offsets needed */ + + surf[2] = (0 << BRW_SURFACE_LOD_SHIFT | + (width - 1) << BRW_SURFACE_WIDTH_SHIFT | + (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); + + uint32_t tiling = surface->map_stencil_as_y_tiled + ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y + : brw_get_surface_tiling_bits(region->tiling); + uint32_t pitch_bytes = region->pitch * region->cpp; + if (surface->map_stencil_as_y_tiled) + pitch_bytes *= 2; + surf[3] = (tiling | + 0 << BRW_SURFACE_DEPTH_SHIFT | + (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT); + + surf[4] = brw_get_surface_num_multisamples(surface->num_samples); + + surf[5] = (0 << BRW_SURFACE_X_OFFSET_SHIFT | + 0 << BRW_SURFACE_Y_OFFSET_SHIFT | + (surface->mt->align_h == 4 ? + BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); + + /* Emit relocation to surface contents */ + drm_intel_bo_emit_reloc(brw->intel.batch.bo, + wm_surf_offset + 4, + region->bo, + surf[1] - region->bo->offset, + read_domains, write_domain); + + return wm_surf_offset; +} + + +/* BINDING_TABLE. See brw_wm_binding_table(). */ +uint32_t +gen6_blorp_emit_binding_table(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t wm_surf_offset_renderbuffer, + uint32_t wm_surf_offset_texture) +{ + uint32_t wm_bind_bo_offset; + uint32_t *bind = (uint32_t *) + brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, + sizeof(uint32_t) * + BRW_BLORP_NUM_BINDING_TABLE_ENTRIES, + 32, /* alignment */ + &wm_bind_bo_offset); + bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] = + wm_surf_offset_renderbuffer; + bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture; + + return wm_bind_bo_offset; +} + + +/** + * SAMPLER_STATE. See brw_update_sampler_state(). + */ +static uint32_t +gen6_blorp_emit_sampler_state(struct brw_context *brw, + const brw_blorp_params *params) +{ + uint32_t sampler_offset; + + struct brw_sampler_state *sampler = (struct brw_sampler_state *) + brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, + sizeof(struct brw_sampler_state), + 32, &sampler_offset); + memset(sampler, 0, sizeof(*sampler)); + + sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR; + sampler->ss0.mip_filter = BRW_MIPFILTER_NONE; + sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR; + + sampler->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; + + sampler->ss0.min_mag_neq = 1; + + /* Set LOD bias: + */ + sampler->ss0.lod_bias = 0; + + sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ + sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - /* 3DSTATE_VS + /* Set BaseMipLevel, MaxLOD, MinLOD: * - * Disable vertex shader. + * XXX: I don't think that using firstLevel, lastLevel works, + * because we always setup the surface state as if firstLevel == + * level zero. Probably have to subtract firstLevel from each of + * these: */ - { + sampler->ss0.base_level = U_FIXED(0, 1); + + sampler->ss1.max_lod = U_FIXED(0, 6); + sampler->ss1.min_lod = U_FIXED(0, 6); + + sampler->ss3.non_normalized_coord = 1; + + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | + BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | + BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | + BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | + BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; + + return sampler_offset; +} + + +/** + * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers(). + */ +static void +gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t sampler_offset) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 | + VS_SAMPLER_STATE_CHANGE | + GS_SAMPLER_STATE_CHANGE | + PS_SAMPLER_STATE_CHANGE | + (4 - 2)); + OUT_BATCH(0); /* VS */ + OUT_BATCH(0); /* GS */ + OUT_BATCH(sampler_offset); + ADVANCE_BATCH(); +} + + +/* 3DSTATE_VS + * + * Disable vertex shader. + */ +void +gen6_blorp_emit_vs_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + if (intel->gen == 6) { /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section * 3DSTATE_VS, Dword 5.0 "VS Function Enable": - * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS - * command that causes the VS Function Enable to toggle. Pipeline - * flush can be executed by sending a PIPE_CONTROL command with CS - * stall bit set and a post sync operation. + * + * [DevSNB] A pipeline flush must be programmed prior to a + * 3DSTATE_VS command that causes the VS Function Enable to + * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL + * command with CS stall bit set and a post sync operation. */ intel_emit_post_sync_nonzero_flush(intel); - - BEGIN_BATCH(6); - OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); } - /* 3DSTATE_GS - * - * Disable the geometry shader. - */ - { - BEGIN_BATCH(7); - OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } + BEGIN_BATCH(6); + OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} - /* 3DSTATE_CLIP - * - * Disable the clipper. - * - * The HiZ op emits a rectangle primitive, which requires clipping to - * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1 - * Section 1.3 "3D Primitives Overview": - * RECTLIST: - * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip - * Mode should be set to a value other than CLIPMODE_NORMAL. - * - * Also disable perspective divide. This doesn't change the clipper's - * output, but does spare a few electrons. - */ - { - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); - OUT_BATCH(0); - OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE); + +/* 3DSTATE_GS + * + * Disable the geometry shader. + */ +void +gen6_blorp_emit_gs_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + + +/* 3DSTATE_CLIP + * + * Disable the clipper. + * + * The BLORP op emits a rectangle primitive, which requires clipping to + * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1 + * Section 1.3 "3D Primitives Overview": + * RECTLIST: + * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip + * Mode should be set to a value other than CLIPMODE_NORMAL. + * + * Also disable perspective divide. This doesn't change the clipper's + * output, but does spare a few electrons. + */ +void +gen6_blorp_emit_clip_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + + +/* 3DSTATE_SF + * + * Disable ViewportTransformEnable (dw2.1) + * + * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D + * Primitives Overview": + * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the + * use of screen- space coordinates). + * + * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3) + * and BackFaceFillMode (dw2.5:6) to SOLID(0). + * + * From the Sandy Bridge PRM, Volume 2, Part 1, Section + * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: + * SOLID: Any triangle or rectangle object found to be front-facing + * is rendered as a solid object. This setting is required when + * (rendering rectangle (RECTLIST) objects. + */ +static void +gen6_blorp_emit_sf_config(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(20); + OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); + OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */ + 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | + 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); + OUT_BATCH(0); /* dw2 */ + OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0); + for (int i = 0; i < 16; ++i) OUT_BATCH(0); - ADVANCE_BATCH(); - } + ADVANCE_BATCH(); +} - /* 3DSTATE_SF - * - * Disable ViewportTransformEnable (dw2.1) - * - * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D - * Primitives Overview": - * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the - * use of screen- space coordinates). - * - * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3) - * and BackFaceFillMode (dw2.5:6) to SOLID(0). - * - * From the Sandy Bridge PRM, Volume 2, Part 1, Section - * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: - * SOLID: Any triangle or rectangle object found to be front-facing - * is rendered as a solid object. This setting is required when - * (rendering rectangle (RECTLIST) objects. - */ - { - BEGIN_BATCH(20); - OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); - OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */ - 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | - 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); - for (int i = 0; i < 18; ++i) - OUT_BATCH(0); - ADVANCE_BATCH(); - } - /* 3DSTATE_WM - * - * Disable thread dispatch (dw5.19) and enable the HiZ op. - * - * Even though thread dispatch is disabled, max threads (dw5.25:31) must be +/** + * Enable or disable thread dispatch and set the HiZ op appropriately. + */ +static void +gen6_blorp_emit_wm_config(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t prog_offset, + brw_blorp_prog_data *prog_data) +{ + struct intel_context *intel = &brw->intel; + uint32_t dw2, dw4, dw5, dw6; + + /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be * nonzero to prevent the GPU from hanging. See the valid ranges in the * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31 * "Maximum Number Of Threads". + * + * To be safe (and to minimize extraneous code) we go ahead and fully + * configure the WM state whether or not there is a WM program. */ - { - uint32_t dw4 = 0; - - switch (op) { - case GEN6_HIZ_OP_DEPTH_CLEAR: - assert(!"not implemented"); - dw4 |= GEN6_WM_DEPTH_CLEAR; - break; - case GEN6_HIZ_OP_DEPTH_RESOLVE: - dw4 |= GEN6_WM_DEPTH_RESOLVE; - break; - case GEN6_HIZ_OP_HIZ_RESOLVE: - dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE; - break; - default: - assert(0); - break; - } - - BEGIN_BATCH(9); - OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(dw4); - OUT_BATCH((brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT); - OUT_BATCH((1 - 1) << GEN6_WM_NUM_SF_OUTPUTS_SHIFT); /* only position */ - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); + + dw2 = dw4 = dw5 = dw6 = 0; + switch (params->hiz_op) { + case GEN6_HIZ_OP_DEPTH_CLEAR: + dw4 |= GEN6_WM_DEPTH_CLEAR; + break; + case GEN6_HIZ_OP_DEPTH_RESOLVE: + dw4 |= GEN6_WM_DEPTH_RESOLVE; + break; + case GEN6_HIZ_OP_HIZ_RESOLVE: + dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE; + break; + case GEN6_HIZ_OP_NONE: + break; + default: + assert(0); + break; + } + dw4 |= GEN6_WM_STATISTICS_ENABLE; + dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; + dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5; + dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; + dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ + dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */ + if (params->use_wm_prog) { + dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ + dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0; + dw5 |= GEN6_WM_16_DISPATCH_ENABLE; + dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */ + dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */ } + if (params->num_samples > 0) { + dw6 |= GEN6_WM_MSRAST_ON_PATTERN; + if (prog_data && prog_data->persample_msaa_dispatch) + dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; + else + dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL; + } else { + dw6 |= GEN6_WM_MSRAST_OFF_PIXEL; + dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; + } + + BEGIN_BATCH(9); + OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2)); + OUT_BATCH(params->use_wm_prog ? prog_offset : 0); + OUT_BATCH(dw2); + OUT_BATCH(0); /* No scratch needed */ + OUT_BATCH(dw4); + OUT_BATCH(dw5); + OUT_BATCH(dw6); + OUT_BATCH(0); /* No other programs */ + OUT_BATCH(0); /* No other programs */ + ADVANCE_BATCH(); +} + + +static void +gen6_blorp_emit_constant_ps(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t wm_push_const_offset) +{ + struct intel_context *intel = &brw->intel; + + /* Make sure the push constants fill an exact integer number of + * registers. + */ + assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0); + + /* There must be at least one register worth of push constant data. */ + assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0); + + /* Enable push constant buffer 0. */ + BEGIN_BATCH(5); + OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | + GEN6_CONSTANT_BUFFER_0_ENABLE | + (5 - 2)); + OUT_BATCH(wm_push_const_offset + (BRW_BLORP_NUM_PUSH_CONST_REGS - 1)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + + +/** + * 3DSTATE_BINDING_TABLE_POINTERS + */ +static void +gen6_blorp_emit_binding_table_pointers(struct brw_context *brw, + const brw_blorp_params *params, + uint32_t wm_bind_bo_offset) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | + GEN6_BINDING_TABLE_MODIFY_PS | + (4 - 2)); + OUT_BATCH(0); /* vs -- ignored */ + OUT_BATCH(0); /* gs -- ignored */ + OUT_BATCH(wm_bind_bo_offset); /* wm/ps */ + ADVANCE_BATCH(); +} + + +static void +gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + uint32_t draw_x, draw_y; + uint32_t tile_mask_x, tile_mask_y; + + gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); + params->depth.get_draw_offsets(&draw_x, &draw_y); + /* 3DSTATE_DEPTH_BUFFER */ { - uint32_t width = mt->level[level].width; - uint32_t height = mt->level[level].height; + uint32_t width, height; + params->depth.get_miplevel_dims(&width, &height); uint32_t tile_x = draw_x & tile_mask_x; uint32_t tile_y = draw_y & tile_mask_y; - uint32_t offset = intel_region_get_aligned_offset(mt->region, - draw_x & ~tile_mask_x, - draw_y & ~tile_mask_y); + uint32_t offset = + intel_region_get_aligned_offset(params->depth.mt->region, + draw_x & ~tile_mask_x, + draw_y & ~tile_mask_y); /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth @@ -506,27 +859,21 @@ gen6_hiz_exec(struct intel_context *intel, tile_x &= ~7; tile_y &= ~7; - uint32_t format; - switch (mt->format) { - case MESA_FORMAT_Z16: format = BRW_DEPTHFORMAT_D16_UNORM; break; - case MESA_FORMAT_Z32_FLOAT: format = BRW_DEPTHFORMAT_D32_FLOAT; break; - case MESA_FORMAT_X8_Z24: format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; break; - default: assert(0); break; - } - intel_emit_post_sync_nonzero_flush(intel); intel_emit_depth_stall_flushes(intel); BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); - OUT_BATCH(((mt->region->pitch * mt->region->cpp) - 1) | - format << 18 | + uint32_t pitch_bytes = + params->depth.mt->region->pitch * params->depth.mt->region->cpp; + OUT_BATCH((pitch_bytes - 1) | + params->depth_format << 18 | 1 << 21 | /* separate stencil enable */ 1 << 22 | /* hiz enable */ BRW_TILEWALK_YMAJOR << 26 | 1 << 27 | /* y-tiled */ BRW_SURFACE_2D << 29); - OUT_RELOC(mt->region->bo, + OUT_RELOC(params->depth.mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 | @@ -541,7 +888,7 @@ gen6_hiz_exec(struct intel_context *intel, /* 3DSTATE_HIER_DEPTH_BUFFER */ { - struct intel_region *hiz_region = mt->hiz_mt->region; + struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; uint32_t hiz_offset = intel_region_get_aligned_offset(hiz_region, draw_x & ~tile_mask_x, @@ -564,99 +911,192 @@ gen6_hiz_exec(struct intel_context *intel, OUT_BATCH(0); ADVANCE_BATCH(); } +} - /* 3DSTATE_CLEAR_PARAMS - * - * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: - * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE - * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes. - */ - { - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2)); - OUT_BATCH(0); - ADVANCE_BATCH(); - } - /* 3DSTATE_DRAWING_RECTANGLE */ - { - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); - OUT_BATCH(0); - OUT_BATCH(((mt->level[level].width - 1) & 0xffff) | - ((mt->level[level].height - 1) << 16)); - OUT_BATCH(0); - ADVANCE_BATCH(); - } +static void +gen6_blorp_emit_depth_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; - /* 3DPRIMITIVE */ - { - BEGIN_BATCH(6); - OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) | - _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT | - GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); - OUT_BATCH(3); /* vertex count per instance */ - OUT_BATCH(0); - OUT_BATCH(1); /* instance count */ - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); + OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | + (BRW_SURFACE_NULL << 29)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} - /* See comments above at first invocation of intel_flush() in - * gen6_hiz_emit_batch_head(). - */ - intel_flush(ctx); - /* Be safe. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; +/* 3DSTATE_CLEAR_PARAMS + * + * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: + * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE + * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes. + */ +static void +gen6_blorp_emit_clear_params(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | + GEN5_DEPTH_CLEAR_VALID | + (2 - 2)); + OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0); + ADVANCE_BATCH(); } -/** - * \param out_offset is relative to - * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. - */ + +/* 3DSTATE_DRAWING_RECTANGLE */ void -gen6_hiz_emit_depth_stencil_state(struct brw_context *brw, - enum gen6_hiz_op op, - uint32_t *out_offset) +gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, + const brw_blorp_params *params) { - struct gen6_depth_stencil_state *state; - state = (struct gen6_depth_stencil_state *) - brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, - sizeof(*state), 64, - out_offset); - memset(state, 0, sizeof(*state)); + struct intel_context *intel = &brw->intel; - /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2: - * - 7.5.3.1 Depth Buffer Clear - * - 7.5.3.2 Depth Buffer Resolve - * - 7.5.3.3 Hierarchical Depth Buffer Resolve - */ - state->ds2.depth_write_enable = 1; - if (op == GEN6_HIZ_OP_DEPTH_RESOLVE) { - state->ds2.depth_test_enable = 1; - state->ds2.depth_test_func = COMPAREFUNC_NEVER; - } + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(((params->x1 - 1) & 0xffff) | + ((params->y1 - 1) << 16)); + OUT_BATCH(0); + ADVANCE_BATCH(); } -/** \see intel_context::vtbl::resolve_hiz_slice */ +/* 3DSTATE_VIEWPORT_STATE_POINTERS */ void -gen6_resolve_hiz_slice(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) +gen6_blorp_emit_viewport_state(struct brw_context *brw, + const brw_blorp_params *params) { - gen6_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); + struct intel_context *intel = &brw->intel; + struct brw_cc_viewport *ccv; + uint32_t cc_vp_offset; + + ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE, + sizeof(*ccv), 32, + &cc_vp_offset); + + ccv->min_depth = 0.0; + ccv->max_depth = 1.0; + + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) | + GEN6_CC_VIEWPORT_MODIFY); + OUT_BATCH(0); /* clip VP */ + OUT_BATCH(0); /* SF VP */ + OUT_BATCH(cc_vp_offset); + ADVANCE_BATCH(); } -/** \see intel_context::vtbl::resolve_depth_slice */ + +/* 3DPRIMITIVE */ +static void +gen6_blorp_emit_primitive(struct brw_context *brw, + const brw_blorp_params *params) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(6); + OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) | + _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT | + GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); + OUT_BATCH(3); /* vertex count per instance */ + OUT_BATCH(0); + OUT_BATCH(1); /* instance count */ + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + + +/** + * \brief Execute a blit or render pass operation. + * + * To execute the operation, this function manually constructs and emits a + * batch to draw a rectangle primitive. The batchbuffer is flushed before + * constructing and after emitting the batch. + * + * This function alters no GL state. + */ void -gen6_resolve_depth_slice(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) +gen6_blorp_exec(struct intel_context *intel, + const brw_blorp_params *params) { - gen6_hiz_exec(intel, mt, level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE); + struct gl_context *ctx = &intel->ctx; + struct brw_context *brw = brw_context(ctx); + brw_blorp_prog_data *prog_data = NULL; + uint32_t cc_blend_state_offset = 0; + uint32_t cc_state_offset = 0; + uint32_t depthstencil_offset; + uint32_t wm_push_const_offset = 0; + uint32_t wm_bind_bo_offset = 0; + + uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); + gen6_blorp_emit_batch_head(brw, params); + gen6_emit_3dstate_multisample(brw, params->num_samples); + gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); + gen6_blorp_emit_state_base_address(brw, params); + gen6_blorp_emit_vertices(brw, params); + gen6_blorp_emit_urb_config(brw, params); + if (params->use_wm_prog) { + cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); + cc_state_offset = gen6_blorp_emit_cc_state(brw, params); + } + depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); + gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset, + depthstencil_offset, cc_state_offset); + if (params->use_wm_prog) { + uint32_t wm_surf_offset_renderbuffer; + uint32_t wm_surf_offset_texture; + uint32_t sampler_offset; + wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); + wm_surf_offset_renderbuffer = + gen6_blorp_emit_surface_state(brw, params, ¶ms->dst, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + wm_surf_offset_texture = + gen6_blorp_emit_surface_state(brw, params, ¶ms->src, + I915_GEM_DOMAIN_SAMPLER, 0); + wm_bind_bo_offset = + gen6_blorp_emit_binding_table(brw, params, + wm_surf_offset_renderbuffer, + wm_surf_offset_texture); + sampler_offset = gen6_blorp_emit_sampler_state(brw, params); + gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset); + } + gen6_blorp_emit_vs_disable(brw, params); + gen6_blorp_emit_gs_disable(brw, params); + gen6_blorp_emit_clip_disable(brw, params); + gen6_blorp_emit_sf_config(brw, params); + if (params->use_wm_prog) + gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset); + gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data); + if (params->use_wm_prog) + gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset); + gen6_blorp_emit_viewport_state(brw, params); + + if (params->depth.mt) + gen6_blorp_emit_depth_stencil_config(brw, params); + else + gen6_blorp_emit_depth_disable(brw, params); + gen6_blorp_emit_clear_params(brw, params); + gen6_blorp_emit_drawing_rectangle(brw, params); + gen6_blorp_emit_primitive(brw, params); + + /* See comments above at first invocation of intel_flush() in + * gen6_blorp_emit_batch_head(). + */ + intel_flush(ctx); + + /* Be safe. */ + brw->state.dirty.brw = ~0; + brw->state.dirty.cache = ~0; } +