X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen6_cc.c;h=3bab8f46ae8fbca6d00b06cd09b9982cea878d5f;hb=8a688bee83ced46eb4bff741f05d2da033c07ade;hp=b61a816cd875f3807e1af98803dd824ebef17e67;hpb=4bec2e31bfb6aad5b3af16f463211e51d1e67217;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index b61a816cd87..3bab8f46ae8 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -32,12 +32,14 @@ #include "intel_batchbuffer.h" #include "main/macros.h" #include "main/enums.h" +#include "main/glformats.h" +#include "main/stencil.h" static void gen6_upload_blend_state(struct brw_context *brw) { bool is_buffer_zero_integer_format = false; - struct gl_context *ctx = &brw->intel.ctx; + struct gl_context *ctx = &brw->ctx; struct gen6_blend_state *blend; int b; int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers; @@ -49,7 +51,7 @@ gen6_upload_blend_state(struct brw_context *brw) * with render target 0, which will reference BLEND_STATE[0] for * alpha test enable. */ - if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled) + if (nr_draw_buffers == 0) nr_draw_buffers = 1; size = sizeof(*blend) * nr_draw_buffers; @@ -95,8 +97,8 @@ gen6_upload_blend_state(struct brw_context *brw) rb_type != GL_UNSIGNED_NORMALIZED && rb_type != GL_FLOAT, "Ignoring %s logic op on %s " "renderbuffer\n", - _mesa_lookup_enum_by_nr(ctx->Color.LogicOp), - _mesa_lookup_enum_by_nr(rb_type)); + _mesa_enum_to_string(ctx->Color.LogicOp), + _mesa_enum_to_string(rb_type)); if (rb_type == GL_UNSIGNED_NORMALIZED) { blend[b].blend1.logic_op_enable = 1; blend[b].blend1.logic_op_func = @@ -118,6 +120,21 @@ gen6_upload_blend_state(struct brw_context *brw) srcA = dstA = GL_ONE; } + /* Due to hardware limitations, the destination may have information + * in an alpha channel even when the format specifies no alpha + * channel. In order to avoid getting any incorrect blending due to + * that alpha channel, coerce the blend factors to values that will + * not read the alpha channel, but will instead use the correct + * implicit value for alpha. + */ + if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat, GL_TEXTURE_ALPHA_TYPE)) + { + srcRGB = brw_fix_xRGB_alpha(srcRGB); + srcA = brw_fix_xRGB_alpha(srcA); + dstRGB = brw_fix_xRGB_alpha(dstRGB); + dstA = brw_fix_xRGB_alpha(dstA); + } + blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB); blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB); blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB); @@ -198,7 +215,7 @@ gen6_upload_blend_state(struct brw_context *brw) blend[b].blend1.alpha_to_one = ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne; - blend[b].blend1.alpha_to_coverage_dither = (brw->intel.gen >= 7); + blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7); } else { blend[b].blend1.alpha_to_coverage = false; @@ -206,16 +223,29 @@ gen6_upload_blend_state(struct brw_context *brw) } } - brw->state.dirty.cache |= CACHE_NEW_BLEND_STATE; + /* Point the GPU at the new indirect state. */ + if (brw->gen == 6) { + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); + OUT_BATCH(brw->cc.blend_state_offset | 1); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.blend_state_offset | 1); + ADVANCE_BATCH(); + } } const struct brw_tracked_state gen6_blend_state = { .dirty = { - .mesa = (_NEW_COLOR | - _NEW_BUFFERS | - _NEW_MULTISAMPLE), - .brw = BRW_NEW_BATCH, - .cache = 0, + .mesa = _NEW_BUFFERS | + _NEW_COLOR | + _NEW_MULTISAMPLE, + .brw = BRW_NEW_BATCH | + BRW_NEW_STATE_BASE_ADDRESS, }, .emit = gen6_upload_blend_state, }; @@ -223,7 +253,7 @@ const struct brw_tracked_state gen6_blend_state = { static void gen6_upload_color_calc_state(struct brw_context *brw) { - struct gl_context *ctx = &brw->intel.ctx; + struct gl_context *ctx = &brw->ctx; struct gen6_color_calc_state *cc; cc = brw_state_batch(brw, AUB_TRACE_CC_STATE, @@ -234,9 +264,12 @@ gen6_upload_color_calc_state(struct brw_context *brw) cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef); - /* _NEW_STENCIL */ - cc->cc0.stencil_ref = ctx->Stencil.Ref[0]; - cc->cc0.bf_stencil_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace]; + if (brw->gen < 9) { + /* _NEW_STENCIL */ + cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0); + cc->cc0.bf_stencil_ref = + _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace); + } /* _NEW_COLOR */ cc->constant_r = ctx->Color.BlendColorUnclamped[0]; @@ -244,38 +277,28 @@ gen6_upload_color_calc_state(struct brw_context *brw) cc->constant_b = ctx->Color.BlendColorUnclamped[2]; cc->constant_a = ctx->Color.BlendColorUnclamped[3]; - brw->state.dirty.cache |= CACHE_NEW_COLOR_CALC_STATE; + /* Point the GPU at the new indirect state. */ + if (brw->gen == 6) { + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(brw->cc.state_offset | 1); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(2); + OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); + OUT_BATCH(brw->cc.state_offset | 1); + ADVANCE_BATCH(); + } } const struct brw_tracked_state gen6_color_calc_state = { .dirty = { - .mesa = _NEW_COLOR | _NEW_STENCIL, - .brw = BRW_NEW_BATCH, - .cache = 0, + .mesa = _NEW_COLOR | + _NEW_STENCIL, + .brw = BRW_NEW_BATCH | + BRW_NEW_STATE_BASE_ADDRESS, }, .emit = gen6_upload_color_calc_state, }; - -static void upload_cc_state_pointers(struct brw_context *brw) -{ - struct intel_context *intel = &brw->intel; - - BEGIN_BATCH(4); - OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); - OUT_BATCH(brw->cc.blend_state_offset | 1); - OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); - OUT_BATCH(brw->cc.state_offset | 1); - ADVANCE_BATCH(); -} - -const struct brw_tracked_state gen6_cc_state_pointers = { - .dirty = { - .mesa = 0, - .brw = (BRW_NEW_BATCH | - BRW_NEW_STATE_BASE_ADDRESS), - .cache = (CACHE_NEW_BLEND_STATE | - CACHE_NEW_COLOR_CALC_STATE | - CACHE_NEW_DEPTH_STENCIL_STATE) - }, - .emit = upload_cc_state_pointers, -};