X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen6_wm_state.c;h=cda7c11d9340f32d5343d4cae39e99aebc229973;hb=700bebb958e93f4d472c383de62ced9db8e64bec;hp=4a5aa129d41f6bfec6163440ec34d7d98a581fc4;hpb=b0f8768905c84b3aa69a44030d998d1076d77728;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index 4a5aa129d41..cda7c11d934 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -28,11 +28,13 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" +#include "compiler/brw_eu_defines.h" #include "brw_util.h" #include "brw_wm.h" #include "program/program.h" #include "program/prog_parameter.h" #include "program/prog_statevars.h" +#include "main/shaderapi.h" #include "main/framebuffer.h" #include "intel_batchbuffer.h" @@ -41,12 +43,13 @@ gen6_upload_wm_push_constants(struct brw_context *brw) { struct brw_stage_state *stage_state = &brw->wm.base; /* BRW_NEW_FRAGMENT_PROGRAM */ - const struct brw_fragment_program *fp = - brw_fragment_program_const(brw->fragment_program); + const struct brw_program *fp = brw_program_const(brw->fragment_program); /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; + const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data; - gen6_upload_push_constants(brw, &fp->program.Base, &prog_data->base, + _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_FRAGMENT); + + gen6_upload_push_constants(brw, &fp->program, prog_data, stage_state, AUB_TRACE_WM_CONSTANTS); if (brw->gen >= 7) { @@ -77,6 +80,7 @@ gen6_upload_wm_state(struct brw_context *brw, bool line_stipple_enable, bool polygon_stipple_enable, bool statistic_enable) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t dw2, dw4, dw5, dw6, ksp0, ksp2; /* We can't fold this into gen6_upload_wm_push_constants(), because @@ -127,31 +131,21 @@ gen6_upload_wm_state(struct brw_context *brw, dw2 |= ((prog_data->base.binding_table.size_bytes / 4) << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT); - dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; + dw5 |= (devinfo->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; + + if (prog_data->dispatch_8) + dw5 |= GEN6_WM_8_DISPATCH_ENABLE; - if (prog_data->prog_offset_16 || prog_data->no_8) { + if (prog_data->dispatch_16) dw5 |= GEN6_WM_16_DISPATCH_ENABLE; - if (!prog_data->no_8 && !prog_data->persample_dispatch) { - dw5 |= GEN6_WM_8_DISPATCH_ENABLE; - dw4 |= (prog_data->base.dispatch_grf_start_reg << - GEN6_WM_DISPATCH_START_GRF_SHIFT_0); - dw4 |= (prog_data->dispatch_grf_start_reg_16 << - GEN6_WM_DISPATCH_START_GRF_SHIFT_2); - ksp0 = stage_state->prog_offset; - ksp2 = stage_state->prog_offset + prog_data->prog_offset_16; - } else { - dw4 |= (prog_data->dispatch_grf_start_reg_16 << - GEN6_WM_DISPATCH_START_GRF_SHIFT_0); - ksp0 = stage_state->prog_offset + prog_data->prog_offset_16; - } - } - else { - dw5 |= GEN6_WM_8_DISPATCH_ENABLE; - dw4 |= (prog_data->base.dispatch_grf_start_reg << - GEN6_WM_DISPATCH_START_GRF_SHIFT_0); - ksp0 = stage_state->prog_offset; - } + dw4 |= prog_data->base.dispatch_grf_start_reg << + GEN6_WM_DISPATCH_START_GRF_SHIFT_0; + dw4 |= prog_data->dispatch_grf_start_reg_2 << + GEN6_WM_DISPATCH_START_GRF_SHIFT_2; + + ksp0 = stage_state->prog_offset; + ksp2 = stage_state->prog_offset + prog_data->prog_offset_2; if (dual_source_blend_enable) dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE; @@ -200,37 +194,6 @@ gen6_upload_wm_state(struct brw_context *brw, dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; else { dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL; - - /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping - * (Dispatch Size) Control"), p.334: - * - * Note: in the table below, the Valid column indicates which - * products that combination is supported on. Combinations of - * dispatch enables not listed in the table are not available on - * any product. - * - * A: Valid on all products - * - * B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader - * computed depth. - * - * D: Valid on all products, except when in non-1x PERSAMPLE mode - * (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x - * PERPIXEL mode with pixel shader computed depth. - * - * E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader - * computed depth. - * - * F: Valid on all products, except not valid on [DevSNB] if 4x - * PERPIXEL mode with pixel shader computed depth. - * - * In the table that follows, the only entry with "A" in the Valid - * column is the entry where only 8 pixel dispatch is enabled. - * Therefore, when we are in PERPIXEL mode with pixel shader computed - * depth, we need to disable SIMD16 dispatch. - */ - if (dw5 & GEN6_WM_COMPUTED_DEPTH) - dw5 &= ~GEN6_WM_16_DISPATCH_ENABLE; } } else { dw6 |= GEN6_WM_MSRAST_OFF_PIXEL; @@ -261,7 +224,7 @@ gen6_upload_wm_state(struct brw_context *brw, if (prog_data->base.total_scratch) { OUT_RELOC(stage_state->scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - ffs(prog_data->base.total_scratch) - 11); + ffs(stage_state->per_thread_scratch) - 11); } else { OUT_BATCH(0); } @@ -278,7 +241,8 @@ upload_wm_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; + const struct brw_wm_prog_data *prog_data = + brw_wm_prog_data(brw->wm.base.prog_data); /* _NEW_BUFFERS */ const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1; @@ -288,9 +252,10 @@ upload_wm_state(struct brw_context *brw) (ctx->Color.BlendEnabled & 1) && ctx->Color.Blend[0]._UsesDualSrc; - /* _NEW_COLOR, _NEW_MULTISAMPLE */ - const bool kill_enable = prog_data->uses_kill || ctx->Color.AlphaEnabled || - ctx->Multisample.SampleAlphaToCoverage || + /* _NEW_COLOR, _NEW_MULTISAMPLE _NEW_BUFFERS */ + const bool kill_enable = prog_data->uses_kill || + _mesa_is_alpha_test_enabled(ctx) || + _mesa_is_alpha_to_coverage_enabled(ctx) || prog_data->uses_omask; /* Rendering against the gl-context is always taken into account. */