X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen7_blorp.cpp;h=4bf93964a82f43716b7405d0082a08ae34d900c6;hb=a92e5f7cf63d496ad7830b5cea4bbab287c25b8e;hp=00f13a532128aaf5a38200764bf43d257ebf06f5;hpb=f04f219906e40a6647a10fd9c1928509fe25fb84;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 00f13a53212..4bf93964a82 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -40,8 +40,9 @@ * 3DSTATE_URB_DS * 3DSTATE_URB_GS * - * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the - * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS: + * If the 3DSTATE_URB_VS is emitted, than the others must be also. + * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS: + * * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be * programmed in order for the programming of this state to be * valid. @@ -50,14 +51,22 @@ static void gen7_blorp_emit_urb_config(struct brw_context *brw, const brw_blorp_params *params) { - /* The minimum valid value is 32. See 3DSTATE_URB_VS, - * Dword 1.15:0 "VS Number of URB Entries". + unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16; + gen7_emit_push_constant_state(brw, + urb_size / 2 /* vs_size */, + 0 /* gs_size */, + urb_size / 2 /* fs_size */); + + /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword + * 1.15:0 "VS Number of URB Entries". */ - int num_vs_entries = 32; - int vs_size = 2; - int vs_start = 2; /* skip over push constants */ - - gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start); + gen7_emit_urb_state(brw, + 32 /* num_vs_entries */, + 2 /* vs_size */, + 2 /* vs_start */, + 0 /* num_gs_entries */, + 1 /* gs_size */, + 2 /* gs_start */); } @@ -67,8 +76,6 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, const brw_blorp_params *params, uint32_t cc_blend_state_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); OUT_BATCH(cc_blend_state_offset | 1); @@ -82,8 +89,6 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, const brw_blorp_params *params, uint32_t cc_state_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); OUT_BATCH(cc_state_offset | 1); @@ -94,7 +99,6 @@ static void gen7_blorp_emit_cc_viewport(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; struct brw_cc_viewport *ccv; uint32_t cc_vp_offset; @@ -120,8 +124,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, const brw_blorp_params *params, uint32_t depthstencil_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); OUT_BATCH(depthstencil_offset | 1); @@ -139,8 +141,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, uint32_t read_domains, uint32_t write_domain, bool is_render_target) { - struct intel_context *intel = &brw->intel; - uint32_t wm_surf_offset; uint32_t width = surface->width; uint32_t height = surface->height; @@ -151,65 +151,70 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, */ struct intel_region *region = surface->mt->region; uint32_t tile_x, tile_y; + const uint8_t mocs = GEN7_MOCS_L3; + + uint32_t tiling = surface->map_stencil_as_y_tiled + ? I915_TILING_Y : region->tiling; - struct gen7_surface_state *surf = (struct gen7_surface_state *) - brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32, - &wm_surf_offset); - memset(surf, 0, sizeof(*surf)); + uint32_t *surf = (uint32_t *) + brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset); + memset(surf, 0, 8 * 4); + + surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | + surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT | + gen7_surface_tiling_mode(tiling); if (surface->mt->align_h == 4) - surf->ss0.vertical_alignment = 1; + surf[0] |= GEN7_SURFACE_VALIGN_4; if (surface->mt->align_w == 8) - surf->ss0.horizontal_alignment = 1; + surf[0] |= GEN7_SURFACE_HALIGN_8; - surf->ss0.surface_format = surface->brw_surfaceformat; - surf->ss0.surface_type = BRW_SURFACE_2D; - surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ? - GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL; + if (surface->array_spacing_lod0) + surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; + else + surf[0] |= GEN7_SURFACE_ARYSPC_FULL; /* reloc */ - surf->ss1.base_addr = surface->compute_tile_offsets(&tile_x, &tile_y); - surf->ss1.base_addr += region->bo->offset; + surf[1] = + surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset64; /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. */ assert(tile_x % 4 == 0); assert(tile_y % 2 == 0); - surf->ss5.x_offset = tile_x / 4; - surf->ss5.y_offset = tile_y / 2; + surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) | + SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) | + SET_FIELD(mocs, GEN7_SURFACE_MOCS); - surf->ss2.width = width - 1; - surf->ss2.height = height - 1; - - uint32_t tiling = surface->map_stencil_as_y_tiled - ? I915_TILING_Y : region->tiling; - gen7_set_surface_tiling(surf, tiling); + surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) | + SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT); - uint32_t pitch_bytes = region->pitch * region->cpp; + uint32_t pitch_bytes = region->pitch; if (surface->map_stencil_as_y_tiled) pitch_bytes *= 2; - surf->ss3.pitch = pitch_bytes - 1; + surf[3] = pitch_bytes - 1; - gen7_set_surface_msaa(surf, surface->num_samples, surface->msaa_layout); - if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { - gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, - surface->mt->mcs_mt, is_render_target); + surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout); + if (surface->mt->mcs_mt) { + gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt, + is_render_target); } - if (intel->is_haswell) { - surf->ss7.shader_channel_select_r = HSW_SCS_RED; - surf->ss7.shader_channel_select_g = HSW_SCS_GREEN; - surf->ss7.shader_channel_select_b = HSW_SCS_BLUE; - surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA; + surf[7] = surface->mt->fast_clear_color_value; + + if (brw->is_haswell) { + surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A)); } /* Emit relocation to surface contents */ - drm_intel_bo_emit_reloc(brw->intel.batch.bo, - wm_surf_offset + - offsetof(struct gen7_surface_state, ss1), + drm_intel_bo_emit_reloc(brw->batch.bo, + wm_surf_offset + 4, region->bo, - surf->ss1.base_addr - region->bo->offset, + surf[1] - region->bo->offset64, read_domains, write_domain); gen7_check_surface_setup(surf, is_render_target); @@ -243,14 +248,14 @@ gen7_blorp_emit_sampler_state(struct brw_context *brw, // sampler->ss0.min_mag_neq = 1; - /* Set LOD bias: + /* Set LOD bias: */ sampler->ss0.lod_bias = 0; sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - /* Set BaseMipLevel, MaxLOD, MinLOD: + /* Set BaseMipLevel, MaxLOD, MinLOD: * * XXX: I don't think that using firstLevel, lastLevel works, * because we always setup the surface state as if firstLevel == @@ -275,6 +280,35 @@ gen7_blorp_emit_sampler_state(struct brw_context *brw, } +/* 3DSTATE_VS + * + * Disable vertex shader. + */ +static void +gen7_blorp_emit_vs_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(6); + OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + + /* 3DSTATE_HS * * Disable the hull shader. @@ -283,7 +317,15 @@ static void gen7_blorp_emit_hs_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); @@ -305,8 +347,6 @@ static void gen7_blorp_emit_te_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); OUT_BATCH(0); @@ -324,7 +364,15 @@ static void gen7_blorp_emit_ds_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2)); @@ -336,6 +384,50 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw, ADVANCE_BATCH(); } +/* 3DSTATE_GS + * + * Disable the geometry shader. + */ +static void +gen7_blorp_emit_gs_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + /** + * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages > + * Geometry > Geometry Shader > State: + * + * "Note: Because of corruption in IVB:GT2, software needs to flush the + * whole fixed function pipeline when the GS enable changes value in + * the 3DSTATE_GS." + * + * The hardware architects have clarified that in this context "flush the + * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS + * Stall" bit set. + */ + if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled) + gen7_emit_cs_stall_flush(brw); + + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + brw->gs.enabled = false; +} /* 3DSTATE_STREAMOUT * @@ -345,8 +437,6 @@ static void gen7_blorp_emit_streamout_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); OUT_BATCH(0); @@ -359,8 +449,6 @@ static void gen7_blorp_emit_sf_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - /* 3DSTATE_SF * * Disable ViewportTransformEnable (dw1.1) @@ -384,7 +472,7 @@ gen7_blorp_emit_sf_config(struct brw_context *brw, OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2)); OUT_BATCH(params->depth_format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); - OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); + OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); @@ -414,8 +502,6 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, const brw_blorp_params *params, brw_blorp_prog_data *prog_data) { - struct intel_context *intel = &brw->intel; - uint32_t dw1 = 0, dw2 = 0; switch (params->hiz_op) { @@ -434,7 +520,6 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, assert(0); break; } - dw1 |= GEN7_WM_STATISTICS_ENABLE; dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ @@ -443,7 +528,7 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */ } - if (params->num_samples > 1) { + if (params->dst.num_samples > 1) { dw1 |= GEN7_WM_MSRAST_ON_PATTERN; if (prog_data && prog_data->persample_msaa_dispatch) dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; @@ -467,8 +552,8 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, * * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite * that, thread dispatch info must still be specified. - * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec - * states that the valid range for this field is [0x3, 0x2f]. + * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the + * valid range for this field is [0x3, 0x2f]. * - A dispatch mode must be given; that is, at least one of the * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was * discovered through simulator error messages. @@ -479,9 +564,8 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, uint32_t prog_offset, brw_blorp_prog_data *prog_data) { - struct intel_context *intel = &brw->intel; uint32_t dw2, dw4, dw5; - const int max_threads_shift = brw->intel.is_haswell ? + const int max_threads_shift = brw->is_haswell ? HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT; dw2 = dw4 = dw5 = 0; @@ -495,7 +579,7 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, */ dw4 |= GEN7_PS_16_DISPATCH_ENABLE; - if (intel->is_haswell) + if (brw->is_haswell) dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ if (params->use_wm_prog) { dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ @@ -503,6 +587,17 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; } + switch (params->fast_clear_op) { + case GEN7_FAST_CLEAR_OP_FAST_CLEAR: + dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE; + break; + case GEN7_FAST_CLEAR_OP_RESOLVE: + dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE; + break; + default: + break; + } + BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(params->use_wm_prog ? prog_offset : 0); @@ -521,8 +616,6 @@ gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, const brw_blorp_params *params, uint32_t wm_bind_bo_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); OUT_BATCH(wm_bind_bo_offset); @@ -535,8 +628,6 @@ gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, const brw_blorp_params *params, uint32_t sampler_offset) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); OUT_BATCH(sampler_offset); @@ -549,7 +640,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw, const brw_blorp_params *params, uint32_t wm_push_const_offset) { - struct intel_context *intel = &brw->intel; + const uint8_t mocs = GEN7_MOCS_L3; /* Make sure the push constants fill an exact integer number of * registers. @@ -565,89 +656,112 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw, (7 - 2)); OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS); OUT_BATCH(0); - OUT_BATCH(wm_push_const_offset); + OUT_BATCH(wm_push_const_offset | mocs); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } +static void +gen7_blorp_emit_constant_ps_disable(struct brw_context *brw, + const brw_blorp_params *params) +{ + BEGIN_BATCH(7); + OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} static void gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - uint32_t draw_x = params->depth.x_offset; - uint32_t draw_y = params->depth.y_offset; - uint32_t tile_mask_x, tile_mask_y; + const uint8_t mocs = GEN7_MOCS_L3; + uint32_t surfwidth, surfheight; + uint32_t surftype; + unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1); + unsigned int min_array_element; + GLenum gl_target = params->depth.mt->target; + unsigned int lod; + + switch (gl_target) { + case GL_TEXTURE_CUBE_MAP_ARRAY: + case GL_TEXTURE_CUBE_MAP: + /* The PRM claims that we should use BRW_SURFACE_CUBE for this + * situation, but experiments show that gl_Layer doesn't work when we do + * this. So we use BRW_SURFACE_2D, since for rendering purposes this is + * equivalent. + */ + surftype = BRW_SURFACE_2D; + depth *= 6; + break; + default: + surftype = translate_tex_target(gl_target); + break; + } - gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); + min_array_element = params->depth.layer; + if (params->depth.mt->num_samples > 1) { + /* Convert physical layer to logical layer. */ + min_array_element /= params->depth.mt->num_samples; + } - /* 3DSTATE_DEPTH_BUFFER */ - { - uint32_t tile_x = draw_x & tile_mask_x; - uint32_t tile_y = draw_y & tile_mask_y; - uint32_t offset = - intel_region_get_aligned_offset(params->depth.mt->region, - draw_x & ~tile_mask_x, - draw_y & ~tile_mask_y); - - /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 - * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth - * Coordinate Offset X/Y": - * - * "The 3 LSBs of both offsets must be zero to ensure correct - * alignment" - * - * We have no guarantee that tile_x and tile_y are correctly aligned, - * since they are determined by the mipmap layout, which is only aligned - * to multiples of 4. - * - * So, to avoid hanging the GPU, just smash the low order 3 bits of - * tile_x and tile_y to 0. This is a temporary workaround until we come - * up with a better solution. + lod = params->depth.level - params->depth.mt->first_level; + + if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) { + /* HIZ ops for lod 0 may set the width & height a little + * larger to allow the fast depth clear to fit the hardware + * alignment requirements. (8x4) */ - tile_x &= ~7; - tile_y &= ~7; + surfwidth = params->depth.width; + surfheight = params->depth.height; + } else { + surfwidth = params->depth.mt->logical_width0; + surfheight = params->depth.mt->logical_height0; + } - intel_emit_depth_stall_flushes(intel); + /* 3DSTATE_DEPTH_BUFFER */ + { + intel_emit_depth_stall_flushes(brw); BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); - uint32_t pitch_bytes = - params->depth.mt->region->pitch * params->depth.mt->region->cpp; - OUT_BATCH((pitch_bytes - 1) | + OUT_BATCH((params->depth.mt->region->pitch - 1) | params->depth_format << 18 | 1 << 22 | /* hiz enable */ 1 << 28 | /* depth write */ - BRW_SURFACE_2D << 29); + surftype << 29); OUT_RELOC(params->depth.mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - offset); - OUT_BATCH((params->depth.width + tile_x - 1) << 4 | - (params->depth.height + tile_y - 1) << 18); - OUT_BATCH(0); - OUT_BATCH(tile_x | - tile_y << 16); + 0); + OUT_BATCH((surfwidth - 1) << 4 | + (surfheight - 1) << 18 | + lod); + OUT_BATCH(((depth - 1) << 21) | + (min_array_element << 10) | + mocs); OUT_BATCH(0); + OUT_BATCH((depth - 1) << 21); ADVANCE_BATCH(); } /* 3DSTATE_HIER_DEPTH_BUFFER */ { struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; - uint32_t hiz_offset = - intel_region_get_aligned_offset(hiz_region, - draw_x & ~tile_mask_x, - (draw_y & ~tile_mask_y) / 2); BEGIN_BATCH(3); OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); + OUT_BATCH((mocs << 25) | + (hiz_region->pitch - 1)); OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - hiz_offset); + 0); ADVANCE_BATCH(); } @@ -666,7 +780,7 @@ static void gen7_blorp_emit_depth_disable(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; + intel_emit_depth_stall_flushes(brw); BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); @@ -677,14 +791,26 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw, OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); } /* 3DSTATE_CLEAR_PARAMS * - * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2 + * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4 * 3DSTATE_CLEAR_PARAMS: - * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along + * 3DSTATE_CLEAR_PARAMS must always be programmed in the along * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER, * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER). */ @@ -692,8 +818,6 @@ static void gen7_blorp_emit_clear_params(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0); @@ -707,8 +831,6 @@ static void gen7_blorp_emit_primitive(struct brw_context *brw, const brw_blorp_params *params) { - struct intel_context *intel = &brw->intel; - BEGIN_BATCH(7); OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2)); OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL | @@ -726,11 +848,12 @@ gen7_blorp_emit_primitive(struct brw_context *brw, * \copydoc gen6_blorp_exec() */ void -gen7_blorp_exec(struct intel_context *intel, +gen7_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) { - struct gl_context *ctx = &intel->ctx; - struct brw_context *brw = brw_context(ctx); + if (brw->gen >= 8) + return; + brw_blorp_prog_data *prog_data = NULL; uint32_t cc_blend_state_offset = 0; uint32_t cc_state_offset = 0; @@ -740,10 +863,10 @@ gen7_blorp_exec(struct intel_context *intel, uint32_t sampler_offset = 0; uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); - gen6_blorp_emit_batch_head(brw, params); - gen7_allocate_push_constants(brw); - gen6_emit_3dstate_multisample(brw, params->num_samples); - gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); + gen6_emit_3dstate_multisample(brw, params->dst.num_samples); + gen6_emit_3dstate_sample_mask(brw, + params->dst.num_samples > 1 ? + (1 << params->dst.num_samples) - 1 : 1); gen6_blorp_emit_state_base_address(brw, params); gen6_blorp_emit_vertices(brw, params); gen7_blorp_emit_urb_config(brw, params); @@ -758,28 +881,31 @@ gen7_blorp_exec(struct intel_context *intel, depthstencil_offset); if (params->use_wm_prog) { uint32_t wm_surf_offset_renderbuffer; - uint32_t wm_surf_offset_texture; + uint32_t wm_surf_offset_texture = 0; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); + intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, true /* is_render_target */); - wm_surf_offset_texture = - gen7_blorp_emit_surface_state(brw, params, ¶ms->src, - I915_GEM_DOMAIN_SAMPLER, 0, - false /* is_render_target */); + if (params->src.mt) { + wm_surf_offset_texture = + gen7_blorp_emit_surface_state(brw, params, ¶ms->src, + I915_GEM_DOMAIN_SAMPLER, 0, + false /* is_render_target */); + } wm_bind_bo_offset = gen6_blorp_emit_binding_table(brw, params, wm_surf_offset_renderbuffer, wm_surf_offset_texture); sampler_offset = gen7_blorp_emit_sampler_state(brw, params); } - gen6_blorp_emit_vs_disable(brw, params); + gen7_blorp_emit_vs_disable(brw, params); gen7_blorp_emit_hs_disable(brw, params); gen7_blorp_emit_te_disable(brw, params); gen7_blorp_emit_ds_disable(brw, params); - gen6_blorp_emit_gs_disable(brw, params); + gen7_blorp_emit_gs_disable(brw, params); gen7_blorp_emit_streamout_disable(brw, params); gen6_blorp_emit_clip_disable(brw, params); gen7_blorp_emit_sf_config(brw, params); @@ -789,6 +915,8 @@ gen7_blorp_exec(struct intel_context *intel, wm_bind_bo_offset); gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset); gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset); + } else { + gen7_blorp_emit_constant_ps_disable(brw, params); } gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data); gen7_blorp_emit_cc_viewport(brw, params); @@ -800,13 +928,4 @@ gen7_blorp_exec(struct intel_context *intel, gen7_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen7_blorp_emit_primitive(brw, params); - - /* See comments above at first invocation of intel_flush() in - * gen6_blorp_emit_batch_head(). - */ - intel_flush(ctx); - - /* Be safe. */ - brw->state.dirty.brw = ~0; - brw->state.dirty.cache = ~0; }