X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen7_blorp.cpp;h=e1e855951f878c9f8f5b8c2ade188dc7513d3004;hb=0ae360f098d88450f73f2b2176a6839ab593da2a;hp=0fa352aebfeb6ca58dc80d3815eb3fd7f3f23c57;hpb=2273b652bb884a6188af7f8d063d0d0fc5497054;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 0fa352aebfe..e1e855951f8 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -24,16 +24,25 @@ #include #include "intel_batchbuffer.h" -#include "intel_fbo.h" #include "intel_mipmap_tree.h" #include "brw_context.h" -#include "brw_defines.h" #include "brw_state.h" #include "brw_blorp.h" -#include "gen7_blorp.h" +static bool +gen7_blorp_skip_urb_config(const struct brw_context *brw) +{ + if (brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) + return false; + + /* Vertex elements along with full VUE header take 96 bytes. As the size + * is expressed in 64 bytes, one needs at least two times that, otherwise + * the setup can be any valid configuration. + */ + return brw->urb.vsize >= 2; +} /* 3DSTATE_URB_VS * 3DSTATE_URB_HS @@ -47,25 +56,52 @@ * programmed in order for the programming of this state to be * valid. */ -static void -gen7_blorp_emit_urb_config(struct brw_context *brw, - const brw_blorp_params *params) +void +gen7_blorp_emit_urb_config(struct brw_context *brw) { - /* The minimum valid value is 32. See 3DSTATE_URB_VS, - * Dword 1.15:0 "VS Number of URB Entries". - */ - int num_vs_entries = 32; - int vs_size = 2; - int vs_start = 2; /* skip over push constants */ - - gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start); + /* URB allocations must be done in 8k chunks. */ + const unsigned chunk_size_bytes = 8192; + const unsigned urb_size = + (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16; + const unsigned push_constant_bytes = 1024 * urb_size; + const unsigned push_constant_chunks = + push_constant_bytes / chunk_size_bytes; + const unsigned vs_size = 2; + const unsigned vs_start = push_constant_chunks; + const unsigned vs_chunks = + DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes); + + if (gen7_blorp_skip_urb_config(brw)) + return; + + brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE; + + gen7_emit_push_constant_state(brw, + urb_size / 2 /* vs_size */, + 0 /* hs_size */, + 0 /* ds_size */, + 0 /* gs_size */, + urb_size / 2 /* fs_size */); + + gen7_emit_urb_state(brw, + brw->urb.min_vs_entries /* num_vs_entries */, + vs_size, + vs_start, + 0 /* num_hs_entries */, + 1 /* hs_size */, + vs_start + vs_chunks /* hs_start */, + 0 /* num_ds_entries */, + 1 /* ds_size */, + vs_start + vs_chunks /* ds_start */, + 0 /* num_gs_entries */, + 1 /* gs_size */, + vs_start + vs_chunks /* gs_start */); } /* 3DSTATE_BLEND_STATE_POINTERS */ -static void +void gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, - const brw_blorp_params *params, uint32_t cc_blend_state_offset) { BEGIN_BATCH(2); @@ -76,9 +112,8 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw, /* 3DSTATE_CC_STATE_POINTERS */ -static void +void gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, - const brw_blorp_params *params, uint32_t cc_state_offset) { BEGIN_BATCH(2); @@ -87,9 +122,8 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw, ADVANCE_BATCH(); } -static void -gen7_blorp_emit_cc_viewport(struct brw_context *brw, - const brw_blorp_params *params) +void +gen7_blorp_emit_cc_viewport(struct brw_context *brw) { struct brw_cc_viewport *ccv; uint32_t cc_vp_offset; @@ -113,7 +147,6 @@ gen7_blorp_emit_cc_viewport(struct brw_context *brw, */ static void gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, - const brw_blorp_params *params, uint32_t depthstencil_offset) { BEGIN_BATCH(2); @@ -128,7 +161,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw, */ static uint32_t gen7_blorp_emit_surface_state(struct brw_context *brw, - const brw_blorp_params *params, const brw_blorp_surface_info *surface, uint32_t read_domains, uint32_t write_domain, bool is_render_target) @@ -141,12 +173,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, * to divide them by 2 as we do for Gen6 (see * gen6_blorp_emit_surface_state). */ - struct intel_region *region = surface->mt->region; + struct intel_mipmap_tree *mt = surface->mt; uint32_t tile_x, tile_y; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; uint32_t tiling = surface->map_stencil_as_y_tiled - ? I915_TILING_Y : region->tiling; + ? I915_TILING_Y : mt->tiling; uint32_t *surf = (uint32_t *) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset); @@ -156,19 +188,19 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT | gen7_surface_tiling_mode(tiling); - if (surface->mt->align_h == 4) + if (surface->mt->valign == 4) surf[0] |= GEN7_SURFACE_VALIGN_4; - if (surface->mt->align_w == 8) + if (surface->mt->halign == 8) surf[0] |= GEN7_SURFACE_HALIGN_8; - if (surface->array_spacing_lod0) + if (surface->array_layout == ALL_SLICES_AT_EACH_LOD) surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; else surf[0] |= GEN7_SURFACE_ARYSPC_FULL; /* reloc */ surf[1] = - surface->compute_tile_offsets(&tile_x, &tile_y) + region->bo->offset; + surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64; /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. @@ -182,7 +214,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) | SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT); - uint32_t pitch_bytes = region->pitch; + uint32_t pitch_bytes = mt->pitch; if (surface->map_stencil_as_y_tiled) pitch_bytes *= 2; surf[3] = pitch_bytes - 1; @@ -205,8 +237,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->batch.bo, wm_surf_offset + 4, - region->bo, - surf[1] - region->bo->offset, + mt->bo, + surf[1] - mt->bo->offset64, read_domains, write_domain); gen7_check_surface_setup(surf, is_render_target); @@ -215,70 +247,12 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, } -/** - * SAMPLER_STATE. See gen7_update_sampler_state(). - */ -static uint32_t -gen7_blorp_emit_sampler_state(struct brw_context *brw, - const brw_blorp_params *params) -{ - uint32_t sampler_offset; - - struct gen7_sampler_state *sampler = (struct gen7_sampler_state *) - brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, - sizeof(struct gen7_sampler_state), - 32, &sampler_offset); - memset(sampler, 0, sizeof(*sampler)); - - sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR; - sampler->ss0.mip_filter = BRW_MIPFILTER_NONE; - sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR; - - sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; - sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; - sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; - - // sampler->ss0.min_mag_neq = 1; - - /* Set LOD bias: - */ - sampler->ss0.lod_bias = 0; - - sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ - sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ - - /* Set BaseMipLevel, MaxLOD, MinLOD: - * - * XXX: I don't think that using firstLevel, lastLevel works, - * because we always setup the surface state as if firstLevel == - * level zero. Probably have to subtract firstLevel from each of - * these: - */ - sampler->ss0.base_level = U_FIXED(0, 1); - - sampler->ss1.max_lod = U_FIXED(0, 8); - sampler->ss1.min_lod = U_FIXED(0, 8); - - sampler->ss3.non_normalized_coord = 1; - - sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | - BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; - sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | - BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; - - return sampler_offset; -} - - /* 3DSTATE_VS * * Disable vertex shader. */ static void -gen7_blorp_emit_vs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_vs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); @@ -306,8 +280,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw, * Disable the hull shader. */ static void -gen7_blorp_emit_hs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_hs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2)); @@ -335,9 +308,8 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw, * * Disable the tesselation engine. */ -static void -gen7_blorp_emit_te_disable(struct brw_context *brw, - const brw_blorp_params *params) +void +gen7_blorp_emit_te_disable(struct brw_context *brw) { BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2)); @@ -353,8 +325,7 @@ gen7_blorp_emit_te_disable(struct brw_context *brw, * Disable the domain shader. */ static void -gen7_blorp_emit_ds_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_ds_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2)); @@ -381,8 +352,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw, * Disable the geometry shader. */ static void -gen7_blorp_emit_gs_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_gs_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2)); @@ -394,6 +364,21 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw, OUT_BATCH(0); ADVANCE_BATCH(); + /** + * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages > + * Geometry > Geometry Shader > State: + * + * "Note: Because of corruption in IVB:GT2, software needs to flush the + * whole fixed function pipeline when the GS enable changes value in + * the 3DSTATE_GS." + * + * The hardware architects have clarified that in this context "flush the + * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS + * Stall" bit set. + */ + if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled) + gen7_emit_cs_stall_flush(brw); + BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); OUT_BATCH(0); @@ -403,6 +388,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw, OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + brw->gs.enabled = false; } /* 3DSTATE_STREAMOUT @@ -410,8 +396,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw, * Disable streamout. */ static void -gen7_blorp_emit_streamout_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_streamout_disable(struct brw_context *brw) { BEGIN_BATCH(3); OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2)); @@ -448,7 +433,7 @@ gen7_blorp_emit_sf_config(struct brw_context *brw, OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2)); OUT_BATCH(params->depth_format << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); - OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); + OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); @@ -460,9 +445,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw, { BEGIN_BATCH(14); OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2)); - OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */ + OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE | + params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT | 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT | - 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); + BRW_SF_URB_ENTRY_READ_OFFSET << + GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT); for (int i = 0; i < 12; ++i) OUT_BATCH(0); ADVANCE_BATCH(); @@ -493,18 +480,19 @@ gen7_blorp_emit_wm_config(struct brw_context *brw, case GEN6_HIZ_OP_NONE: break; default: - assert(0); - break; + unreachable("not reached"); } dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ - if (params->use_wm_prog) { - dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */ + + if (params->use_wm_prog) dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */ - } - if (params->num_samples > 1) { + if (params->src.mt) + dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */ + + if (params->dst.num_samples > 1) { dw1 |= GEN7_WM_MSRAST_ON_PATTERN; if (prog_data && prog_data->persample_msaa_dispatch) dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; @@ -558,21 +546,14 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, if (brw->is_haswell) dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */ if (params->use_wm_prog) { - dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; } - switch (params->fast_clear_op) { - case GEN7_FAST_CLEAR_OP_FAST_CLEAR: - dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE; - break; - case GEN7_FAST_CLEAR_OP_RESOLVE: - dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE; - break; - default: - break; - } + if (params->src.mt) + dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ + + dw4 |= params->fast_clear_op; BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); @@ -587,9 +568,8 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, } -static void +void gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_bind_bo_offset) { BEGIN_BATCH(2); @@ -599,9 +579,8 @@ gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw, } -static void +void gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t sampler_offset) { BEGIN_BATCH(2); @@ -611,12 +590,11 @@ gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw, } -static void +void gen7_blorp_emit_constant_ps(struct brw_context *brw, - const brw_blorp_params *params, uint32_t wm_push_const_offset) { - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; /* Make sure the push constants fill an exact integer number of * registers. @@ -639,9 +617,8 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw, ADVANCE_BATCH(); } -static void -gen7_blorp_emit_constant_ps_disable(struct brw_context *brw, - const brw_blorp_params *params) +void +gen7_blorp_emit_constant_ps_disable(struct brw_context *brw) { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); @@ -658,82 +635,86 @@ static void gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, const brw_blorp_params *params) { - struct gl_context *ctx = &brw->ctx; - uint32_t draw_x = params->depth.x_offset; - uint32_t draw_y = params->depth.y_offset; - uint32_t tile_mask_x, tile_mask_y; + const uint8_t mocs = GEN7_MOCS_L3; + uint32_t surfwidth, surfheight; + uint32_t surftype; + unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1); + unsigned int min_array_element; + GLenum gl_target = params->depth.mt->target; + unsigned int lod; + + switch (gl_target) { + case GL_TEXTURE_CUBE_MAP_ARRAY: + case GL_TEXTURE_CUBE_MAP: + /* The PRM claims that we should use BRW_SURFACE_CUBE for this + * situation, but experiments show that gl_Layer doesn't work when we do + * this. So we use BRW_SURFACE_2D, since for rendering purposes this is + * equivalent. + */ + surftype = BRW_SURFACE_2D; + depth *= 6; + break; + default: + surftype = translate_tex_target(gl_target); + break; + } + + min_array_element = params->depth.layer; + if (params->depth.mt->num_samples > 1) { + /* Convert physical layer to logical layer. */ + min_array_element /= params->depth.mt->num_samples; + } - brw_get_depthstencil_tile_masks(params->depth.mt, - params->depth.level, - params->depth.layer, - NULL, - &tile_mask_x, &tile_mask_y); + lod = params->depth.level - params->depth.mt->first_level; - /* 3DSTATE_DEPTH_BUFFER */ - { - uint32_t tile_x = draw_x & tile_mask_x; - uint32_t tile_y = draw_y & tile_mask_y; - uint32_t offset = - intel_region_get_aligned_offset(params->depth.mt->region, - draw_x & ~tile_mask_x, - draw_y & ~tile_mask_y, false); - - /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 - * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth - * Coordinate Offset X/Y": - * - * "The 3 LSBs of both offsets must be zero to ensure correct - * alignment" - * - * We have no guarantee that tile_x and tile_y are correctly aligned, - * since they are determined by the mipmap layout, which is only aligned - * to multiples of 4. - * - * So, to avoid hanging the GPU, just smash the low order 3 bits of - * tile_x and tile_y to 0. This is a temporary workaround until we come - * up with a better solution. + if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) { + /* HIZ ops for lod 0 may set the width & height a little + * larger to allow the fast depth clear to fit the hardware + * alignment requirements. (8x4) */ - WARN_ONCE((tile_x & 7) || (tile_y & 7), - "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n" - "Truncating offset, bad rendering may occur.\n"); - tile_x &= ~7; - tile_y &= ~7; + surfwidth = params->depth.width; + surfheight = params->depth.height; + } else { + surfwidth = params->depth.mt->logical_width0; + surfheight = params->depth.mt->logical_height0; + } - intel_emit_depth_stall_flushes(brw); + /* 3DSTATE_DEPTH_BUFFER */ + { + brw_emit_depth_stall_flushes(brw); BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); - OUT_BATCH((params->depth.mt->region->pitch - 1) | + OUT_BATCH((params->depth.mt->pitch - 1) | params->depth_format << 18 | 1 << 22 | /* hiz enable */ 1 << 28 | /* depth write */ - BRW_SURFACE_2D << 29); - OUT_RELOC(params->depth.mt->region->bo, + surftype << 29); + OUT_RELOC(params->depth.mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - offset); - OUT_BATCH((params->depth.width + tile_x - 1) << 4 | - (params->depth.height + tile_y - 1) << 18); - OUT_BATCH(0); - OUT_BATCH(tile_x | - tile_y << 16); + 0); + OUT_BATCH((surfwidth - 1) << 4 | + (surfheight - 1) << 18 | + lod); + OUT_BATCH(((depth - 1) << 21) | + (min_array_element << 10) | + mocs); OUT_BATCH(0); + OUT_BATCH((depth - 1) << 21); ADVANCE_BATCH(); } /* 3DSTATE_HIER_DEPTH_BUFFER */ { - struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; - uint32_t hiz_offset = - intel_region_get_aligned_offset(hiz_region, - draw_x & ~tile_mask_x, - (draw_y & ~tile_mask_y) / 2, false); + struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf; BEGIN_BATCH(3); OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_region->pitch - 1); - OUT_RELOC(hiz_region->bo, + OUT_BATCH((mocs << 25) | + (hiz_buf->pitch - 1)); + OUT_RELOC(hiz_buf->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - hiz_offset); + 0); ADVANCE_BATCH(); } @@ -749,9 +730,10 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, static void -gen7_blorp_emit_depth_disable(struct brw_context *brw, - const brw_blorp_params *params) +gen7_blorp_emit_depth_disable(struct brw_context *brw) { + brw_emit_depth_stall_flushes(brw); + BEGIN_BATCH(7); OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29)); @@ -761,6 +743,18 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw, OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); } @@ -772,7 +766,7 @@ gen7_blorp_emit_depth_disable(struct brw_context *brw, * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER, * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER). */ -static void +void gen7_blorp_emit_clear_params(struct brw_context *brw, const brw_blorp_params *params) { @@ -785,7 +779,7 @@ gen7_blorp_emit_clear_params(struct brw_context *brw, /* 3DPRIMITIVE */ -static void +void gen7_blorp_emit_primitive(struct brw_context *brw, const brw_blorp_params *params) { @@ -795,7 +789,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw, _3DPRIM_RECTLIST); OUT_BATCH(3); /* vertex count per instance */ OUT_BATCH(0); - OUT_BATCH(1); /* instance count */ + OUT_BATCH(params->num_layers); /* instance count */ OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); @@ -809,76 +803,84 @@ void gen7_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) { + if (brw->gen >= 8) + return; + brw_blorp_prog_data *prog_data = NULL; uint32_t cc_blend_state_offset = 0; uint32_t cc_state_offset = 0; uint32_t depthstencil_offset; uint32_t wm_push_const_offset = 0; uint32_t wm_bind_bo_offset = 0; - uint32_t sampler_offset = 0; uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); - gen6_blorp_emit_batch_head(brw, params); - gen6_emit_3dstate_multisample(brw, params->num_samples); - gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false, ~0u); + gen6_emit_3dstate_multisample(brw, params->dst.num_samples); + gen6_emit_3dstate_sample_mask(brw, + params->dst.num_samples > 1 ? + (1 << params->dst.num_samples) - 1 : 1); gen6_blorp_emit_state_base_address(brw, params); gen6_blorp_emit_vertices(brw, params); - gen7_blorp_emit_urb_config(brw, params); + gen7_blorp_emit_urb_config(brw); if (params->use_wm_prog) { cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); - cc_state_offset = gen6_blorp_emit_cc_state(brw, params); - gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset); - gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset); + cc_state_offset = gen6_blorp_emit_cc_state(brw); + gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset); + gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset); } depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); - gen7_blorp_emit_depth_stencil_state_pointers(brw, params, - depthstencil_offset); + gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset); + if (brw->use_resource_streamer) + gen7_disable_hw_binding_tables(brw); if (params->use_wm_prog) { uint32_t wm_surf_offset_renderbuffer; uint32_t wm_surf_offset_texture = 0; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = - gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, + gen7_blorp_emit_surface_state(brw, ¶ms->dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, true /* is_render_target */); if (params->src.mt) { wm_surf_offset_texture = - gen7_blorp_emit_surface_state(brw, params, ¶ms->src, + gen7_blorp_emit_surface_state(brw, ¶ms->src, I915_GEM_DOMAIN_SAMPLER, 0, false /* is_render_target */); } wm_bind_bo_offset = - gen6_blorp_emit_binding_table(brw, params, + gen6_blorp_emit_binding_table(brw, wm_surf_offset_renderbuffer, wm_surf_offset_texture); - sampler_offset = gen7_blorp_emit_sampler_state(brw, params); } - gen7_blorp_emit_vs_disable(brw, params); - gen7_blorp_emit_hs_disable(brw, params); - gen7_blorp_emit_te_disable(brw, params); - gen7_blorp_emit_ds_disable(brw, params); - gen7_blorp_emit_gs_disable(brw, params); - gen7_blorp_emit_streamout_disable(brw, params); - gen6_blorp_emit_clip_disable(brw, params); + gen7_blorp_emit_vs_disable(brw); + gen7_blorp_emit_hs_disable(brw); + gen7_blorp_emit_te_disable(brw); + gen7_blorp_emit_ds_disable(brw); + gen7_blorp_emit_gs_disable(brw); + gen7_blorp_emit_streamout_disable(brw); + gen6_blorp_emit_clip_disable(brw); gen7_blorp_emit_sf_config(brw, params); gen7_blorp_emit_wm_config(brw, params, prog_data); if (params->use_wm_prog) { - gen7_blorp_emit_binding_table_pointers_ps(brw, params, - wm_bind_bo_offset); - gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset); - gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset); + gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset); + gen7_blorp_emit_constant_ps(brw, wm_push_const_offset); } else { - gen7_blorp_emit_constant_ps_disable(brw, params); + gen7_blorp_emit_constant_ps_disable(brw); } + + if (params->src.mt) { + const uint32_t sampler_offset = + gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true); + gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset); + } + gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data); - gen7_blorp_emit_cc_viewport(brw, params); + gen7_blorp_emit_cc_viewport(brw); if (params->depth.mt) gen7_blorp_emit_depth_stencil_config(brw, params); else - gen7_blorp_emit_depth_disable(brw, params); + gen7_blorp_emit_depth_disable(brw); gen7_blorp_emit_clear_params(brw, params); gen6_blorp_emit_drawing_rectangle(brw, params); gen7_blorp_emit_primitive(brw, params);