X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen7_misc_state.c;h=1a9e645084c5a8c924cc41980939c7d8ca26c0e2;hb=8c47ccb13a198f4d38c772df1de457de34dde23e;hp=1d3677d38dae9ab6572b0ea6fb985a7cc1f5e854;hpb=01bd29d681c68c8b5b23dfc8f92a3ff25c51a069;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 1d3677d38da..1a9e645084c 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -21,9 +21,9 @@ * IN THE SOFTWARE. */ +#include "main/mtypes.h" #include "intel_batchbuffer.h" #include "intel_mipmap_tree.h" -#include "intel_regions.h" #include "intel_fbo.h" #include "brw_context.h" #include "brw_state.h" @@ -35,54 +35,126 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t depth_offset, uint32_t depthbuffer_format, uint32_t depth_surface_type, struct intel_mipmap_tree *stencil_mt, - struct intel_mipmap_tree *hiz_mt, - bool separate_stencil, uint32_t width, - uint32_t height, uint32_t tile_x, uint32_t tile_y) + bool hiz, bool separate_stencil, + uint32_t width, uint32_t height, + uint32_t tile_x, uint32_t tile_y) { - struct intel_context *intel = &brw->intel; - struct gl_context *ctx = &intel->ctx; + struct gl_context *ctx = &brw->ctx; + const uint8_t mocs = GEN7_MOCS_L3; + struct gl_framebuffer *fb = ctx->DrawBuffer; + uint32_t surftype; + unsigned int depth = 1; + unsigned int min_array_element; + GLenum gl_target = GL_TEXTURE_2D; + unsigned int lod; + const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt; + const struct intel_renderbuffer *irb = NULL; + const struct gl_renderbuffer *rb = NULL; - intel_emit_depth_stall_flushes(intel); + /* Skip repeated NULL depth/stencil emits (think 2D rendering). */ + if (!mt && brw->no_depth_or_stencil) { + assert(brw->hw_ctx); + return; + } + + brw_emit_depth_stall_flushes(brw); + + irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); + if (!irb) + irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); + rb = (struct gl_renderbuffer*) irb; + + if (rb) { + depth = MAX2(irb->layer_count, 1); + if (rb->TexImage) + gl_target = rb->TexImage->TexObject->Target; + } + + switch (gl_target) { + case GL_TEXTURE_CUBE_MAP_ARRAY: + case GL_TEXTURE_CUBE_MAP: + /* The PRM claims that we should use BRW_SURFACE_CUBE for this + * situation, but experiments show that gl_Layer doesn't work when we do + * this. So we use BRW_SURFACE_2D, since for rendering purposes this is + * equivalent. + */ + surftype = BRW_SURFACE_2D; + depth *= 6; + break; + case GL_TEXTURE_3D: + assert(mt); + depth = mt->surf.logical_level0_px.depth; + /* fallthrough */ + default: + surftype = translate_tex_target(gl_target); + break; + } + + min_array_element = irb ? irb->mt_layer : 0; + + lod = irb ? irb->mt_level - irb->mt->first_level : 0; + + if (mt) { + width = mt->surf.logical_level0_px.width; + height = mt->surf.logical_level0_px.height; + } - /* _NEW_DEPTH, _NEW_STENCIL */ + /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */ BEGIN_BATCH(7); + /* 3DSTATE_DEPTH_BUFFER dw0 */ OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); - OUT_BATCH((depth_mt ? depth_mt->region->pitch - 1 : 0) | + + /* 3DSTATE_DEPTH_BUFFER dw1 */ + OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) | (depthbuffer_format << 18) | - ((hiz_mt ? 1 : 0) << 22) | - ((stencil_mt != NULL && ctx->Stencil._WriteEnabled) << 27) | - ((ctx->Depth.Mask != 0) << 28) | - (depth_surface_type << 29)); + ((hiz ? 1 : 0) << 22) | + ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) | + (brw_depth_writes_enabled(brw) << 28) | + (surftype << 29)); + /* 3DSTATE_DEPTH_BUFFER dw2 */ if (depth_mt) { - OUT_RELOC(depth_mt->region->bo, + OUT_RELOC(depth_mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - depth_offset); + 0); } else { OUT_BATCH(0); } - OUT_BATCH(((width + tile_x - 1) << 4) | - ((height + tile_y - 1) << 18)); - OUT_BATCH(0); - OUT_BATCH(tile_x | (tile_y << 16)); + /* 3DSTATE_DEPTH_BUFFER dw3 */ + OUT_BATCH(((width - 1) << 4) | + ((height - 1) << 18) | + lod); + + /* 3DSTATE_DEPTH_BUFFER dw4 */ + OUT_BATCH(((depth - 1) << 21) | + (min_array_element << 10) | + mocs); + + /* 3DSTATE_DEPTH_BUFFER dw5 */ OUT_BATCH(0); + + /* 3DSTATE_DEPTH_BUFFER dw6 */ + OUT_BATCH((depth - 1) << 21); ADVANCE_BATCH(); - if (hiz_mt == NULL) { + if (!hiz) { BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); } else { + assert(depth_mt); + BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); - OUT_BATCH(hiz_mt->region->pitch - 1); - OUT_RELOC(hiz_mt->region->bo, + OUT_BATCH((mocs << 25) | + (depth_mt->hiz_buf->pitch - 1)); + OUT_RELOC(depth_mt->hiz_buf->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - brw->depthstencil.hiz_offset); + 0); ADVANCE_BATCH(); } @@ -93,37 +165,32 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH(0); ADVANCE_BATCH(); } else { - const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0; + stencil_mt->r8stencil_needs_update = true; + const int enabled = brw->is_haswell ? HSW_STENCIL_ENABLED : 0; BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); - /* The stencil buffer has quirky pitch requirements. From the Graphics - * BSpec: vol2a.11 3D Pipeline Windower > Early Depth/Stencil Processing - * > Depth/Stencil Buffer State > 3DSTATE_STENCIL_BUFFER [DevIVB+], - * field "Surface Pitch": - * - * The pitch must be set to 2x the value computed based on width, as - * the stencil buffer is stored with two rows interleaved. - * - * (Note that it is not 100% clear whether this intended to apply to - * Gen7; the BSpec flags this comment as "DevILK,DevSNB" (which would - * imply that it doesn't), however the comment appears on a "DevIVB+" - * page (which would imply that it does). Experiments with the hardware - * indicate that it does. - */ OUT_BATCH(enabled | - (2 * stencil_mt->region->pitch - 1)); - OUT_RELOC(stencil_mt->region->bo, + mocs << 25 | + (stencil_mt->surf.row_pitch - 1)); + OUT_RELOC(stencil_mt->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - brw->depthstencil.stencil_offset); + 0); ADVANCE_BATCH(); } BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2)); - OUT_BATCH(depth_mt ? depth_mt->depth_clear_value : 0); + if (depth_mt) { + OUT_BATCH(brw_convert_depth_value(depth_mt->format, + depth_mt->fast_clear_color.f32[0])); + } else { + OUT_BATCH(0); + } OUT_BATCH(1); ADVANCE_BATCH(); + + brw->no_depth_or_stencil = !mt; } /** @@ -131,9 +198,11 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, */ const struct brw_tracked_state gen7_depthbuffer = { .dirty = { - .mesa = (_NEW_BUFFERS | _NEW_DEPTH | _NEW_STENCIL), - .brw = BRW_NEW_BATCH, - .cache = 0, + .mesa = _NEW_BUFFERS | + _NEW_DEPTH | + _NEW_STENCIL, + .brw = BRW_NEW_BATCH | + BRW_NEW_BLORP, }, .emit = brw_emit_depthbuffer, };