X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen7_vs_state.c;h=2715b37118adc1ec50430c6671b7b93724cebe8f;hb=ac08bc8ac220f22333536a9f881fde1e5607148e;hp=462db5bf1944a84287b07e1d92636237253167d6;hpb=6ba9090ea05e817bd38c1fcc63c53168b16593c7;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 462db5bf194..2715b37118a 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -32,64 +32,41 @@ static void upload_vs_state(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; + const struct brw_stage_state *stage_state = &brw->vs.base; uint32_t floating_point_mode = 0; + const int max_threads_shift = brw->is_haswell ? + HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; + const struct brw_vue_prog_data *prog_data = &brw->vs.prog_data->base; - BEGIN_BATCH(2); - OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2)); - OUT_BATCH(brw->vs.bind_bo_offset); - ADVANCE_BATCH(); - - if (brw->vs.push_const_size == 0) { - /* Disable the push constant buffers. */ - BEGIN_BATCH(7); - OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } else { - BEGIN_BATCH(7); - OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); - OUT_BATCH(brw->vs.push_const_size); - OUT_BATCH(0); - /* Pointer to the VS constant buffer. Covered by the set of - * state flags from gen6_prepare_wm_contants - */ - OUT_BATCH(brw->vs.push_const_offset); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } + if (!brw->is_haswell && !brw->is_baytrail) + gen7_emit_vs_workaround_flush(brw); - /* Use ALT floating point mode for ARB vertex programs, because they - * require 0^0 == 1. - */ - if (intel->ctx.Shader.CurrentVertexProgram == NULL) + if (brw->vs.prog_data->base.base.use_alt_mode) floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT; BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); - OUT_BATCH(brw->vs.prog_offset); - OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | floating_point_mode); + OUT_BATCH(stage_state->prog_offset); + OUT_BATCH(floating_point_mode | + ((ALIGN(stage_state->sampler_count, 4)/4) << + GEN6_VS_SAMPLER_COUNT_SHIFT) | + ((brw->vs.prog_data->base.base.binding_table.size_bytes / 4) << + GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); - if (brw->vs.prog_data->total_scratch) { - OUT_RELOC(brw->vs.scratch_bo, + if (prog_data->base.total_scratch) { + OUT_RELOC(stage_state->scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - ffs(brw->vs.prog_data->total_scratch) - 11); + ffs(stage_state->per_thread_scratch) - 11); } else { OUT_BATCH(0); } - OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) | - (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | + OUT_BATCH((prog_data->base.dispatch_grf_start_reg << + GEN6_VS_DISPATCH_START_GRF_SHIFT) | + (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH(((brw->max_vs_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) | + OUT_BATCH(((brw->max_vs_threads - 1) << max_threads_shift) | GEN6_VS_STATISTICS_ENABLE | GEN6_VS_ENABLE); ADVANCE_BATCH(); @@ -97,14 +74,11 @@ upload_vs_state(struct brw_context *brw) const struct brw_tracked_state gen7_vs_state = { .dirty = { - .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS, - .brw = (BRW_NEW_CURBE_OFFSETS | - BRW_NEW_URB_FENCE | - BRW_NEW_CONTEXT | - BRW_NEW_VERTEX_PROGRAM | - BRW_NEW_VS_BINDING_TABLE | - BRW_NEW_BATCH), - .cache = CACHE_NEW_VS_PROG + .mesa = _NEW_TRANSFORM, + .brw = BRW_NEW_BATCH | + BRW_NEW_BLORP | + BRW_NEW_CONTEXT | + BRW_NEW_VS_PROG_DATA, }, .emit = upload_vs_state, };