X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen7_wm_surface_state.c;h=e1690a7982778050c6422ba113c38dd26ef7a07a;hb=794de2f3873bcedc78300b3ba69656adc755894c;hp=50a3385dcb3f36207b1771c97746187268d2283f;hpb=fd99cd0e10849205749aad580fea8c970fb46a31;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 50a3385dcb3..e1690a79827 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -21,205 +21,495 @@ * IN THE SOFTWARE. */ #include "main/mtypes.h" +#include "main/blend.h" #include "main/samplerobj.h" -#include "main/texstore.h" +#include "main/texformat.h" #include "program/prog_parameter.h" #include "intel_mipmap_tree.h" #include "intel_batchbuffer.h" #include "intel_tex.h" #include "intel_fbo.h" +#include "intel_buffer_objects.h" #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" #include "brw_wm.h" -static void -gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling) +/** + * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+ + * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED) + */ +static unsigned +swizzle_to_scs(GLenum swizzle) +{ + switch (swizzle) { + case SWIZZLE_X: + return HSW_SCS_RED; + case SWIZZLE_Y: + return HSW_SCS_GREEN; + case SWIZZLE_Z: + return HSW_SCS_BLUE; + case SWIZZLE_W: + return HSW_SCS_ALPHA; + case SWIZZLE_ZERO: + return HSW_SCS_ZERO; + case SWIZZLE_ONE: + return HSW_SCS_ONE; + } + + assert(!"Should not get here: invalid swizzle mode"); + return HSW_SCS_ZERO; +} + +uint32_t +gen7_surface_tiling_mode(uint32_t tiling) { switch (tiling) { - case I915_TILING_NONE: - surf->ss0.tiled_surface = 0; - surf->ss0.tile_walk = 0; - break; case I915_TILING_X: - surf->ss0.tiled_surface = 1; - surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR; - break; + return GEN7_SURFACE_TILING_X; case I915_TILING_Y: - surf->ss0.tiled_surface = 1; - surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR; - break; + return GEN7_SURFACE_TILING_Y; + default: + return GEN7_SURFACE_TILING_NONE; + } +} + + +uint32_t +gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout) +{ + uint32_t ss4 = 0; + + if (num_samples > 4) + ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8; + else if (num_samples > 1) + ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4; + else + ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1; + + if (layout == INTEL_MSAA_LAYOUT_IMS) + ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL; + else + ss4 |= GEN7_SURFACE_MSFMT_MSS; + + return ss4; +} + + +void +gen7_set_surface_mcs_info(struct brw_context *brw, + uint32_t *surf, + uint32_t surf_offset, + const struct intel_mipmap_tree *mcs_mt, + bool is_render_target) +{ + /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address": + * + * "The MCS surface must be stored as Tile Y." + */ + assert(mcs_mt->region->tiling == I915_TILING_Y); + + /* Compute the pitch in units of tiles. To do this we need to divide the + * pitch in bytes by 128, since a single Y-tile is 128 bytes wide. + */ + unsigned pitch_tiles = mcs_mt->region->pitch / 128; + + /* The upper 20 bits of surface state DWORD 6 are the upper 20 bits of the + * GPU address of the MCS buffer; the lower 12 bits contain other control + * information. Since buffer addresses are always on 4k boundaries (and + * thus have their lower 12 bits zero), we can use an ordinary reloc to do + * the necessary address translation. + */ + assert ((mcs_mt->region->bo->offset & 0xfff) == 0); + + surf[6] = GEN7_SURFACE_MCS_ENABLE | + SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) | + mcs_mt->region->bo->offset; + + drm_intel_bo_emit_reloc(brw->batch.bo, + surf_offset + 6 * 4, + mcs_mt->region->bo, + surf[6] & 0xfff, + is_render_target ? I915_GEM_DOMAIN_RENDER + : I915_GEM_DOMAIN_SAMPLER, + is_render_target ? I915_GEM_DOMAIN_RENDER : 0); +} + + +void +gen7_check_surface_setup(uint32_t *surf, bool is_render_target) +{ + unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3); + unsigned multisampled_surface_storage_format = surf[4] & (1 << 6); + unsigned surface_array_spacing = surf[0] & (1 << 10); + bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1; + + (void) surface_array_spacing; + + /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > + * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array + * Spacing: + * + * If Multisampled Surface Storage Format is MSFMT_MSS and Number of + * Multisamples is not MULTISAMPLECOUNT_1, this field must be set to + * ARYSPC_LOD0. + */ + if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS + && is_multisampled) + assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0); + + /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > + * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled + * Surface Storage Format: + * + * All multisampled render target surfaces must have this field set to + * MSFMT_MSS. + * + * But also: + * + * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1. + */ + if (is_render_target && is_multisampled) { + assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS); + } + + /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > + * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled + * Surface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width + * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this + * field must be set to MSFMT_MSS. + */ + uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1; + if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) { + assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS); + } + + /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State > + * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled + * Surface Storage Format: + * + * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, + * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number of + * Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is > + * 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.This field + * must be set to MSFMT_DEPTH_STENCIL if Surface Format is one of the + * following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or + * R24_UNORM_X8_TYPELESS. + * + * But also: + * + * This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1. + */ + uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1; + uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1; + if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && + depth * height > 4194304) { + assert(multisampled_surface_storage_format == + GEN7_SURFACE_MSFMT_DEPTH_STENCIL); + } + if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 && + depth * height > 8388608) { + assert(multisampled_surface_storage_format == + GEN7_SURFACE_MSFMT_DEPTH_STENCIL); + } + if (is_multisampled) { + switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) { + case BRW_SURFACEFORMAT_I24X8_UNORM: + case BRW_SURFACEFORMAT_L24X8_UNORM: + case BRW_SURFACEFORMAT_A24X8_UNORM: + case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS: + assert(multisampled_surface_storage_format == + GEN7_SURFACE_MSFMT_DEPTH_STENCIL); + } } } + static void -gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) +gen7_update_buffer_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) { struct brw_context *brw = brw_context(ctx); + struct intel_context *intel = &brw->intel; + struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; + struct intel_buffer_object *intel_obj = + intel_buffer_object(tObj->BufferObject); + drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL; + gl_format format = tObj->_BufferObjectFormat; + + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, &binding_table[surf_index]); + memset(surf, 0, 8 * 4); + + uint32_t surface_format = brw_format_for_mesa_format(format); + if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) { + _mesa_problem(NULL, "bad format %s for texture buffer\n", + _mesa_get_format_name(format)); + } + + surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | + surface_format << BRW_SURFACE_FORMAT_SHIFT | + BRW_SURFACE_RC_READ_WRITE; + + if (bo) { + surf[1] = bo->offset; /* reloc */ + + /* Emit relocation to surface contents. Section 5.1.1 of the gen4 + * bspec ("Data Cache") says that the data cache does not exist as + * a separate cache and is just the sampler cache. + */ + drm_intel_bo_emit_reloc(brw->batch.bo, + binding_table[surf_index] + 4, + bo, 0, + I915_GEM_DOMAIN_SAMPLER, 0); + + int texel_size = _mesa_get_format_bytes(format); + int w = intel_obj->Base.Size / texel_size; + + /* note that these differ from GEN6 */ + surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */ + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); /* 20:7 */ + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | /* bits 26:21 */ + (texel_size - 1); + } + + gen7_check_surface_setup(surf, false /* is_render_target */); +} + +static void +gen7_update_texture_surface(struct gl_context *ctx, + unsigned unit, + uint32_t *binding_table, + unsigned surf_index) +{ + struct brw_context *brw = brw_context(ctx); + struct intel_context *intel = &brw->intel; struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); + struct intel_mipmap_tree *mt = intelObj->mt; struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); - const GLuint surf_index = SURF_INDEX_TEXTURE(unit); - struct gen7_surface_state *surf; - int width, height, depth; - - intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth); - - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, &brw->wm.surf_offset[surf_index]); - memset(surf, 0, sizeof(*surf)); - - surf->ss0.surface_type = translate_tex_target(tObj->Target); - surf->ss0.surface_format = translate_tex_format(firstImage->TexFormat, - firstImage->InternalFormat, - sampler->DepthMode, - sampler->sRGBDecode); - if (tObj->Target == GL_TEXTURE_CUBE_MAP) { - surf->ss0.cube_pos_x = 1; - surf->ss0.cube_pos_y = 1; - surf->ss0.cube_pos_z = 1; - surf->ss0.cube_neg_x = 1; - surf->ss0.cube_neg_y = 1; - surf->ss0.cube_neg_z = 1; + uint32_t tile_x, tile_y; + + if (tObj->Target == GL_TEXTURE_BUFFER) { + gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); + return; } - gen7_set_surface_tiling(surf, intelObj->mt->region->tiling); + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, &binding_table[surf_index]); + memset(surf, 0, 8 * 4); - /* ss0 remaining fields: - * - is_array - * - vertical_alignment - * - horizontal_alignment - * - vert_line_stride (exists on gen6 but we ignore it) - * - vert_line_stride_ofs (exists on gen6 but we ignore it) - * - surface_array_spacing - * - render_cache_read_write (exists on gen6 but ignored here) - */ + uint32_t tex_format = translate_tex_format(brw, + mt->format, + tObj->DepthMode, + sampler->sRGBDecode); + + surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT | + tex_format << BRW_SURFACE_FORMAT_SHIFT | + gen7_surface_tiling_mode(mt->region->tiling) | + BRW_SURFACE_CUBEFACE_ENABLES; + + if (mt->align_h == 4) + surf[0] |= GEN7_SURFACE_VALIGN_4; + if (mt->align_w == 8) + surf[0] |= GEN7_SURFACE_HALIGN_8; - surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */ + if (mt->logical_depth0 > 1 && tObj->Target != GL_TEXTURE_3D) + surf[0] |= GEN7_SURFACE_IS_ARRAY; - surf->ss2.width = width - 1; - surf->ss2.height = height - 1; + if (mt->array_spacing_lod0) + surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; - surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1; - surf->ss3.depth = depth - 1; + surf[1] = mt->region->bo->offset + mt->offset; /* reloc */ + surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, + &tile_x, &tile_y); - /* ss4: ignored? */ + surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | + SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); + surf[3] = SET_FIELD(mt->logical_depth0 - 1, BRW_SURFACE_DEPTH) | + ((intelObj->mt->region->pitch) - 1); - surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel; - surf->ss5.min_lod = 0; + surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout); - /* ss5 remaining fields: - * - x_offset (N/A for textures?) - * - y_offset (ditto) - * - cache_control + assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. */ + surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | + (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | + /* mip count */ + (intelObj->_MaxLevel - tObj->BaseLevel)); + + if (brw->is_haswell) { + /* Handling GL_ALPHA as a surface format override breaks 1.30+ style + * texturing functions that return a float, as our code generation always + * selects the .x channel (which would always be 0). + */ + const bool alpha_depth = tObj->DepthMode == GL_ALPHA && + (firstImage->_BaseFormat == GL_DEPTH_COMPONENT || + firstImage->_BaseFormat == GL_DEPTH_STENCIL); + + const int swizzle = unlikely(alpha_depth) + ? SWIZZLE_XYZW : brw_get_texture_swizzle(ctx, tObj); + + surf[7] = + SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) | + SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) | + SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) | + SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A); + } /* Emit relocation to surface contents */ - drm_intel_bo_emit_reloc(brw->intel.batch.bo, - brw->wm.surf_offset[surf_index] + - offsetof(struct gen7_surface_state, ss1), - intelObj->mt->region->bo, 0, + drm_intel_bo_emit_reloc(brw->batch.bo, + binding_table[surf_index] + 4, + intelObj->mt->region->bo, + surf[1] - intelObj->mt->region->bo->offset, I915_GEM_DOMAIN_SAMPLER, 0); + + gen7_check_surface_setup(surf, false /* is_render_target */); } /** * Create the constant buffer surface. Vertex/fragment shader constants will * be read from this buffer with Data Port Read instructions/messages. */ -void +static void gen7_create_constant_surface(struct brw_context *brw, drm_intel_bo *bo, - int width, - uint32_t *out_offset) + uint32_t offset, + uint32_t size, + uint32_t *out_offset, + bool dword_pitch) { - const GLint w = width - 1; - struct gen7_surface_state *surf; - - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, out_offset); - memset(surf, 0, sizeof(*surf)); + struct intel_context *intel = &brw->intel; + uint32_t stride = dword_pitch ? 4 : 16; + uint32_t elements = ALIGN(size, stride) / stride; + const GLint w = elements - 1; - surf->ss0.surface_type = BRW_SURFACE_BUFFER; - surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, out_offset); + memset(surf, 0, 8 * 4); - surf->ss0.render_cache_read_write = 1; + surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | + BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT | + BRW_SURFACE_RC_READ_WRITE; assert(bo); - surf->ss1.base_addr = bo->offset; /* reloc */ - - surf->ss2.width = w & 0x7f; /* bits 6:0 of size or width */ - surf->ss2.height = (w >> 7) & 0x1fff; /* bits 19:7 of size or width */ - surf->ss3.depth = (w >> 20) & 0x7f; /* bits 26:20 of size or width */ - surf->ss3.pitch = (width * 16) - 1; /* ignored?? */ - gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */ + surf[1] = bo->offset + offset; /* reloc */ + + /* note that these differ from GEN6 */ + surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH) | + (stride - 1); + + if (brw->is_haswell) { + surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + } /* Emit relocation to surface contents. Section 5.1.1 of the gen4 * bspec ("Data Cache") says that the data cache does not exist as * a separate cache and is just the sampler cache. */ - drm_intel_bo_emit_reloc(brw->intel.batch.bo, - (*out_offset + - offsetof(struct gen7_surface_state, ss1)), - bo, 0, + drm_intel_bo_emit_reloc(brw->batch.bo, + *out_offset + 4, + bo, offset, I915_GEM_DOMAIN_SAMPLER, 0); + + gen7_check_surface_setup(surf, false /* is_render_target */); } /** - * Updates surface / buffer for fragment shader constant buffer, if - * one is required. - * - * This consumes the state updates for the constant buffer, and produces - * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for - * inclusion in the binding table. + * Create a surface for shader time. */ -static void upload_wm_constant_surface(struct brw_context *brw) +void +gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset) { - GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER; - struct brw_fragment_program *fp = - (struct brw_fragment_program *) brw->fragment_program; - const struct gl_program_parameter_list *params = - fp->program.Base.Parameters; - - /* If there's no constant buffer, then no surface BO is needed to point at - * it. + struct intel_context *intel = &brw->intel; + const int w = brw->shader_time.bo->size - 1; + + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, out_offset); + memset(surf, 0, 8 * 4); + + surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | + BRW_SURFACEFORMAT_RAW << BRW_SURFACE_FORMAT_SHIFT | + BRW_SURFACE_RC_READ_WRITE; + + surf[1] = brw->shader_time.bo->offset; /* reloc */ + + /* note that these differ from GEN6 */ + surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | + SET_FIELD((w >> 7) & 0x3fff, GEN7_SURFACE_HEIGHT); + surf[3] = SET_FIELD((w >> 21) & 0x3f, BRW_SURFACE_DEPTH); + + /* Unlike texture or renderbuffer surfaces, we only do untyped operations + * on the shader_time surface, so there's no need to set HSW channel + * overrides. */ - if (brw->wm.const_bo == 0) { - if (brw->wm.surf_offset[surf]) { - brw->state.dirty.brw |= BRW_NEW_WM_SURFACES; - brw->wm.surf_offset[surf] = 0; - } - return; - } - gen7_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters, - &brw->wm.surf_offset[surf]); - brw->state.dirty.brw |= BRW_NEW_WM_SURFACES; -} + /* Emit relocation to surface contents. Section 5.1.1 of the gen4 + * bspec ("Data Cache") says that the data cache does not exist as + * a separate cache and is just the sampler cache. + */ + drm_intel_bo_emit_reloc(brw->batch.bo, + *out_offset + 4, + brw->shader_time.bo, 0, + I915_GEM_DOMAIN_SAMPLER, 0); -const struct brw_tracked_state gen7_wm_constant_surface = { - .dirty = { - .mesa = 0, - .brw = (BRW_NEW_WM_CONSTBUF | - BRW_NEW_BATCH), - .cache = 0 - }, - .emit = upload_wm_constant_surface, -}; + gen7_check_surface_setup(surf, false /* is_render_target */); +} static void gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) { - struct gen7_surface_state *surf; + /* From the Ivy bridge PRM, Vol4 Part1 p62 (Surface Type: Programming + * Notes): + * + * A null surface is used in instances where an actual surface is not + * bound. When a write message is generated to a null surface, no + * actual surface is written to. When a read message (including any + * sampling engine message) is generated to a null surface, the result + * is all zeros. Note that a null surface type is allowed to be used + * with all messages, even if it is not specificially indicated as + * supported. All of the remaining fields in surface state are ignored + * for null surfaces, with the following exceptions: Width, Height, + * Depth, LOD, and Render Target View Extent fields must match the + * depth buffer’s corresponding state for all render target surfaces, + * including null. + */ + struct intel_context *intel = &brw->intel; + struct gl_context *ctx = &intel->ctx; + + /* _NEW_BUFFERS */ + const struct gl_framebuffer *fb = ctx->DrawBuffer; + + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, &brw->wm.surf_offset[unit]); + memset(surf, 0, 8 * 4); - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, &brw->wm.surf_offset[unit]); - memset(surf, 0, sizeof(*surf)); + /* From the Ivybridge PRM, Volume 4, Part 1, page 65, + * Tiled Surface: Programming Notes: + * "If Surface Type is SURFTYPE_NULL, this field must be TRUE." + */ + surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT | + BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT | + GEN7_SURFACE_TILING_Y; + + surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) | + SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT); - surf->ss0.surface_type = BRW_SURFACE_NULL; - surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + gen7_check_surface_setup(surf, true /* is_render_target */); } /** @@ -230,172 +520,121 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) static void gen7_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, + bool layered, unsigned int unit) { struct intel_context *intel = &brw->intel; struct gl_context *ctx = &intel->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); - struct intel_region *region = irb->region; - struct gen7_surface_state *surf; - uint32_t tile_x, tile_y; + struct intel_region *region = irb->mt->region; + uint32_t format; + /* _NEW_BUFFERS */ + gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); + uint32_t surftype; + bool is_array = false; + int depth = MAX2(rb->Depth, 1); + int min_array_element; + GLenum gl_target = rb->TexImage ? + rb->TexImage->TexObject->Target : GL_TEXTURE_2D; + + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, + 8 * 4, 32, &brw->wm.surf_offset[unit]); + memset(surf, 0, 8 * 4); + + intel_miptree_used_for_rendering(irb->mt); + + /* Render targets can't use IMS layout */ + assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); + + assert(brw_render_target_supported(brw, rb)); + format = brw->render_target_format[rb_format]; + if (unlikely(!brw->format_supported_as_render_target[rb_format])) { + _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", + __FUNCTION__, _mesa_get_format_name(rb_format)); + } - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, - sizeof(*surf), 32, &brw->wm.surf_offset[unit]); - memset(surf, 0, sizeof(*surf)); - - switch (irb->Base.Format) { - case MESA_FORMAT_XRGB8888: - /* XRGB is handled as ARGB because the chips in this family - * cannot render to XRGB targets. This means that we have to - * mask writes to alpha (ala glColorMask) and reconfigure the - * alpha blending hardware to use GL_ONE (or GL_ZERO) for - * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is - * used. - */ - surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; - break; - case MESA_FORMAT_INTENSITY_FLOAT32: - case MESA_FORMAT_LUMINANCE_FLOAT32: - /* For these formats, we just need to read/write the first - * channel into R, which is to say that we just treat them as - * GL_RED. - */ - surf->ss0.surface_format = BRW_SURFACEFORMAT_R32_FLOAT; - break; - case MESA_FORMAT_SARGB8: - /* without GL_EXT_framebuffer_sRGB we shouldn't bind sRGB - surfaces to the blend/update as sRGB */ - if (ctx->Color.sRGBEnabled) - surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format); - else - surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + switch (gl_target) { + case GL_TEXTURE_CUBE_MAP_ARRAY: + case GL_TEXTURE_CUBE_MAP: + surftype = BRW_SURFACE_2D; + is_array = true; + depth *= 6; break; default: - assert(brw_render_target_supported(irb->Base.Format)); - surf->ss0.surface_format = brw_format_for_mesa_format(irb->Base.Format); + surftype = translate_tex_target(gl_target); + is_array = _mesa_tex_target_is_array(gl_target); + break; } - surf->ss0.surface_type = BRW_SURFACE_2D; - /* reloc */ - surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); - surf->ss1.base_addr += region->bo->offset; /* reloc */ + if (layered) { + min_array_element = 0; + } else if (irb->mt->num_samples > 1) { + min_array_element = irb->mt_layer / irb->mt->num_samples; + } else { + min_array_element = irb->mt_layer; + } - assert(brw->has_surface_tile_offset); - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - assert(tile_x % 4 == 0); - assert(tile_y % 2 == 0); - surf->ss5.x_offset = tile_x / 4; - surf->ss5.y_offset = tile_y / 2; - - surf->ss2.width = rb->Width - 1; - surf->ss2.height = rb->Height - 1; - gen7_set_surface_tiling(surf, region->tiling); - surf->ss3.pitch = (region->pitch * region->cpp) - 1; - - drm_intel_bo_emit_reloc(brw->intel.batch.bo, - brw->wm.surf_offset[unit] + - offsetof(struct gen7_surface_state, ss1), - region->bo, - surf->ss1.base_addr - region->bo->offset, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); -} + surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT | + format << BRW_SURFACE_FORMAT_SHIFT | + (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0 + : GEN7_SURFACE_ARYSPC_FULL) | + gen7_surface_tiling_mode(region->tiling); -static void -prepare_wm_surfaces(struct brw_context *brw) -{ - struct gl_context *ctx = &brw->intel.ctx; - int i; - int nr_surfaces = 0; - - if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; - struct intel_renderbuffer *irb = intel_renderbuffer(rb); - struct intel_region *region = irb ? irb->region : NULL; - - if (region) - brw_add_validated_bo(brw, region->bo); - nr_surfaces = SURF_INDEX_DRAW(i) + 1; - } - } + if (irb->mt->align_h == 4) + surf[0] |= GEN7_SURFACE_VALIGN_4; + if (irb->mt->align_w == 8) + surf[0] |= GEN7_SURFACE_HALIGN_8; - if (brw->wm.const_bo) { - brw_add_validated_bo(brw, brw->wm.const_bo); - nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1; + if (is_array) { + surf[0] |= GEN7_SURFACE_IS_ARRAY; } - for (i = 0; i < BRW_MAX_TEX_UNIT; i++) { - const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; - struct gl_texture_object *tObj = texUnit->_Current; - struct intel_texture_object *intelObj = intel_texture_object(tObj); + surf[1] = region->bo->offset; - if (texUnit->_ReallyEnabled) { - brw_add_validated_bo(brw, intelObj->mt->region->bo); - nr_surfaces = SURF_INDEX_TEXTURE(i) + 1; - } - } + assert(brw->has_surface_tile_offset); - /* Have to update this in our prepare, since the unit's prepare - * relies on it. - */ - if (brw->wm.nr_surfaces != nr_surfaces) { - brw->wm.nr_surfaces = nr_surfaces; - brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES; - } -} + surf[5] = irb->mt_level - irb->mt->first_level; -/** - * Constructs the set of surface state objects pointed to by the - * binding table. - */ -static void -upload_wm_surfaces(struct brw_context *brw) -{ - struct gl_context *ctx = &brw->intel.ctx; - GLuint i; - - /* _NEW_BUFFERS | _NEW_COLOR */ - /* Update surfaces for drawing buffers */ - if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { - for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { - if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { - gen7_update_renderbuffer_surface(brw, - ctx->DrawBuffer->_ColorDrawBuffers[i], i); - } else { - gen7_update_null_renderbuffer_surface(brw, i); - } - } - } else { - gen7_update_null_renderbuffer_surface(brw, 0); + surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) | + SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT); + + surf[3] = ((depth - 1) << BRW_SURFACE_DEPTH_SHIFT) | + (region->pitch - 1); + + surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout) | + min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT | + (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; + + if (irb->mt->mcs_mt) { + gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit], + irb->mt->mcs_mt, true /* is RT */); } - /* Update surfaces for textures */ - for (i = 0; i < BRW_MAX_TEX_UNIT; i++) { - const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i]; - const GLuint surf = SURF_INDEX_TEXTURE(i); + surf[7] = irb->mt->fast_clear_color_value; - /* _NEW_TEXTURE */ - if (texUnit->_ReallyEnabled) { - gen7_update_texture_surface(ctx, i); - } else { - brw->wm.surf_offset[surf] = 0; - } + if (brw->is_haswell) { + surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A)); } - brw->state.dirty.brw |= BRW_NEW_WM_SURFACES; + drm_intel_bo_emit_reloc(brw->batch.bo, + brw->wm.surf_offset[unit] + 4, + region->bo, + surf[1] - region->bo->offset, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + + gen7_check_surface_setup(surf, true /* is_render_target */); } -const struct brw_tracked_state gen7_wm_surfaces = { - .dirty = { - .mesa = (_NEW_COLOR | - _NEW_TEXTURE | - _NEW_BUFFERS), - .brw = BRW_NEW_BATCH, - .cache = 0 - }, - .prepare = prepare_wm_surfaces, - .emit = upload_wm_surfaces, -}; +void +gen7_init_vtable_surface_functions(struct brw_context *brw) +{ + brw->vtbl.update_texture_surface = gen7_update_texture_surface; + brw->vtbl.update_renderbuffer_surface = gen7_update_renderbuffer_surface; + brw->vtbl.update_null_renderbuffer_surface = + gen7_update_null_renderbuffer_surface; + brw->vtbl.create_constant_surface = gen7_create_constant_surface; +}