X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fgen8_surface_state.c;h=a3ad108ac2e2bfe56abc7a6b1c83e1ada947d900;hb=44997fc0c1cc7f24216e3b1c5d954919df946ee5;hp=d2f333fd4dd9a38d2087bb7cbb58c755e33663a4;hpb=d2e3638ef9e2ddf7e02b9fbe3fa8d40c63ebe5da;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index d2f333fd4dd..a3ad108ac2e 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -27,12 +27,14 @@ #include "main/texformat.h" #include "main/teximage.h" #include "program/prog_parameter.h" +#include "program/prog_instruction.h" #include "intel_mipmap_tree.h" #include "intel_batchbuffer.h" #include "intel_tex.h" #include "intel_fbo.h" #include "intel_buffer_objects.h" +#include "intel_image.h" #include "brw_context.h" #include "brw_state.h" @@ -69,8 +71,8 @@ surface_tiling_resource_mode(uint32_t tr_mode) } } -static uint32_t -surface_tiling_mode(uint32_t tiling) +uint32_t +gen8_surface_tiling_mode(uint32_t tiling) { switch (tiling) { case I915_TILING_X: @@ -82,10 +84,10 @@ surface_tiling_mode(uint32_t tiling) } } -static unsigned -vertical_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type) +unsigned +gen8_vertical_alignment(const struct brw_context *brw, + const struct intel_mipmap_tree *mt, + uint32_t surf_type) { /* On Gen9+ vertical alignment is ignored for 1D surfaces and when * tr_mode is not TRMODE_NONE. Set to an arbitrary non-reserved value. @@ -95,7 +97,7 @@ vertical_alignment(const struct brw_context *brw, surf_type == BRW_SURFACE_1D)) return GEN8_SURFACE_VALIGN_4; - switch (mt->align_h) { + switch (mt->valign) { case 4: return GEN8_SURFACE_VALIGN_4; case 8: @@ -107,10 +109,10 @@ vertical_alignment(const struct brw_context *brw, } } -static unsigned -horizontal_alignment(const struct brw_context *brw, - const struct intel_mipmap_tree *mt, - uint32_t surf_type) +unsigned +gen8_horizontal_alignment(const struct brw_context *brw, + const struct intel_mipmap_tree *mt, + uint32_t surf_type) { /* On Gen9+ horizontal alignment is ignored when tr_mode is not * TRMODE_NONE. Set to an arbitrary non-reserved value. @@ -120,7 +122,7 @@ horizontal_alignment(const struct brw_context *brw, gen9_use_linear_1d_layout(brw, mt))) return GEN8_SURFACE_HALIGN_4; - switch (mt->align_w) { + switch (mt->halign) { case 4: return GEN8_SURFACE_HALIGN_4; case 8: @@ -132,8 +134,9 @@ horizontal_alignment(const struct brw_context *brw, } } -static uint32_t * -allocate_surface_state(struct brw_context *brw, uint32_t *out_offset, int index) +uint32_t * +gen8_allocate_surface_state(struct brw_context *brw, + uint32_t *out_offset, int index) { int dwords = brw->gen >= 9 ? 16 : 13; uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, @@ -153,7 +156,7 @@ gen8_emit_buffer_surface_state(struct brw_context *brw, bool rw) { const unsigned mocs = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; - uint32_t *surf = allocate_surface_state(brw, out_offset, -1); + uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1); surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT | surface_format << BRW_SURFACE_FORMAT_SHIFT | @@ -182,6 +185,44 @@ gen8_emit_buffer_surface_state(struct brw_context *brw, } } +void +gen8_emit_fast_clear_color(const struct brw_context *brw, + const struct intel_mipmap_tree *mt, + uint32_t *surf) +{ + if (brw->gen >= 9) { + surf[12] = mt->gen9_fast_clear_color.ui[0]; + surf[13] = mt->gen9_fast_clear_color.ui[1]; + surf[14] = mt->gen9_fast_clear_color.ui[2]; + surf[15] = mt->gen9_fast_clear_color.ui[3]; + } else + surf[7] |= mt->fast_clear_color_value; +} + +uint32_t +gen8_get_aux_mode(const struct brw_context *brw, + const struct intel_mipmap_tree *mt) +{ + if (mt->mcs_mt == NULL) + return GEN8_SURFACE_AUX_MODE_NONE; + + /* + * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE): + * "When MCS is enabled for non-MSRT, HALIGN_16 must be used" + * + * From the hardware spec for GEN9: + * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN + * 16 must be used." + */ + if (brw->gen >= 9 || mt->num_samples == 1) + assert(mt->halign == 16); + + if (intel_miptree_is_lossless_compressed(brw, mt)) + return GEN9_SURFACE_AUX_MODE_CCS_E; + + return GEN8_SURFACE_AUX_MODE_MCS; +} + static void gen8_emit_texture_surface_state(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -190,48 +231,41 @@ gen8_emit_texture_surface_state(struct brw_context *brw, unsigned min_level, unsigned max_level, unsigned format, unsigned swizzle, - uint32_t *surf_offset, + uint32_t *surf_offset, int surf_index, bool rw, bool for_gather) { const unsigned depth = max_layer - min_layer; - struct intel_mipmap_tree *aux_mt = NULL; - uint32_t aux_mode = 0; + struct intel_mipmap_tree *aux_mt = mt->mcs_mt; uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; - int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; unsigned tiling_mode, pitch; const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode); + const uint32_t surf_type = translate_tex_target(target); + uint32_t aux_mode = gen8_get_aux_mode(brw, mt); if (mt->format == MESA_FORMAT_S_UINT8) { tiling_mode = GEN8_SURFACE_TILING_W; pitch = 2 * mt->pitch; } else { - tiling_mode = surface_tiling_mode(mt->tiling); + tiling_mode = gen8_surface_tiling_mode(mt->tiling); pitch = mt->pitch; } - if (mt->mcs_mt) { - aux_mt = mt->mcs_mt; - aux_mode = GEN8_SURFACE_AUX_MODE_MCS; - - /* - * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE): - * "When MCS is enabled for non-MSRT, HALIGN_16 must be used" - * - * From the hardware spec for GEN9: - * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN - * 16 must be used." - */ - assert(brw->gen < 9 || mt->align_w == 16); - assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16); + /* Prior to Gen9, MCS is not uploaded for single-sampled surfaces because + * the color buffer should always have been resolved before it is used as + * a texture so there is no need for it. On Gen9 it will be uploaded when + * the surface is losslessly compressed (CCS_E). + */ + if (mt->num_samples <= 1 && aux_mode != GEN9_SURFACE_AUX_MODE_CCS_E) { + aux_mt = NULL; + aux_mode = GEN8_SURFACE_AUX_MODE_NONE; } - const uint32_t surf_type = translate_tex_target(target); - uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index); + uint32_t *surf = gen8_allocate_surface_state(brw, surf_offset, surf_index); surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) | format << BRW_SURFACE_FORMAT_SHIFT | - vertical_alignment(brw, mt, surf_type) | - horizontal_alignment(brw, mt, surf_type) | + gen8_vertical_alignment(brw, mt, surf_type) | + gen8_horizontal_alignment(brw, mt, surf_type) | tiling_mode; if (surf_type == BRW_SURFACE_CUBE) { @@ -252,7 +286,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw, format == BRW_SURFACEFORMAT_BC7_UNORM)) surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE; - if (_mesa_is_array_texture(target) || target == GL_TEXTURE_CUBE_MAP) + if (_mesa_is_array_texture(mt->target) || mt->target == GL_TEXTURE_CUBE_MAP) surf[0] |= GEN8_SURFACE_IS_ARRAY; surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2; @@ -276,14 +310,18 @@ gen8_emit_texture_surface_state(struct brw_context *brw, } if (aux_mt) { + uint32_t tile_w, tile_h; + assert(aux_mt->tiling == I915_TILING_Y); + intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode, + aux_mt->cpp, &tile_w, &tile_h); surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) | - SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) | + SET_FIELD((aux_mt->pitch / tile_w) - 1, + GEN8_SURFACE_AUX_PITCH) | aux_mode; - } else { - surf[6] = 0; } - surf[7] = mt->fast_clear_color_value | + gen8_emit_fast_clear_color(brw, mt, surf); + surf[7] |= SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) | SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) | SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) | @@ -297,11 +335,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw, aux_mt->bo, 0, I915_GEM_DOMAIN_SAMPLER, (rw ? I915_GEM_DOMAIN_SAMPLER : 0)); - } else { - surf[10] = 0; - surf[11] = 0; } - surf[12] = 0; /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->batch.bo, @@ -316,7 +350,8 @@ static void gen8_update_texture_surface(struct gl_context *ctx, unsigned unit, uint32_t *surf_offset, - bool for_gather) + bool for_gather, + uint32_t plane) { struct brw_context *brw = brw_context(ctx); struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current; @@ -350,14 +385,24 @@ gen8_update_texture_surface(struct gl_context *ctx, if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) { mt = mt->stencil_mt; format = BRW_SURFACEFORMAT_R8_UINT; + } else if (obj->Target == GL_TEXTURE_EXTERNAL_OES) { + if (plane > 0) + mt = mt->plane[plane - 1]; + if (mt == NULL) + return; + + format = translate_tex_format(brw, mt->format, sampler->sRGBDecode); + } + const int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; + gen8_emit_texture_surface_state(brw, mt, obj->Target, obj->MinLayer, obj->MinLayer + depth, obj->MinLevel + obj->BaseLevel, obj->MinLevel + intel_obj->_MaxLevel + 1, format, swizzle, surf_offset, - false, for_gather); + surf_index, false, for_gather); } } @@ -376,7 +421,7 @@ gen8_emit_null_surface_state(struct brw_context *brw, unsigned samples, uint32_t *out_offset) { - uint32_t *surf = allocate_surface_state(brw, out_offset, -1); + uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1); surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT | BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT | @@ -399,8 +444,6 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; - struct intel_mipmap_tree *aux_mt = NULL; - uint32_t aux_mode = 0; unsigned width = mt->logical_width0; unsigned height = mt->logical_height0; unsigned pitch = mt->pitch; @@ -431,7 +474,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, /* fallthrough */ default: surf_type = translate_tex_target(gl_target); - is_array = _mesa_tex_target_is_array(gl_target); + is_array = _mesa_is_array_texture(mt->target); break; } @@ -453,30 +496,17 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, __func__, _mesa_get_format_name(rb_format)); } - if (mt->mcs_mt) { - aux_mt = mt->mcs_mt; - aux_mode = GEN8_SURFACE_AUX_MODE_MCS; - - /* - * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE): - * "When MCS is enabled for non-MSRT, HALIGN_16 must be used" - * - * From the hardware spec for GEN9: - * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN - * 16 must be used." - */ - assert(brw->gen < 9 || mt->align_w == 16); - assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16); - } + struct intel_mipmap_tree *aux_mt = mt->mcs_mt; + const uint32_t aux_mode = gen8_get_aux_mode(brw, mt); - uint32_t *surf = allocate_surface_state(brw, &offset, surf_index); + uint32_t *surf = gen8_allocate_surface_state(brw, &offset, surf_index); surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | (is_array ? GEN7_SURFACE_IS_ARRAY : 0) | (format << BRW_SURFACE_FORMAT_SHIFT) | - vertical_alignment(brw, mt, surf_type) | - horizontal_alignment(brw, mt, surf_type) | - surface_tiling_mode(tiling); + gen8_vertical_alignment(brw, mt, surf_type) | + gen8_horizontal_alignment(brw, mt, surf_type) | + gen8_surface_tiling_mode(tiling); surf[1] = SET_FIELD(mocs, GEN8_SURFACE_MOCS) | mt->qpitch >> 2; @@ -501,18 +531,21 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, } if (aux_mt) { + uint32_t tile_w, tile_h; + assert(aux_mt->tiling == I915_TILING_Y); + intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode, + aux_mt->cpp, &tile_w, &tile_h); surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) | - SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) | + SET_FIELD((aux_mt->pitch / tile_w) - 1, + GEN8_SURFACE_AUX_PITCH) | aux_mode; - } else { - surf[6] = 0; } - surf[7] = mt->fast_clear_color_value | - SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | - SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | - SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | - SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + gen8_emit_fast_clear_color(brw, mt, surf); + surf[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); assert(mt->offset % mt->cpp == 0); *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */ @@ -523,11 +556,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, offset + 10 * 4, aux_mt->bo, 0, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - } else { - surf[10] = 0; - surf[11] = 0; } - surf[12] = 0; drm_intel_bo_emit_reloc(brw->batch.bo, offset + 8 * 4,