X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_blit.c;h=9500bd70e8142e37372a6af6fb1d6246031a28f0;hb=ce3f46397d77141156f81dd7fcf06fb936e2b0ef;hp=9806e5001e6e21b983a472bac9c6dc682db6e861;hpb=b15f1fc3c6b3b9dc4422940c412f80e581c9900d;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 9806e5001e6..9500bd70e81 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -1,8 +1,8 @@ /************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * + * Copyright 2003 VMware, Inc. * All Rights Reserved. - * + * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -10,19 +10,19 @@ * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: - * + * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * + * **************************************************************************/ @@ -33,11 +33,11 @@ #include "main/fbobject.h" #include "brw_context.h" +#include "brw_defines.h" #include "intel_blit.h" #include "intel_buffers.h" #include "intel_fbo.h" #include "intel_reg.h" -#include "intel_regions.h" #include "intel_batchbuffer.h" #include "intel_mipmap_tree.h" @@ -85,8 +85,7 @@ br13_for_cpp(int cpp) return BR13_8; break; default: - assert(0); - return 0; + unreachable("not reached"); } } @@ -104,8 +103,7 @@ static void set_blitter_tiling(struct brw_context *brw, bool dst_y_tiled, bool src_y_tiled) { - struct intel_context *intel = &brw->intel; - assert(intel->gen >= 6); + assert(brw->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ OUT_BATCH(MI_FLUSH_DW); @@ -158,12 +156,16 @@ intel_miptree_blit(struct brw_context *brw, uint32_t width, uint32_t height, GLenum logicop) { + /* The blitter doesn't understand multisampling at all. */ + if (src_mt->num_samples > 0 || dst_mt->num_samples > 0) + return false; + /* No sRGB decode or encode is done by the hardware blitter, which is * consistent with what we want in the callers (glCopyTexSubImage(), * glBlitFramebuffer(), texture validation, etc.). */ - gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format); - gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format); + mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format); + mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format); /* The blitter doesn't support doing any format conversions. We do also * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into @@ -171,10 +173,10 @@ intel_miptree_blit(struct brw_context *brw, * channel to 1.0 at the end. */ if (src_format != dst_format && - ((src_format != MESA_FORMAT_ARGB8888 && - src_format != MESA_FORMAT_XRGB8888) || - (dst_format != MESA_FORMAT_ARGB8888 && - dst_format != MESA_FORMAT_XRGB8888))) { + ((src_format != MESA_FORMAT_B8G8R8A8_UNORM && + src_format != MESA_FORMAT_B8G8R8X8_UNORM) || + (dst_format != MESA_FORMAT_B8G8R8A8_UNORM && + dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) { perf_debug("%s: Can't use hardware blitter from %s to %s, " "falling back.\n", __FUNCTION__, _mesa_get_format_name(src_format), @@ -198,11 +200,11 @@ intel_miptree_blit(struct brw_context *brw, * pitches < 32k. * * As a result of these two limitations, we can only use the blitter to do - * this copy when the region's pitch is less than 32k. + * this copy when the miptree's pitch is less than 32k. */ - if (src_mt->region->pitch > 32768 || - dst_mt->region->pitch > 32768) { - perf_debug("Falling back due to >32k pitch\n"); + if (src_mt->pitch >= 32768 || + dst_mt->pitch >= 32768) { + perf_debug("Falling back due to >=32k pitch\n"); return false; } @@ -215,35 +217,43 @@ intel_miptree_blit(struct brw_context *brw, intel_miptree_resolve_color(brw, dst_mt); if (src_flip) - src_y = src_mt->level[src_level].height - src_y - height; + src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height; if (dst_flip) - dst_y = dst_mt->level[dst_level].height - dst_y - height; + dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height; - int src_pitch = src_mt->region->pitch; + int src_pitch = src_mt->pitch; if (src_flip != dst_flip) src_pitch = -src_pitch; - uint32_t src_image_x, src_image_y; + uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y; intel_miptree_get_image_offset(src_mt, src_level, src_slice, &src_image_x, &src_image_y); - src_x += src_image_x; - src_y += src_image_y; - - uint32_t dst_image_x, dst_image_y; intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice, &dst_image_x, &dst_image_y); + src_x += src_image_x; + src_y += src_image_y; dst_x += dst_image_x; dst_y += dst_image_y; + /* The blitter interprets the 16-bit destination x/y as a signed 16-bit + * value. The values we're working with are unsigned, so make sure we don't + * overflow. + */ + if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) { + perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n", + src_x, src_y, dst_x, dst_y); + return false; + } + if (!intelEmitCopyBlit(brw, src_mt->cpp, src_pitch, - src_mt->region->bo, src_mt->offset, - src_mt->region->tiling, - dst_mt->region->pitch, - dst_mt->region->bo, dst_mt->offset, - dst_mt->region->tiling, + src_mt->bo, src_mt->offset, + src_mt->tiling, + dst_mt->pitch, + dst_mt->bo, dst_mt->offset, + dst_mt->tiling, src_x, src_y, dst_x, dst_y, width, height, @@ -251,8 +261,8 @@ intel_miptree_blit(struct brw_context *brw, return false; } - if (src_mt->format == MESA_FORMAT_XRGB8888 && - dst_mt->format == MESA_FORMAT_ARGB8888) { + if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM && + dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) { intel_miptree_set_alpha_to_one(brw, dst_mt, dst_x, dst_y, width, height); @@ -279,14 +289,12 @@ intelEmitCopyBlit(struct brw_context *brw, GLshort w, GLshort h, GLenum logic_op) { - struct intel_context *intel = &brw->intel; GLuint CMD, BR13, pass = 0; int dst_y2 = dst_y + h; int dst_x2 = dst_x + w; drm_intel_bo *aper_array[3]; bool dst_y_tiled = dst_tiling == I915_TILING_Y; bool src_y_tiled = src_tiling == I915_TILING_Y; - BATCH_LOCALS; if (dst_tiling != I915_TILING_NONE) { if (dst_offset & 4095) @@ -296,9 +304,12 @@ intelEmitCopyBlit(struct brw_context *brw, if (src_offset & 4095) return false; } - if ((dst_y_tiled || src_y_tiled) && intel->gen < 6) + if ((dst_y_tiled || src_y_tiled) && brw->gen < 6) return false; + assert(!dst_y_tiled || (dst_pitch % 128) == 0); + assert(!src_y_tiled || (src_pitch % 128) == 0); + /* do space check before going any further */ do { aper_array[0] = brw->batch.bo; @@ -315,16 +326,19 @@ intelEmitCopyBlit(struct brw_context *brw, if (pass >= 2) return false; - intel_batchbuffer_require_space(brw, 8 * 4, true); + unsigned length = brw->gen >= 8 ? 10 : 8; + + intel_batchbuffer_require_space(brw, length * 4, BLT_RING); DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", __FUNCTION__, src_buffer, src_pitch, src_offset, src_x, src_y, dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop - * the low bits. + * the low bits. Offsets must be naturally aligned. */ - if (src_pitch % 4 != 0 || dst_pitch % 4 != 0) + if (src_pitch % 4 != 0 || src_offset % cpp != 0 || + dst_pitch % 4 != 0 || dst_offset % cpp != 0) return false; /* For big formats (such as floating point), do the copy using 16 or 32bpp @@ -374,21 +388,36 @@ intelEmitCopyBlit(struct brw_context *brw, assert(dst_x < dst_x2); assert(dst_y < dst_y2); + assert(src_offset + (src_y + h - 1) * abs(src_pitch) + + (w * cpp) <= src_buffer->size); + assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) + + (w * cpp) <= dst_buffer->size); - BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled); - - OUT_BATCH(CMD | (8 - 2)); + BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled); + OUT_BATCH(CMD | (length - 2)); OUT_BATCH(BR13 | (uint16_t)dst_pitch); - OUT_BATCH((dst_y << 16) | dst_x); - OUT_BATCH((dst_y2 << 16) | dst_x2); - OUT_RELOC_FENCED(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); - OUT_BATCH((src_y << 16) | src_x); + OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X)); + OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X)); + if (brw->gen >= 8) { + OUT_RELOC64(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); + } else { + OUT_RELOC(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); + } + OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X)); OUT_BATCH((uint16_t)src_pitch); - OUT_RELOC_FENCED(src_buffer, - I915_GEM_DOMAIN_RENDER, 0, - src_offset); + if (brw->gen >= 8) { + OUT_RELOC64(src_buffer, + I915_GEM_DOMAIN_RENDER, 0, + src_offset); + } else { + OUT_RELOC(src_buffer, + I915_GEM_DOMAIN_RENDER, 0, + src_offset); + } ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled); @@ -420,8 +449,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, return false; } - assert( logic_op - GL_CLEAR >= 0 ); - assert( logic_op - GL_CLEAR < 0x10 ); + assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f))); assert(dst_pitch > 0); if (w < 0 || h < 0) @@ -431,7 +459,9 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); - intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, true); + unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8; + intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) + + (3 * 4) + dwords * 4, BLT_RING); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) @@ -448,24 +478,32 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, if (dst_tiling != I915_TILING_NONE) blit_cmd |= XY_DST_TILED; - BEGIN_BATCH_BLT(8 + 3); - OUT_BATCH(opcode | (8 - 2)); + BEGIN_BATCH_BLT(xy_setup_blt_length + 3); + OUT_BATCH(opcode | (xy_setup_blt_length - 2)); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ - OUT_RELOC_FENCED(dst_buffer, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - dst_offset); + if (brw->gen >= 8) { + OUT_RELOC64(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); + } else { + OUT_RELOC(dst_buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + dst_offset); + } OUT_BATCH(0); /* bg */ OUT_BATCH(fg_color); /* fg */ OUT_BATCH(0); /* pattern base addr */ + if (brw->gen >= 8) + OUT_BATCH(0); OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); - OUT_BATCH((y << 16) | x); - OUT_BATCH(((y + h) << 16) | (x + w)); + OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X)); + OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X)); ADVANCE_BATCH(); - intel_batchbuffer_data(brw, src_bits, dwords * 4, true); + intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING); intel_batchbuffer_emit_mi_flush(brw); @@ -484,8 +522,7 @@ intel_emit_linear_blit(struct brw_context *brw, unsigned int src_offset, unsigned int size) { - struct intel_context *intel = &brw->intel; - struct gl_context *ctx = &intel->ctx; + struct gl_context *ctx = &brw->ctx; GLuint pitch, height; bool ok; @@ -536,23 +573,21 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, struct intel_mipmap_tree *mt, int x, int y, int width, int height) { - struct intel_region *region = mt->region; uint32_t BR13, CMD; int pitch, cpp; drm_intel_bo *aper_array[2]; - BATCH_LOCALS; - pitch = region->pitch; - cpp = region->cpp; + pitch = mt->pitch; + cpp = mt->cpp; DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", - __FUNCTION__, region->bo, pitch, x, y, width, height); + __FUNCTION__, mt->bo, pitch, x, y, width, height); BR13 = br13_for_cpp(cpp) | 0xf0 << 16; CMD = XY_COLOR_BLT_CMD; CMD |= XY_BLT_WRITE_ALPHA; - if (region->tiling != I915_TILING_NONE) { + if (mt->tiling != I915_TILING_NONE) { CMD |= XY_DST_TILED; pitch /= 4; } @@ -560,23 +595,30 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw, /* do space check before going any further */ aper_array[0] = brw->batch.bo; - aper_array[1] = region->bo; + aper_array[1] = mt->bo; if (drm_intel_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)) != 0) { intel_batchbuffer_flush(brw); } - bool dst_y_tiled = region->tiling == I915_TILING_Y; + unsigned length = brw->gen >= 8 ? 7 : 6; + bool dst_y_tiled = mt->tiling == I915_TILING_Y; - BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false); - OUT_BATCH(CMD | (6 - 2)); + BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false); + OUT_BATCH(CMD | (length - 2)); OUT_BATCH(BR13); - OUT_BATCH((y << 16) | x); - OUT_BATCH(((y + height) << 16) | (x + width)); - OUT_RELOC_FENCED(region->bo, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - 0); + OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X)); + OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X)); + if (brw->gen >= 8) { + OUT_RELOC64(mt->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); + } else { + OUT_RELOC(mt->bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); + } OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ ADVANCE_BATCH_TILED(dst_y_tiled, false);