X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_blit.c;h=b7a9cc951cb5d61603adcbd848497e2c517aed8e;hb=9c9f45b82410646d2f7a8576d03de9916118bf07;hp=0cd2a203cb39c42b9895a87fbf8e90d54225e264;hpb=0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 0cd2a203cb3..b7a9cc951cb 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -27,7 +27,6 @@ #include "main/blit.h" #include "main/context.h" #include "main/enums.h" -#include "main/colormac.h" #include "main/fbobject.h" #include "brw_context.h" @@ -35,7 +34,6 @@ #include "intel_blit.h" #include "intel_buffers.h" #include "intel_fbo.h" -#include "intel_reg.h" #include "intel_batchbuffer.h" #include "intel_mipmap_tree.h" @@ -105,64 +103,6 @@ br13_for_cpp(int cpp) } } -static uint32_t -get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) { - /* Alignment tables for YF/YS tiled surfaces. */ - const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16}; - const uint32_t bpp = cpp * 8; - const uint32_t shift = is_src ? 17 : 10; - uint32_t align; - int i = 0; - - if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) - return 0; - - /* Compute array index. */ - assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); - i = ffs(bpp / 8) - 1; - - align = tr_mode == INTEL_MIPTREE_TRMODE_YF ? - align_2d_yf[i] : - 4 * align_2d_yf[i]; - - assert(_mesa_is_pow_two(align)); - - /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */ - if (align == 16) - align = 32; - - return (ffs(align) - 6) << shift; -} - -static uint32_t -get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) { - /* Vertical alignment tables for YF/YS tiled surfaces. */ - const unsigned align_2d_yf[] = {64, 32, 32, 16, 16}; - const uint32_t bpp = cpp * 8; - const uint32_t shift = is_src ? 15 : 8; - uint32_t align; - int i = 0; - - if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) - return 0; - - /* Compute array index. */ - assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)); - i = ffs(bpp / 8) - 1; - - align = tr_mode == INTEL_MIPTREE_TRMODE_YF ? - align_2d_yf[i] : - 4 * align_2d_yf[i]; - - assert(_mesa_is_pow_two(align)); - - /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */ - if (align == 16 || align == 32) - align = 64; - - return (ffs(align) - 7) << shift; -} - /** * Emits the packet for switching the blitter from X to Y tiled or back. * @@ -270,8 +210,8 @@ intel_miptree_blit(struct brw_context *brw, return false; /* No sRGB decode or encode is done by the hardware blitter, which is - * consistent with what we want in the callers (glCopyTexSubImage(), - * glBlitFramebuffer(), texture validation, etc.). + * consistent with what we want in many callers (glCopyTexSubImage(), + * texture validation, etc.). */ mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format); mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format); @@ -318,8 +258,8 @@ intel_miptree_blit(struct brw_context *brw, */ intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice); intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice); - intel_miptree_resolve_color(brw, src_mt); - intel_miptree_resolve_color(brw, dst_mt); + intel_miptree_resolve_color(brw, src_mt, 0); + intel_miptree_resolve_color(brw, dst_mt, 0); if (src_flip) src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height; @@ -399,7 +339,8 @@ can_fast_copy_blit(struct brw_context *brw, int16_t dst_x, int16_t dst_y, uintptr_t dst_offset, uint32_t dst_pitch, uint32_t dst_tiling, uint32_t dst_tr_mode, - int16_t w, int16_t h, uint32_t cpp) + int16_t w, int16_t h, uint32_t cpp, + GLenum logic_op) { const bool dst_tiling_none = dst_tiling == I915_TILING_NONE; const bool src_tiling_none = src_tiling == I915_TILING_NONE; @@ -407,11 +348,6 @@ can_fast_copy_blit(struct brw_context *brw, if (brw->gen < 9) return false; - if (src_buffer->handle == dst_buffer->handle && - _mesa_regions_overlap(src_x, src_y, src_x + w, src_y + h, - dst_x, dst_y, dst_x + w, dst_y + h)) - return false; - /* Enable fast copy blit only if the surfaces are Yf/Ys tiled. * FIXME: Based on performance data, remove this condition later to * enable for all types of surfaces. @@ -420,12 +356,21 @@ can_fast_copy_blit(struct brw_context *brw, dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE) return false; + if (logic_op != GL_COPY) + return false; + + /* The start pixel for Fast Copy blit should be on an OWord boundary. */ + if ((dst_x * cpp | src_x * cpp) & 15) + return false; + /* For all surface types buffers must be cacheline-aligned. */ if ((dst_offset | src_offset) & 63) return false; - /* Color depth greater than 128 bits not supported. */ - if (cpp > 16) + /* Color depths which are not power of 2 or greater than 128 bits are + * not supported. + */ + if (!_mesa_is_pow_two(cpp) || cpp > 16) return false; /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15 @@ -439,14 +384,6 @@ can_fast_copy_blit(struct brw_context *brw, (dst_tiling_none && dst_pitch % 16 != 0)) return false; - /* For Tiled surfaces, the pitch has to be a multiple of the Tile width - * (X direction width of the Tile). This means the pitch value will - * always be Cache Line aligned (64byte multiple). - */ - if ((!dst_tiling_none && dst_pitch % 64 != 0) || - (!src_tiling_none && src_pitch % 64 != 0)) - return false; - return true; } @@ -465,13 +402,6 @@ xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode, if (src_tiling != I915_TILING_NONE) SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC); - - CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */); - CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */); - - CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */); - CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */); - } else { assert(cpp <= 4); switch (cpp) { @@ -555,6 +485,13 @@ intelEmitCopyBlit(struct brw_context *brw, intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h); intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h); + /* For Tiled surfaces, the pitch has to be a multiple of the Tile width + * (X direction width of the Tile). This is ensured while allocating the + * buffer object. + */ + assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0); + assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0); + use_fast_copy_blit = can_fast_copy_blit(brw, src_buffer, src_x, src_y, @@ -564,12 +501,15 @@ intelEmitCopyBlit(struct brw_context *brw, dst_x, dst_y, dst_offset, dst_pitch, dst_tiling, dst_tr_mode, - w, h, cpp); - assert(use_fast_copy_blit || - (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE && - dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)); + w, h, cpp, logic_op); + if (!use_fast_copy_blit && + (src_tr_mode != INTEL_MIPTREE_TRMODE_NONE || + dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE)) + return false; if (use_fast_copy_blit) { + assert(logic_op == GL_COPY); + /* When two sequential fast copy blits have different source surfaces, * but their destinations refer to the same destination surfaces and * therefore destinations overlap it is imperative that a flush be @@ -593,9 +533,6 @@ intelEmitCopyBlit(struct brw_context *brw, cpp, use_fast_copy_blit); } else { - assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0); - assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0); - /* For big formats (such as floating point), do the copy using 16 or * 32bpp and multiply the coordinates. */