X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fintel_mipmap_tree.c;h=7623d28aad110c58b01188416b0ec533de53b48b;hb=42db7ab1794e3de24acb15593db93c4f6d57ae32;hp=c705c986bad04acab82656203774a17c6f7babf2;hpb=e974456d4f2f3977c07ebe2e931d8d361076a2d2;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index c705c986bad..7623d28aad1 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -262,7 +262,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw, if (brw->gen >= 9) { mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format); const uint32_t brw_format = brw_format_for_mesa_format(linear_format); - return isl_format_supports_lossless_compression(brw->intelScreen->devinfo, + return isl_format_supports_lossless_compression(&brw->screen->devinfo, brw_format); } else return true; @@ -282,7 +282,7 @@ intel_miptree_is_lossless_compressed(const struct brw_context *brw, return false; /* Compression always requires auxiliary buffer. */ - if (!mt->mcs_mt) + if (!mt->mcs_buf) return false; /* Single sample compression is represented re-using msaa compression @@ -364,25 +364,8 @@ intel_miptree_create_layout(struct brw_context *brw, _mesa_get_format_name(format), first_level, last_level, depth0, mt); - if (target == GL_TEXTURE_1D_ARRAY) { - /* For a 1D Array texture the OpenGL API will treat the height0 - * parameter as the number of array slices. For Intel hardware, we treat - * the 1D array as a 2D Array with a height of 1. - * - * So, when we first come through this path to create a 1D Array - * texture, height0 stores the number of slices, and depth0 is 1. In - * this case, we want to swap height0 and depth0. - * - * Since some miptrees will be created based on the base miptree, we may - * come through this path and see height0 as 1 and depth0 being the - * number of slices. In this case we don't need to do the swap. - */ - assert(height0 == 1 || depth0 == 1); - if (height0 > 1) { - depth0 = height0; - height0 = 1; - } - } + if (target == GL_TEXTURE_1D_ARRAY) + assert(height0 == 1); mt->target = target; mt->format = format; @@ -401,6 +384,7 @@ intel_miptree_create_layout(struct brw_context *brw, mt->msaa_layout = INTEL_MSAA_LAYOUT_NONE; mt->refcount = 1; + int depth_multiply = 1; if (num_samples > 1) { /* Adjust width/height/depth for MSAA */ mt->msaa_layout = compute_msaa_layout(brw, format, @@ -487,7 +471,8 @@ intel_miptree_create_layout(struct brw_context *brw, } } else { /* Non-interleaved */ - depth0 *= num_samples; + depth_multiply = num_samples; + depth0 *= depth_multiply; } } @@ -516,10 +501,8 @@ intel_miptree_create_layout(struct brw_context *brw, } } - if (target == GL_TEXTURE_CUBE_MAP) { - assert(depth0 == 1); - depth0 = 6; - } + if (target == GL_TEXTURE_CUBE_MAP) + assert(depth0 == 6 * depth_multiply); mt->physical_width0 = width0; mt->physical_height0 = height0; @@ -551,6 +534,7 @@ intel_miptree_create_layout(struct brw_context *brw, intel_miptree_release(&mt); return NULL; } + mt->stencil_mt->r8stencil_needs_update = true; /* Fix up the Z miptree format for how we're splitting out separate * stencil. Gen7 expects there to be no stencil bits in its depth buffer. @@ -690,7 +674,6 @@ miptree_create(struct brw_context *brw, etc_format = (format != tex_format) ? tex_format : MESA_FORMAT_NONE; - assert((layout_flags & MIPTREE_LAYOUT_DISABLE_AUX) == 0); assert((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0); mt = intel_miptree_create_layout(brw, target, format, first_level, last_level, width0, @@ -806,6 +789,20 @@ intel_miptree_create(struct brw_context *brw, intel_miptree_supports_non_msrt_fast_clear(brw, mt)) { mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED; assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1); + + /* On Gen9+ clients are not currently capable of consuming compressed + * single-sampled buffers. Disabling compression allows us to skip + * resolves. + */ + const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC; + const bool is_lossless_compressed = + unlikely(!lossless_compression_disabled) && + brw->gen >= 9 && !mt->is_scanout && + intel_miptree_supports_lossless_compressed(brw, mt); + + if (is_lossless_compressed) { + intel_miptree_alloc_non_msrt_mcs(brw, mt, is_lossless_compressed); + } } return mt; @@ -1014,6 +1011,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt) drm_intel_bo_unreference((*mt)->bo); intel_miptree_release(&(*mt)->stencil_mt); + intel_miptree_release(&(*mt)->r8stencil_mt); if ((*mt)->hiz_buf) { if ((*mt)->hiz_buf->mt) intel_miptree_release(&(*mt)->hiz_buf->mt); @@ -1021,7 +1019,10 @@ intel_miptree_release(struct intel_mipmap_tree **mt) drm_intel_bo_unreference((*mt)->hiz_buf->bo); free((*mt)->hiz_buf); } - intel_miptree_release(&(*mt)->mcs_mt); + if ((*mt)->mcs_buf) { + intel_miptree_release(&(*mt)->mcs_buf->mt); + free((*mt)->mcs_buf); + } intel_resolve_map_clear(&(*mt)->hiz_map); intel_miptree_release(&(*mt)->plane[0]); @@ -1048,10 +1049,20 @@ intel_get_image_dims(struct gl_texture_image *image, * as a 2D Array with a height of 1. So, here we want to swap image * height and depth. */ + assert(image->Depth == 1); *width = image->Width; *height = 1; *depth = image->Height; break; + case GL_TEXTURE_CUBE_MAP: + /* For Cube maps, the mesa/main api layer gives us a depth of 1 even + * though we really have 6 slices. + */ + assert(image->Depth == 1); + *width = image->Width; + *height = image->Height; + *depth = 6; + break; default: *width = image->Width; *height = image->Height; @@ -1241,12 +1252,9 @@ intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, */ void intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, - bool map_stencil_as_y_tiled, uint32_t *mask_x, uint32_t *mask_y) { uint32_t tile_w_bytes, tile_h; - if (map_stencil_as_y_tiled) - tiling = I915_TILING_Y; intel_get_tile_dims(tiling, tr_mode, cpp, &tile_w_bytes, &tile_h); @@ -1261,26 +1269,12 @@ intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, */ uint32_t intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt, - uint32_t x, uint32_t y, - bool map_stencil_as_y_tiled) + uint32_t x, uint32_t y) { int cpp = mt->cpp; uint32_t pitch = mt->pitch; uint32_t tiling = mt->tiling; - if (map_stencil_as_y_tiled) { - tiling = I915_TILING_Y; - - /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile - * gets transformed into a 32-high Y-tile. Accordingly, the pitch of - * the resulting surface is twice the pitch of the original miptree, - * since each row in the Y-tiled view corresponds to two rows in the - * actual W-tiled surface. So we need to correct the pitch before - * computing the offsets. - */ - pitch *= 2; - } - switch (tiling) { default: unreachable("not reached"); @@ -1316,13 +1310,13 @@ intel_miptree_get_tile_offsets(const struct intel_mipmap_tree *mt, uint32_t x, y; uint32_t mask_x, mask_y; - intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, false, &mask_x, &mask_y); + intel_get_tile_masks(mt->tiling, mt->tr_mode, mt->cpp, &mask_x, &mask_y); intel_miptree_get_image_offset(mt, level, slice, &x, &y); *tile_x = x & mask_x; *tile_y = y & mask_y; - return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, false); + return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y); } static void @@ -1502,19 +1496,67 @@ intel_miptree_init_mcs(struct brw_context *brw, * * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff. */ - void *data = intel_miptree_map_raw(brw, mt->mcs_mt); - memset(data, init_value, mt->mcs_mt->total_height * mt->mcs_mt->pitch); - intel_miptree_unmap_raw(mt->mcs_mt); + const int ret = brw_bo_map_gtt(brw, mt->mcs_buf->bo, "miptree"); + if (unlikely(ret)) { + fprintf(stderr, "Failed to map mcs buffer into GTT\n"); + intel_miptree_release(&mt->mcs_buf->mt); + free(mt->mcs_buf); + return; + } + void *data = mt->mcs_buf->bo->virtual; + memset(data, init_value, + mt->mcs_buf->mt->total_height * mt->mcs_buf->mt->pitch); + drm_intel_bo_unmap(mt->mcs_buf->bo); mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR; } +static struct intel_miptree_aux_buffer * +intel_mcs_miptree_buf_create(struct brw_context *brw, + struct intel_mipmap_tree *mt, + mesa_format format, + unsigned mcs_width, + unsigned mcs_height, + uint32_t layout_flags) +{ + struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1); + + if (!buf) + return NULL; + + /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address": + * + * "The MCS surface must be stored as Tile Y." + */ + layout_flags |= MIPTREE_LAYOUT_TILING_Y; + buf->mt = miptree_create(brw, + mt->target, + format, + mt->first_level, + mt->last_level, + mcs_width, + mcs_height, + mt->logical_depth0, + 0 /* num_samples */, + layout_flags); + if (!buf->mt) { + free(buf); + return NULL; + } + + buf->bo = buf->mt->bo; + buf->pitch = buf->mt->pitch; + buf->qpitch = buf->mt->qpitch; + + return buf; +} + static bool intel_miptree_alloc_mcs(struct brw_context *brw, struct intel_mipmap_tree *mt, GLuint num_samples) { assert(brw->gen >= 7); /* MCS only used on Gen7+ */ - assert(mt->mcs_mt == NULL); + assert(mt->mcs_buf == NULL); assert(!mt->disable_aux_buffers); /* Choose the correct format for the MCS buffer. All that really matters @@ -1547,34 +1589,25 @@ intel_miptree_alloc_mcs(struct brw_context *brw, unreachable("Unrecognized sample count in intel_miptree_alloc_mcs"); }; - /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address": - * - * "The MCS surface must be stored as Tile Y." - */ - const uint32_t mcs_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD | - MIPTREE_LAYOUT_TILING_Y; - mt->mcs_mt = miptree_create(brw, - mt->target, - format, - mt->first_level, - mt->last_level, - mt->logical_width0, - mt->logical_height0, - mt->logical_depth0, - 0 /* num_samples */, - mcs_flags); + mt->mcs_buf = + intel_mcs_miptree_buf_create(brw, mt, + format, + mt->logical_width0, + mt->logical_height0, + MIPTREE_LAYOUT_ACCELERATED_UPLOAD); intel_miptree_init_mcs(brw, mt, 0xFF); - return mt->mcs_mt; + return mt->mcs_buf != NULL; } bool intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt) + struct intel_mipmap_tree *mt, + bool is_lossless_compressed) { - assert(mt->mcs_mt == NULL); + assert(mt->mcs_buf == NULL); assert(!mt->disable_aux_buffers); /* The format of the MCS buffer is opaque to the driver; all that matters @@ -1608,22 +1641,9 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, unsigned mcs_height = ALIGN(mt->logical_height0, height_divisor) / height_divisor; assert(mt->logical_depth0 == 1); - uint32_t layout_flags = MIPTREE_LAYOUT_TILING_Y; - - if (brw->gen >= 8) { - layout_flags |= MIPTREE_LAYOUT_FORCE_HALIGN16; - } - - /* On Gen9+ clients are not currently capable of consuming compressed - * single-sampled buffers. Disabling compression allows us to skip - * resolves. - */ - const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC; - const bool is_lossless_compressed = - unlikely(!lossless_compression_disabled) && - brw->gen >= 9 && !mt->is_scanout && - intel_miptree_supports_lossless_compressed(brw, mt); + uint32_t layout_flags = + (brw->gen >= 8) ? MIPTREE_LAYOUT_FORCE_HALIGN16 : 0; /* In case of compression mcs buffer needs to be initialised requiring the * buffer to be immediately mapped to cpu space for writing. Therefore do * not use the gpu access flag which can cause an unnecessary delay if the @@ -1632,16 +1652,11 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, if (!is_lossless_compressed) layout_flags |= MIPTREE_LAYOUT_ACCELERATED_UPLOAD; - mt->mcs_mt = miptree_create(brw, - mt->target, - format, - mt->first_level, - mt->last_level, - mcs_width, - mcs_height, - mt->logical_depth0, - 0 /* num_samples */, - layout_flags); + mt->mcs_buf = intel_mcs_miptree_buf_create(brw, mt, + format, + mcs_width, + mcs_height, + layout_flags); /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are * used for lossless compression which requires similar initialisation @@ -1662,48 +1677,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, mt->msaa_layout = INTEL_MSAA_LAYOUT_CMS; } - return mt->mcs_mt; -} - -void -intel_miptree_prepare_mcs(struct brw_context *brw, - struct intel_mipmap_tree *mt) -{ - if (mt->mcs_mt) - return; - - if (brw->gen < 9) - return; - - /* Single sample compression is represented re-using msaa compression - * layout type: "Compressed Multisampled Surfaces". - */ - if (mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS || mt->num_samples > 1) - return; - - /* Clients are not currently capable of consuming compressed - * single-sampled buffers. - */ - if (mt->is_scanout) - return; - - assert(intel_tiling_supports_non_msrt_mcs(brw, mt->tiling) || - intel_miptree_supports_lossless_compressed(brw, mt)); - - /* Consider if lossless compression is supported but the needed - * auxiliary buffer doesn't exist yet. - * - * Failing to allocate the auxiliary buffer means running out of - * memory. The pointer to the aux miptree is left NULL which should - * signal non-compressed behavior. - */ - if (!intel_miptree_alloc_non_msrt_mcs(brw, mt)) { - _mesa_warning(NULL, - "Failed to allocated aux buffer for lossless" - " compressed %p %u:%u %s\n", - mt, mt->logical_width0, mt->logical_height0, - _mesa_get_format_name(mt->format)); - } + return mt->mcs_buf != NULL; } /** @@ -1803,14 +1777,8 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, hz_height = DIV_ROUND_UP(hz_height, 2); } else { const unsigned hz_qpitch = h0 + h1 + (12 * vertical_align); - if (mt->target == GL_TEXTURE_CUBE_MAP_ARRAY || - mt->target == GL_TEXTURE_CUBE_MAP) { - /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */ - hz_height = DIV_ROUND_UP(hz_qpitch * Z0 * 6, 2 * 8) * 8; - } else { - /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */ - hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8; - } + /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */ + hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8; } unsigned long pitch; @@ -1907,15 +1875,6 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, } else { /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */ hz_height = DIV_ROUND_UP(buf->qpitch, 2 * 8) * 8 * Z0; - if (mt->target == GL_TEXTURE_CUBE_MAP_ARRAY || - mt->target == GL_TEXTURE_CUBE_MAP) { - /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth - * - * We can can just take our hz_height calculation from above, and - * multiply by 6 for the cube map and cube map array types. - */ - hz_height *= 6; - } } unsigned long pitch; @@ -2028,7 +1987,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, exec_node_init(&m->link); m->level = level; m->layer = layer; - m->need = GEN6_HIZ_OP_HIZ_RESOLVE; + m->need = BLORP_HIZ_OP_HIZ_RESOLVE; exec_list_push_tail(&mt->hiz_map, &m->link); } @@ -2056,7 +2015,7 @@ intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, return; intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); + level, layer, BLORP_HIZ_OP_HIZ_RESOLVE); } @@ -2069,7 +2028,7 @@ intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, return; intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE); + level, layer, BLORP_HIZ_OP_DEPTH_RESOLVE); } void @@ -2089,7 +2048,7 @@ intel_miptree_slice_resolve(struct brw_context *brw, struct intel_mipmap_tree *mt, uint32_t level, uint32_t layer, - enum gen6_hiz_op need) + enum blorp_hiz_op need) { intel_miptree_check_level_layer(mt, level, layer); @@ -2111,7 +2070,7 @@ intel_miptree_slice_resolve_hiz(struct brw_context *brw, uint32_t layer) { return intel_miptree_slice_resolve(brw, mt, level, layer, - GEN6_HIZ_OP_HIZ_RESOLVE); + BLORP_HIZ_OP_HIZ_RESOLVE); } bool @@ -2121,13 +2080,13 @@ intel_miptree_slice_resolve_depth(struct brw_context *brw, uint32_t layer) { return intel_miptree_slice_resolve(brw, mt, level, layer, - GEN6_HIZ_OP_DEPTH_RESOLVE); + BLORP_HIZ_OP_DEPTH_RESOLVE); } static bool intel_miptree_all_slices_resolve(struct brw_context *brw, struct intel_mipmap_tree *mt, - enum gen6_hiz_op need) + enum blorp_hiz_op need) { bool did_resolve = false; @@ -2148,7 +2107,7 @@ intel_miptree_all_slices_resolve_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt) { return intel_miptree_all_slices_resolve(brw, mt, - GEN6_HIZ_OP_HIZ_RESOLVE); + BLORP_HIZ_OP_HIZ_RESOLVE); } bool @@ -2156,11 +2115,11 @@ intel_miptree_all_slices_resolve_depth(struct brw_context *brw, struct intel_mipmap_tree *mt) { return intel_miptree_all_slices_resolve(brw, mt, - GEN6_HIZ_OP_DEPTH_RESOLVE); + BLORP_HIZ_OP_DEPTH_RESOLVE); } -void +bool intel_miptree_resolve_color(struct brw_context *brw, struct intel_mipmap_tree *mt, int flags) @@ -2171,21 +2130,25 @@ intel_miptree_resolve_color(struct brw_context *brw, */ if ((flags & INTEL_MIPTREE_IGNORE_CCS_E) && intel_miptree_is_lossless_compressed(brw, mt)) - return; + return false; switch (mt->fast_clear_state) { case INTEL_FAST_CLEAR_STATE_NO_MCS: case INTEL_FAST_CLEAR_STATE_RESOLVED: /* No resolve needed */ - break; + return false; case INTEL_FAST_CLEAR_STATE_UNRESOLVED: case INTEL_FAST_CLEAR_STATE_CLEAR: /* Fast color clear resolves only make sense for non-MSAA buffers. */ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE || intel_miptree_is_lossless_compressed(brw, mt)) { brw_blorp_resolve_color(brw, mt); + return true; + } else { + return false; } - break; + default: + unreachable("Invalid fast clear state"); } } @@ -2210,9 +2173,9 @@ intel_miptree_make_shareable(struct brw_context *brw, */ assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE); - if (mt->mcs_mt) { + if (mt->mcs_buf) { intel_miptree_resolve_color(brw, mt, 0); - intel_miptree_release(&mt->mcs_mt); + intel_miptree_release(&mt->mcs_buf->mt); mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS; } } @@ -2305,6 +2268,62 @@ intel_miptree_updownsample(struct brw_context *brw, } } +void +intel_update_r8stencil(struct brw_context *brw, + struct intel_mipmap_tree *mt) +{ + assert(brw->gen >= 7); + struct intel_mipmap_tree *src = + mt->format == MESA_FORMAT_S_UINT8 ? mt : mt->stencil_mt; + if (!src || brw->gen >= 8 || !src->r8stencil_needs_update) + return; + + if (!mt->r8stencil_mt) { + const uint32_t r8stencil_flags = + MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y | + MIPTREE_LAYOUT_DISABLE_AUX; + assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */ + mt->r8stencil_mt = intel_miptree_create(brw, + src->target, + MESA_FORMAT_R_UINT8, + src->first_level, + src->last_level, + src->logical_width0, + src->logical_height0, + src->logical_depth0, + src->num_samples, + r8stencil_flags); + assert(mt->r8stencil_mt); + } + + struct intel_mipmap_tree *dst = mt->r8stencil_mt; + + for (int level = src->first_level; level <= src->last_level; level++) { + const unsigned depth = src->level[level].depth; + const int layers_per_blit = + (dst->msaa_layout == INTEL_MSAA_LAYOUT_UMS || + dst->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ? + dst->num_samples : 1; + + for (unsigned layer = 0; layer < depth; layer++) { + brw_blorp_blit_miptrees(brw, + src, level, layer, + src->format, SWIZZLE_X, + dst, level, layers_per_blit * layer, + MESA_FORMAT_R_UNORM8, + 0, 0, + src->logical_width0, src->logical_height0, + 0, 0, + dst->logical_width0, dst->logical_height0, + GL_NEAREST, false, false /*mirror x, y*/, + false, false /* decode/encode srgb */); + } + } + + brw_render_cache_set_check_flush(brw, dst->bo); + src->r8stencil_needs_update = false; +} + static void * intel_miptree_map_raw(struct brw_context *brw, struct intel_mipmap_tree *mt) { @@ -2486,6 +2505,9 @@ intel_miptree_map_movntdqa(struct brw_context *brw, void *src = intel_miptree_map_raw(brw, mt); if (!src) return; + + src += mt->offset; + src += image_y * mt->pitch; src += image_x * mt->cpp; @@ -2849,12 +2871,6 @@ static bool can_blit_slice(struct intel_mipmap_tree *mt, unsigned int level, unsigned int slice) { - uint32_t image_x; - uint32_t image_y; - intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y); - if (image_x >= 32768 || image_y >= 32768) - return false; - /* See intel_miptree_blit() for details on the 32k pitch limit. */ if (mt->pitch >= 32768) return false; @@ -2998,21 +3014,14 @@ intel_miptree_unmap(struct brw_context *brw, intel_miptree_release_map(mt, level, slice); } -void -intel_miptree_get_isl_surf(struct brw_context *brw, - const struct intel_mipmap_tree *mt, - struct isl_surf *surf) +enum isl_surf_dim +get_isl_surf_dim(GLenum target) { - switch (mt->target) { + switch (target) { case GL_TEXTURE_1D: - case GL_TEXTURE_1D_ARRAY: { - surf->dim = ISL_SURF_DIM_1D; - if (brw->gen >= 9 && mt->tiling == I915_TILING_NONE) - surf->dim_layout = ISL_DIM_LAYOUT_GEN9_1D; - else - surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D; - break; - } + case GL_TEXTURE_1D_ARRAY: + return ISL_SURF_DIM_1D; + case GL_TEXTURE_2D: case GL_TEXTURE_2D_ARRAY: case GL_TEXTURE_RECTANGLE: @@ -3021,20 +3030,83 @@ intel_miptree_get_isl_surf(struct brw_context *brw, case GL_TEXTURE_2D_MULTISAMPLE: case GL_TEXTURE_2D_MULTISAMPLE_ARRAY: case GL_TEXTURE_EXTERNAL_OES: - surf->dim = ISL_SURF_DIM_2D; - surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D; - break; + return ISL_SURF_DIM_2D; + case GL_TEXTURE_3D: - surf->dim = ISL_SURF_DIM_3D; - if (brw->gen >= 9) - surf->dim_layout = ISL_DIM_LAYOUT_GEN4_2D; - else - surf->dim_layout = ISL_DIM_LAYOUT_GEN4_3D; - break; - default: - unreachable("Invalid texture target"); + return ISL_SURF_DIM_3D; + } + + unreachable("Invalid texture target"); +} + +enum isl_dim_layout +get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling, + GLenum target) +{ + switch (target) { + case GL_TEXTURE_1D: + case GL_TEXTURE_1D_ARRAY: + return (devinfo->gen >= 9 && tiling == I915_TILING_NONE ? + ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); + + case GL_TEXTURE_2D: + case GL_TEXTURE_2D_ARRAY: + case GL_TEXTURE_RECTANGLE: + case GL_TEXTURE_2D_MULTISAMPLE: + case GL_TEXTURE_2D_MULTISAMPLE_ARRAY: + case GL_TEXTURE_EXTERNAL_OES: + return ISL_DIM_LAYOUT_GEN4_2D; + + case GL_TEXTURE_CUBE_MAP: + case GL_TEXTURE_CUBE_MAP_ARRAY: + return (devinfo->gen == 4 ? ISL_DIM_LAYOUT_GEN4_3D : + ISL_DIM_LAYOUT_GEN4_2D); + + case GL_TEXTURE_3D: + return (devinfo->gen >= 9 ? + ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D); } + unreachable("Invalid texture target"); +} + +enum isl_tiling +intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt) +{ + if (mt->format == MESA_FORMAT_S_UINT8) { + return ISL_TILING_W; + } else { + switch (mt->tiling) { + case I915_TILING_NONE: + return ISL_TILING_LINEAR; + case I915_TILING_X: + return ISL_TILING_X; + case I915_TILING_Y: + switch (mt->tr_mode) { + case INTEL_MIPTREE_TRMODE_NONE: + return ISL_TILING_Y0; + case INTEL_MIPTREE_TRMODE_YF: + return ISL_TILING_Yf; + case INTEL_MIPTREE_TRMODE_YS: + return ISL_TILING_Ys; + default: + unreachable("Invalid tiled resource mode"); + } + default: + unreachable("Invalid tiling mode"); + } + } +} + +void +intel_miptree_get_isl_surf(struct brw_context *brw, + const struct intel_mipmap_tree *mt, + struct isl_surf *surf) +{ + surf->dim = get_isl_surf_dim(mt->target); + surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo, + mt->tiling, mt->target); + if (mt->num_samples > 1) { switch (mt->msaa_layout) { case INTEL_MSAA_LAYOUT_IMS: @@ -3051,38 +3123,15 @@ intel_miptree_get_isl_surf(struct brw_context *brw, surf->msaa_layout = ISL_MSAA_LAYOUT_NONE; } + surf->tiling = intel_miptree_get_isl_tiling(mt); + if (mt->format == MESA_FORMAT_S_UINT8) { - surf->tiling = ISL_TILING_W; /* The ISL definition of row_pitch matches the surface state pitch field * a bit better than intel_mipmap_tree. In particular, ISL incorporates * the factor of 2 for W-tiling in row_pitch. */ surf->row_pitch = 2 * mt->pitch; } else { - switch (mt->tiling) { - case I915_TILING_NONE: - surf->tiling = ISL_TILING_LINEAR; - break; - case I915_TILING_X: - surf->tiling = ISL_TILING_X; - break; - case I915_TILING_Y: - switch (mt->tr_mode) { - case INTEL_MIPTREE_TRMODE_NONE: - surf->tiling = ISL_TILING_Y0; - break; - case INTEL_MIPTREE_TRMODE_YF: - surf->tiling = ISL_TILING_Yf; - break; - case INTEL_MIPTREE_TRMODE_YS: - surf->tiling = ISL_TILING_Ys; - break; - } - break; - default: - unreachable("Invalid tiling mode"); - } - surf->row_pitch = mt->pitch; } @@ -3111,11 +3160,6 @@ intel_miptree_get_isl_surf(struct brw_context *brw, if (surf->dim == ISL_SURF_DIM_3D) { surf->logical_level0_px.depth = mt->logical_depth0; surf->logical_level0_px.array_len = 1; - } else if (mt->target == GL_TEXTURE_CUBE_MAP || - mt->target == GL_TEXTURE_CUBE_MAP_ARRAY) { - /* For cube maps, mt->logical_depth0 is in number of cubes */ - surf->logical_level0_px.depth = 1; - surf->logical_level0_px.array_len = mt->logical_depth0 * 6; } else { surf->logical_level0_px.depth = 1; surf->logical_level0_px.array_len = mt->logical_depth0; @@ -3165,7 +3209,30 @@ intel_miptree_get_isl_surf(struct brw_context *brw, unreachable("Invalid array layout"); } - surf->usage = 0; /* TODO */ + GLenum base_format = _mesa_get_format_base_format(mt->format); + switch (base_format) { + case GL_DEPTH_COMPONENT: + surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT; + break; + case GL_STENCIL_INDEX: + surf->usage = ISL_SURF_USAGE_STENCIL_BIT; + if (brw->gen >= 8) + surf->usage |= ISL_SURF_USAGE_TEXTURE_BIT; + break; + case GL_DEPTH_STENCIL: + /* In this case we only texture from the depth part */ + surf->usage = ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT | + ISL_SURF_USAGE_TEXTURE_BIT; + break; + default: + surf->usage = ISL_SURF_USAGE_TEXTURE_BIT; + if (brw->format_supported_as_render_target[mt->format]) + surf->usage = ISL_SURF_USAGE_RENDER_TARGET_BIT; + break; + } + + if (_mesa_is_cube_map_texture(mt->target)) + surf->usage |= ISL_SURF_USAGE_CUBE_BIT; } /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE @@ -3178,33 +3245,47 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw, struct isl_surf *surf, enum isl_aux_usage *usage) { - /* Much is the same as the regular surface */ - intel_miptree_get_isl_surf(brw, mt->mcs_mt, surf); + uint32_t aux_pitch, aux_qpitch; + if (mt->mcs_buf) { + aux_pitch = mt->mcs_buf->mt->pitch; + aux_qpitch = mt->mcs_buf->mt->qpitch; + + if (mt->num_samples > 1) { + assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS); + *usage = ISL_AUX_USAGE_MCS; + } else if (intel_miptree_is_lossless_compressed(brw, mt)) { + assert(brw->gen >= 9); + *usage = ISL_AUX_USAGE_CCS_E; + } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) { + *usage = ISL_AUX_USAGE_CCS_D; + } else { + unreachable("Invalid MCS miptree"); + } + } else if (mt->hiz_buf) { + if (mt->hiz_buf->mt) { + aux_pitch = mt->hiz_buf->mt->pitch; + aux_qpitch = mt->hiz_buf->mt->qpitch; + } else { + aux_pitch = mt->hiz_buf->pitch; + aux_qpitch = mt->hiz_buf->qpitch; + } - /* Figure out the layout */ - if (_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT) { *usage = ISL_AUX_USAGE_HIZ; - } else if (mt->num_samples > 1) { - assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS); - *usage = ISL_AUX_USAGE_MCS; - } else if (intel_miptree_is_lossless_compressed(brw, mt)) { - assert(brw->gen >= 9); - *usage = ISL_AUX_USAGE_CCS_E; - } else if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_NO_MCS) { - *usage = ISL_AUX_USAGE_CCS_D; } else { - unreachable("Invalid MCS miptree"); + *usage = ISL_AUX_USAGE_NONE; + return; } + /* Start with a copy of the original surface. */ + intel_miptree_get_isl_surf(brw, mt, surf); + /* Figure out the format and tiling of the auxiliary surface */ switch (*usage) { case ISL_AUX_USAGE_NONE: - unreachable("Invalid MCS miptree"); + unreachable("Invalid auxiliary usage"); case ISL_AUX_USAGE_HIZ: - surf->format = ISL_FORMAT_HIZ; - surf->tiling = ISL_TILING_HIZ; - surf->usage = ISL_SURF_USAGE_HIZ_BIT; + isl_surf_get_hiz_surf(&brw->isl_dev, surf, surf); break; case ISL_AUX_USAGE_MCS: @@ -3216,16 +3297,7 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw, if (brw->gen >= 9) assert(mt->halign == 16); - surf->usage = ISL_SURF_USAGE_MCS_BIT; - - switch (mt->num_samples) { - case 2: surf->format = ISL_FORMAT_MCS_2X; break; - case 4: surf->format = ISL_FORMAT_MCS_4X; break; - case 8: surf->format = ISL_FORMAT_MCS_8X; break; - case 16: surf->format = ISL_FORMAT_MCS_16X; break; - default: - unreachable("Invalid number of samples"); - } + isl_surf_get_mcs_surf(&brw->isl_dev, surf, surf); break; case ISL_AUX_USAGE_CCS_D: @@ -3244,45 +3316,20 @@ intel_miptree_get_aux_isl_surf(struct brw_context *brw, if (brw->gen >= 8) assert(mt->halign == 16); - surf->tiling = ISL_TILING_CCS; - surf->usage = ISL_SURF_USAGE_CCS_BIT; - - if (brw->gen >= 9) { - assert(mt->tiling == I915_TILING_Y); - switch (_mesa_get_format_bytes(mt->format)) { - case 4: surf->format = ISL_FORMAT_GEN9_CCS_32BPP; break; - case 8: surf->format = ISL_FORMAT_GEN9_CCS_64BPP; break; - case 16: surf->format = ISL_FORMAT_GEN9_CCS_128BPP; break; - default: - unreachable("Invalid format size for color compression"); - } - } else if (mt->tiling == I915_TILING_Y) { - switch (_mesa_get_format_bytes(mt->format)) { - case 4: surf->format = ISL_FORMAT_GEN7_CCS_32BPP_Y; break; - case 8: surf->format = ISL_FORMAT_GEN7_CCS_64BPP_Y; break; - case 16: surf->format = ISL_FORMAT_GEN7_CCS_128BPP_Y; break; - default: - unreachable("Invalid format size for color compression"); - } - } else { - assert(mt->tiling == I915_TILING_X); - switch (_mesa_get_format_bytes(mt->format)) { - case 4: surf->format = ISL_FORMAT_GEN7_CCS_32BPP_X; break; - case 8: surf->format = ISL_FORMAT_GEN7_CCS_64BPP_X; break; - case 16: surf->format = ISL_FORMAT_GEN7_CCS_128BPP_X; break; - default: - unreachable("Invalid format size for color compression"); - } - } + isl_surf_get_ccs_surf(&brw->isl_dev, surf, surf); break; } + /* We want the pitch of the actual aux buffer. */ + surf->row_pitch = aux_pitch; + /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows * is in elements. This doesn't match intel_mipmap_tree::qpitch which is * in elements of the primary color surface so we have to divide by the * compression block height. */ - surf->array_pitch_el_rows = mt->qpitch / isl_format_get_layout(surf->format)->bh; + surf->array_pitch_el_rows = + aux_qpitch / isl_format_get_layout(surf->format)->bh; } union isl_color_value @@ -3291,7 +3338,12 @@ intel_miptree_get_isl_clear_color(struct brw_context *brw, { union isl_color_value clear_color; - if (brw->gen >= 9) { + if (_mesa_get_format_base_format(mt->format) == GL_DEPTH_COMPONENT) { + clear_color.i32[0] = mt->depth_clear_value; + clear_color.i32[1] = 0; + clear_color.i32[2] = 0; + clear_color.i32[3] = 0; + } else if (brw->gen >= 9) { clear_color.i32[0] = mt->gen9_fast_clear_color.i[0]; clear_color.i32[1] = mt->gen9_fast_clear_color.i[1]; clear_color.i32[2] = mt->gen9_fast_clear_color.i[2];